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transport/serial: Fix serial transport

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Fix a typo that broke the serial transport.

Change-Id: I7fcc97d505a5369f9f14d4a2abda92b7114a58cd
This commit is contained in:
Martin Hauke
2018-02-18 17:04:50 +01:00
parent d9d2b941eb
commit 6cbecaaf5c
1 changed files with 3 additions and 3 deletions
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6
pySim/transport/serial.py
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@@ -143,19 +143,19 @@ class SerialSimLink(LinkBase):
for i in range(4):
if t0 & (0x10 << i):
b = self._rx_byte()
self._atr.apend(ord(b))
self._atr.append(ord(b))
self._dbg_print("T%si = %x" % (chr(ord('A')+i), ord(b)))
for i in range(0, t0 & 0xf):
b = self._rx_byte()
self._atr.apend(ord(b))
self._atr.append(ord(b))
self._dbg_print("Historical = %x" % ord(b))
while True:
x = self._rx_byte()
if not x:
break
self._atr.apend(ord(x))
self._atr.append(ord(x))
self._dbg_print("Extra: %x" % ord(x))
return 1