catarrh/pysim
1
0
Fork 0
mirror of https://gitea.osmocom.org/sim-card/pysim.git synced 2026-03-17 02:48:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

fix various typos all over the code

Browse Source 
Change-Id: Ic8392a951bf94f67b51e35bed95d0e856f7a9250
This commit is contained in:
Harald Welte
2021-04-11 10:28:28 +02:00
parent 790b2709bd
commit c9cdce3e02
8 changed files with 29 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
docs/library.rst
View File

@@ -33,7 +33,7 @@ Transport base class
calypso / OsmocomBB transport
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This allows the use of the SIM slot of an an OsmocomBB compatible phone with the TI Calypso chipset,
This allows the use of the SIM slot of an OsmocomBB compatible phone with the TI Calypso chipset,
using the L1CTL interface to talk to the layer1.bin firmware on the phone.
.. automodule:: pySim.transport.calypso
@@ -67,7 +67,7 @@ Serial/UART transport
This transport implements interfacing smart cards via
very simplistic UART readers. These readers basically
wire together the Rx+Tx pins of a RS232 UART, provide
a fixed crystal oscilator for clock, and operate the UART
a fixed crystal oscillator for clock, and operate the UART
at 9600 bps. These readers are sometimes called `Phoenix`.
.. automodule:: pySim.transport.serial