Decode sigrok-iso7816-stream RST/VCC line events (GSMTAP 0x10/0x11)

Support the sigrok-iso7816-stream decoder (FX2 logic-analyzer passive
SIM sniffer, github.com/anttro/sigrok_iso7816_stream) which streams
GSMTAP-SIM on UDP 4729 and adds two custom sub-types for line events.

- gsmtap.py: GSMTAP_SIM_RST_EVENT (0x10) / GSMTAP_SIM_VCC_EVENT (0x11).
- capture.py: gsmtap_msg_type() maps 0x10→'rst', 0x11→'vcc' (shared by
  the listener and tests); pcap.py _SUB_TYPE_NAMES gains the same
  entries so PCAP re-imports of these captures preserve the events.
- decode.py: decode_line_event() decodes [direction, level, reserved]
  into reset asserted/de-asserted or power applied/removed + level;
  routed through decode_sniff_msg.
- database.py: reset-assert and power-removal invalidate the per-channel
  file selection (card-level transition); de-assert / power-on are
  markers only.
- frontend: RST/VCC labels (RESET ASSERTED / VCC OFF, …), a detail-view
  branch (Event + Level + raw), and list styling (.apdu-type.rst/.vcc).

README notes the custom sub-type compatibility. Tests: +8 (line-event
vectors, sniff routing, subtype + PCAP round-trip mappings) — 359
total. Version 1.21.0, SW cache simtrace-analyser-v31.

simtrace2_pysniff/server/database.py

@@ -377,5 +377,16 @@ class Database:
                 if msg['flags'] & (CHANGE_FLAG_CARD_INSERT | CHANGE_FLAG_CARD_EJECT |
                                    CHANGE_FLAG_RESET_ASSERT | CHANGE_FLAG_RESET_DEASSERT):
                     states = {}
+            elif msg['type'] in ('rst', 'vcc'):
+                # sigrok-iso7816-stream line events: a reset assert or power
+                # removal destroys the card's selection state.  De-assert /
+                # power-on are markers only (the following ATR resets state).
+                data = row[4] if len(row) > 4 and row[4] else b''
+                if msg['type'] == 'rst':
+                    if data and data[0] == 1:  # asserted
+                        states = {}
+                else:  # vcc
+                    if data and data[0] == 0:  # power removed
+                        states = {}
             msgs.append(msg)
         return msgs