From 7861132fad9eac55dee8138e5251b8b2bb05b440 Mon Sep 17 00:00:00 2001 From: Harald Welte Date: Thu, 12 Jan 2017 11:07:04 +0100 Subject: [PATCH] qmod: Don't violate PLL minimum output frequency Table 42-31 ofd DOC6500 states that the minimum output frequency of the PLL is 60 MHz. The existing qmod code violated this by configuring the PLL multiplier output to 12*4 = 48 MHz. Let's use 12*8 = 96 and then divide that by two to get to the desired 48 MHz. This might help to resolve the non-working USB on the qmod so far. --- firmware/src_board/board_lowlevel.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/firmware/src_board/board_lowlevel.c b/firmware/src_board/board_lowlevel.c index e2070018..8ab6db56 100644 --- a/firmware/src_board/board_lowlevel.c +++ b/firmware/src_board/board_lowlevel.c @@ -53,11 +53,11 @@ | CKGR_PLLAR_DIVA(0x5)) #define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK) #else /* qmod */ -/* QMod has 12 MHz clock, so multply by 4 and divide by 1 */ +/* QMod has 12 MHz clock, so multply by 8 (96 MHz) and divide by 2 */ #define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \ - | CKGR_PLLAR_MULA(4-1) \ + | CKGR_PLLAR_MULA(8-1) \ | CKGR_PLLAR_PLLACOUNT(0x1) \ - | CKGR_PLLAR_DIVA(1)) + | CKGR_PLLAR_DIVA(2)) #define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK) #endif /* Clock settings at 64MHz for 18 MHz crystal */