catarrh/simtrace2
1
0
Fork 0
mirror of https://gitea.osmocom.org/sim-card/simtrace2.git synced 2026-03-16 21:28:33 +03:00
Code Issues Packages Projects Releases Wiki Activity

Removed sym links, replaced them with actual folders

Browse Source
This commit is contained in:
Christina Quast
2015-04-07 19:57:44 +02:00
parent fbcd8a1bfd
commit b0bbb1b52e
47 changed files with 0 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1690
firmware/atmel_softpack_libraries/libchip_sam3s/source/USBD_HAL.c
View File

File diff suppressed because it is too large Load Diff

384
firmware/atmel_softpack_libraries/libchip_sam3s/source/exceptions.c
View File

@@ -1,384 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
* This file contains the default exception handlers.
*
* \note
* The exception handler has weak aliases.
* As they are weak aliases, any function with the same name will override
* this definition.
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Default interrupt handler for not used irq.
*/
void IrqHandlerNotUsed( void )
{
while ( 1 ) ;
}
/**
* \brief Default NMI interrupt handler.
*/
WEAK void NMI_Handler( void )
{
while ( 1 ) ;
}
/**
* \brief Default HardFault interrupt handler.
*/
WEAK void HardFault_Handler( void )
{
while ( 1 ) ;
}
/**
* \brief Default MemManage interrupt handler.
*/
WEAK void MemManage_Handler( void )
{
while ( 1 ) ;
}
/**
* \brief Default BusFault interrupt handler.
*/
WEAK void BusFault_Handler( void )
{
while ( 1 ) ;
}
/**
* \brief Default UsageFault interrupt handler.
*/
WEAK void UsageFault_Handler( void )
{
while ( 1 ) ;
}
/**
* \brief Default SVC interrupt handler.
*/
WEAK void SVC_Handler( void )
{
while ( 1 ) ;
}
/**
* \brief Default DebugMon interrupt handler.
*/
WEAK void DebugMon_Handler( void )
{
while ( 1 ) ;
}
/**
* \brief Default PendSV interrupt handler.
*/
WEAK void PendSV_Handler( void )
{
while ( 1 ) ;
}
/**
* \brief Default SysTick interrupt handler.
*/
WEAK void SysTick_Handler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for Supply Controller.
*/
WEAK void SUPC_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for Reset Controller.
*/
WEAK void RSTC_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for Real Time Clock.
*/
WEAK void RTC_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for Real Time Timer.
*/
WEAK void RTT_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for Watchdog Timer.
*/
WEAK void WDT_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for PMC.
*/
WEAK void PMC_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for EEFC.
*/
WEAK void EEFC_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for UART0.
*/
WEAK void UART0_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for UART1.
*/
WEAK void UART1_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for SMC.
*/
WEAK void SMC_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for PIOA Controller.
*/
WEAK void PIOA_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for PIOB Controller.
*/
WEAK void PIOB_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for PIOC Controller.
*/
WEAK void PIOC_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for USART0.
*/
WEAK void USART0_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for USART1.
*/
WEAK void USART1_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for MCI.
*/
WEAK void MCI_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for TWI0.
*/
WEAK void TWI0_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for TWI1.
*/
WEAK void TWI1_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for SPI.
*/
WEAK void SPI_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for SSC.
*/
WEAK void SSC_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for TC0.
*/
WEAK void TC0_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for TC1.
*/
WEAK void TC1_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default interrupt handler for TC2.
*/
WEAK void TC2_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default SUPC interrupt handler for TC3.
*/
WEAK void TC3_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default SUPC interrupt handler for TC4.
*/
WEAK void TC4_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default SUPC interrupt handler for TC5.
*/
WEAK void TC5_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default SUPC interrupt handler for ADC.
*/
WEAK void ADC_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default SUPC interrupt handler for DAC.
*/
WEAK void DAC_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default SUPC interrupt handler for PWM.
*/
WEAK void PWM_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default SUPC interrupt handler for CRCCU.
*/
WEAK void CRCCU_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default SUPC interrupt handler for ACC.
*/
WEAK void ACC_IrqHandler( void )
{
while ( 1 ) ;
}
/**
* \brief Default SUPC interrupt handler for USBD.
*/
WEAK void USBD_IrqHandler( void )
{
while ( 1 ) ;
}

453
firmware/atmel_softpack_libraries/libchip_sam3s/source/pio.c
View File

@@ -1,453 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2010, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include "pio.h"
#include "pmc.h"
/*----------------------------------------------------------------------------
* Local functions
*----------------------------------------------------------------------------*/
/**
* \brief Configures one or more pin(s) of a PIO controller as being controlled by
* peripheral A. Optionally, the corresponding internal pull-up(s) can be enabled.
*
* \param pio Pointer to a PIO controller.
* \param mask Bitmask of one or more pin(s) to configure.
* \param enablePullUp Indicates if the pin(s) internal pull-up shall be
* configured.
*/
static void PIO_SetPeripheralA(
Pio *pio,
unsigned int mask,
unsigned char enablePullUp)
{
unsigned int abcdsr;
/* Disable interrupts on the pin(s) */
pio->PIO_IDR = mask;
/* Enable the pull-up(s) if necessary */
if (enablePullUp) {
pio->PIO_PUER = mask;
}
else {
pio->PIO_PUDR = mask;
}
abcdsr = pio->PIO_ABCDSR[0];
pio->PIO_ABCDSR[0] &= (~mask & abcdsr);
abcdsr = pio->PIO_ABCDSR[1];
pio->PIO_ABCDSR[1] &= (~mask & abcdsr);
pio->PIO_PDR = mask;
}
/**
* \brief Configures one or more pin(s) of a PIO controller as being controlled by
* peripheral B. Optionally, the corresponding internal pull-up(s) can be enabled.
*
* \param pio Pointer to a PIO controller.
* \param mask Bitmask of one or more pin(s) to configure.
* \param enablePullUp Indicates if the pin(s) internal pull-up shall be
* configured.
*/
static void PIO_SetPeripheralB(
Pio *pio,
unsigned int mask,
unsigned char enablePullUp)
{
unsigned int abcdsr;
/* Disable interrupts on the pin(s) */
pio->PIO_IDR = mask;
/* Enable the pull-up(s) if necessary */
if (enablePullUp) {
pio->PIO_PUER = mask;
}
else {
pio->PIO_PUDR = mask;
}
abcdsr = pio->PIO_ABCDSR[0];
pio->PIO_ABCDSR[0] = (mask | abcdsr);
abcdsr = pio->PIO_ABCDSR[1];
pio->PIO_ABCDSR[1] &= (~mask & abcdsr);
pio->PIO_PDR = mask;
}
/**
* \brief Configures one or more pin(s) of a PIO controller as being controlled by
* peripheral C. Optionally, the corresponding internal pull-up(s) can be enabled.
*
* \param pio Pointer to a PIO controller.
* \param mask Bitmask of one or more pin(s) to configure.
* \param enablePullUp Indicates if the pin(s) internal pull-up shall be
* configured.
*/
static void PIO_SetPeripheralC(
Pio *pio,
unsigned int mask,
unsigned char enablePullUp)
{
unsigned int abcdsr;
/* Disable interrupts on the pin(s) */
pio->PIO_IDR = mask;
/* Enable the pull-up(s) if necessary */
if (enablePullUp) {
pio->PIO_PUER = mask;
}
else {
pio->PIO_PUDR = mask;
}
abcdsr = pio->PIO_ABCDSR[0];
pio->PIO_ABCDSR[0] &= (~mask & abcdsr);
abcdsr = pio->PIO_ABCDSR[1];
pio->PIO_ABCDSR[1] = (mask | abcdsr);
pio->PIO_PDR = mask;
}
/**
* \brief Configures one or more pin(s) of a PIO controller as being controlled by
* peripheral D. Optionally, the corresponding internal pull-up(s) can be enabled.
*
* \param pio Pointer to a PIO controller.
* \param mask Bitmask of one or more pin(s) to configure.
* \param enablePullUp Indicates if the pin(s) internal pull-up shall be
* configured.
*/
static void PIO_SetPeripheralD(
Pio *pio,
unsigned int mask,
unsigned char enablePullUp)
{
unsigned int abcdsr;
/* Disable interrupts on the pin(s) */
pio->PIO_IDR = mask;
/* Enable the pull-up(s) if necessary */
if (enablePullUp) {
pio->PIO_PUER = mask;
}
else {
pio->PIO_PUDR = mask;
}
abcdsr = pio->PIO_ABCDSR[0];
pio->PIO_ABCDSR[0] = (mask | abcdsr);
abcdsr = pio->PIO_ABCDSR[1];
pio->PIO_ABCDSR[1] = (mask | abcdsr);
pio->PIO_PDR = mask;
}
/**
* \brief Configures one or more pin(s) or a PIO controller as inputs. Optionally,
* the corresponding internal pull-up(s) and glitch filter(s) can be enabled.
*
* \param pio Pointer to a PIO controller.
* \param mask Bitmask indicating which pin(s) to configure as input(s).
* \param enablePullUp Indicates if the internal pull-up(s) must be enabled.
* \param enableFilter Indicates if the glitch filter(s) must be enabled.
*/
static void PIO_SetInput(
Pio *pio,
unsigned int mask,
unsigned char attribute)
{
/* Disable interrupts */
pio->PIO_IDR = mask;
/* Enable pull-up(s) if necessary */
if (attribute & PIO_PULLUP)
pio->PIO_PUER = mask;
else
pio->PIO_PUDR = mask;
/* Enable Input Filter if necessary */
if (attribute & (PIO_DEGLITCH | PIO_DEBOUNCE))
pio->PIO_IFER = mask;
else
pio->PIO_IFDR = mask;
/* Enable de-glitch or de-bounce if necessary */
if (attribute & PIO_DEGLITCH)
{
pio->PIO_IFSCDR = mask;
}
else
{
if (attribute & PIO_DEBOUNCE)
{
pio->PIO_IFSCER = mask;
}
}
/* Configure pin as input */
pio->PIO_ODR = mask;
pio->PIO_PER = mask;
}
/**
* \brief Configures one or more pin(s) of a PIO controller as outputs, with the
* given default value. Optionally, the multi-drive feature can be enabled
* on the pin(s).
*
* \param pio Pointer to a PIO controller.
* \param mask Bitmask indicating which pin(s) to configure.
* \param defaultValue Default level on the pin(s).
* \param enableMultiDrive Indicates if the pin(s) shall be configured as
* open-drain.
* \param enablePullUp Indicates if the pin shall have its pull-up activated.
*/
static void PIO_SetOutput(
Pio *pio,
unsigned int mask,
unsigned char defaultValue,
unsigned char enableMultiDrive,
unsigned char enablePullUp)
{
/* Disable interrupts */
pio->PIO_IDR = mask;
/* Enable pull-up(s) if necessary */
if (enablePullUp) {
pio->PIO_PUER = mask;
}
else {
pio->PIO_PUDR = mask;
}
/* Enable multi-drive if necessary */
if (enableMultiDrive) {
pio->PIO_MDER = mask;
}
else {
pio->PIO_MDDR = mask;
}
/* Set default value */
if (defaultValue) {
pio->PIO_SODR = mask;
}
else {
pio->PIO_CODR = mask;
}
/* Configure pin(s) as output(s) */
pio->PIO_OER = mask;
pio->PIO_PER = mask;
}
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
/**
* \brief Configures a list of Pin instances, each of which can either hold a single
* pin or a group of pins, depending on the mask value; all pins are configured
* by this function. The size of the array must also be provided and is easily
* computed using PIO_LISTSIZE whenever its length is not known in advance.
*
* \param list Pointer to a list of Pin instances.
* \param size Size of the Pin list (calculated using PIO_LISTSIZE).
*
* \return 1 if the pins have been configured properly; otherwise 0.
*/
uint8_t PIO_Configure( const Pin *list, uint32_t size )
{
/* Configure pins */
while ( size > 0 )
{
switch ( list->type )
{
case PIO_PERIPH_A:
PIO_SetPeripheralA(list->pio,
list->mask,
(list->attribute & PIO_PULLUP) ? 1 : 0);
break;
case PIO_PERIPH_B:
PIO_SetPeripheralB(list->pio,
list->mask,
(list->attribute & PIO_PULLUP) ? 1 : 0);
break;
case PIO_PERIPH_C:
PIO_SetPeripheralC(list->pio,
list->mask,
(list->attribute & PIO_PULLUP) ? 1 : 0);
break;
case PIO_PERIPH_D:
PIO_SetPeripheralD(list->pio,
list->mask,
(list->attribute & PIO_PULLUP) ? 1 : 0);
break;
case PIO_INPUT:
PMC_EnablePeripheral(list->id);
PIO_SetInput(list->pio,
list->mask,
list->attribute);
break;
case PIO_OUTPUT_0:
case PIO_OUTPUT_1:
PIO_SetOutput(list->pio,
list->mask,
(list->type == PIO_OUTPUT_1),
(list->attribute & PIO_OPENDRAIN) ? 1 : 0,
(list->attribute & PIO_PULLUP) ? 1 : 0);
break;
default: return 0;
}
list++;
size--;
}
return 1;
}
/**
* \brief Sets a high output level on all the PIOs defined in the given Pin instance.
* This has no immediate effects on PIOs that are not output, but the PIO
* controller will memorize the value they are changed to outputs.
*
* \param pin Pointer to a Pin instance describing one or more pins.
*/
void PIO_Set(const Pin *pin)
{
pin->pio->PIO_SODR = pin->mask;
}
/**
* \brief Sets a low output level on all the PIOs defined in the given Pin instance.
* This has no immediate effects on PIOs that are not output, but the PIO
* controller will memorize the value they are changed to outputs.
*
* \param pin Pointer to a Pin instance describing one or more pins.
*/
void PIO_Clear(const Pin *pin)
{
pin->pio->PIO_CODR = pin->mask;
}
/**
* \brief Returns 1 if one or more PIO of the given Pin instance currently have
* a high level; otherwise returns 0. This method returns the actual value that
* is being read on the pin. To return the supposed output value of a pin, use
* PIO_GetOutputDataStatus() instead.
*
* \param pin Pointer to a Pin instance describing one or more pins.
*
* \return 1 if the Pin instance contains at least one PIO that currently has
* a high level; otherwise 0.
*/
unsigned char PIO_Get( const Pin *pin )
{
unsigned int reg ;
if ( (pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1) )
{
reg = pin->pio->PIO_ODSR ;
}
else
{
reg = pin->pio->PIO_PDSR ;
}
if ( (reg & pin->mask) == 0 )
{
return 0 ;
}
else
{
return 1 ;
}
}
/**
* \brief Returns 1 if one or more PIO of the given Pin are configured to output a
* high level (even if they are not output).
* To get the actual value of the pin, use PIO_Get() instead.
*
* \param pin Pointer to a Pin instance describing one or more pins.
*
* \return 1 if the Pin instance contains at least one PIO that is configured
* to output a high level; otherwise 0.
*/
unsigned char PIO_GetOutputDataStatus(const Pin *pin)
{
if ((pin->pio->PIO_ODSR & pin->mask) == 0) {
return 0;
}
else {
return 1;
}
}
/*
* \brief Configures Glitch or Debouncing filter for input.
*
* \param pin Pointer to a Pin instance describing one or more pins.
* \param cuttoff Cutt off frequency for debounce filter.
*/
void PIO_SetDebounceFilter( const Pin *pin, uint32_t cuttoff )
{
Pio *pio = pin->pio;
pio->PIO_IFSCER = pin->mask; /* set Debouncing, 0 bit field no effect */
pio->PIO_SCDR = ((32678/(2*(cuttoff))) - 1) & 0x3FFF; /* the lowest 14 bits work */
}

283
firmware/atmel_softpack_libraries/libchip_sam3s/source/pio_capture.c
View File

@@ -1,283 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2010, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup pio_capture_module Working with PIO Parallel Capture Mode
* The PIO Parallel Capture Mode driver provides the interface to configure and use the
* PIO Parallel Capture Mode peripheral.\n
*
* The PIO Controller integrates an interface able to read data from a CMOS digital
* image sensor, a high-speed parallel ADC, a DSP synchronous port in synchronous
* mode, etc.... For better understanding and to ease reading, the following
* description uses an example with a CMOS digital image sensor
*
* To use the PIO Parallel Capture, the user has to follow these few steps:
* <ul>
* <li> Enable PIOA peripheral clock </li>
* <li> Configure the PDC </li>
* <li> Configure the PIO Capture interrupt </li>
* <li> Enable the PDC </li>
* <li> Enable the PIO Capture </li>
* <li> Wait for interrupt </li>
* <li> Disable the interrupt </li>
* <li> Read the DATA </li>
* </ul>
*
* For more accurate information, please look at the PIO Parallel Capture Mode section of the
* Datasheet.
*
* Related files :\n
* \ref pio_capture.c\n
* \ref pio_capture.h\n
*/
/*@{*/
/*@}*/
/**
* \file
*
* Implementation of PIO Parallel Capture.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include <assert.h>
/*----------------------------------------------------------------------------
* Local Functions
*----------------------------------------------------------------------------*/
/** Copy the API structure for interrupt handler */
static SpioCaptureInit* _PioCaptureCopy;
/*----------------------------------------------------------------------------
* Global Functions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/**
* \brief The PIO_CaptureHandler must be called by the PIO Capture Interrupt
* Service Routine with the corresponding PIO Capture instance.
*/
/*----------------------------------------------------------------------------*/
extern void PIO_CaptureHandler( void )
{
volatile uint32_t pio_captureSr;
/* Read the status register*/
pio_captureSr = PIOA->PIO_PCISR ;
pio_captureSr &= PIOA->PIO_PCIMR ;
if (pio_captureSr & PIO_PCISR_DRDY)
{
/* Parallel Capture Mode Data Ready */
if ( _PioCaptureCopy->CbkDataReady != NULL )
{
_PioCaptureCopy->CbkDataReady( _PioCaptureCopy );
}
else
{
TRACE_DEBUG("IT PIO Capture Data Ready received (no callback)\n\r");
}
}
if (pio_captureSr & PIO_PCISR_OVRE)
{
/* Parallel Capture Mode Overrun Error */
if ( _PioCaptureCopy->CbkOverrun != NULL )
{
_PioCaptureCopy->CbkOverrun( _PioCaptureCopy );
}
else
{
TRACE_DEBUG("IT PIO Capture Overrun Error received (no callback)\n\r");
}
}
if (pio_captureSr & PIO_PCISR_RXBUFF)
{
/* Reception Buffer Full */
if ( _PioCaptureCopy->CbkBuffFull != NULL )
{
_PioCaptureCopy->CbkBuffFull( _PioCaptureCopy );
}
else
{
TRACE_DEBUG("IT PIO Capture Reception Buffer Full received (no callback)\n\r");
}
}
if (pio_captureSr & PIO_PCISR_ENDRX)
{
/* End of Reception Transfer */
if ( _PioCaptureCopy->CbkEndReception != NULL )
{
_PioCaptureCopy->CbkEndReception( _PioCaptureCopy );
}
else
{
TRACE_DEBUG("IT PIO Capture End of Reception Transfer received (no callback)\n\r");
}
}
}
/*----------------------------------------------------------------------------*/
/**
* \brief Disable Interupt of the PIO Capture
* \param itToDisable : Interrupt to disable
*/
/*----------------------------------------------------------------------------*/
void PIO_CaptureDisableIt( uint32_t itToDisable )
{
/* Parallel capture mode is enabled */
PIOA->PIO_PCIDR = itToDisable;
}
/*----------------------------------------------------------------------------*/
/**
* \brief Enable Interupt of the PIO Capture
* \param itToEnable : Interrupt to enable
*/
/*----------------------------------------------------------------------------*/
void PIO_CaptureEnableIt( uint32_t itToEnable )
{
/* Parallel capture mode is enabled */
PIOA->PIO_PCIER = itToEnable;
}
/*----------------------------------------------------------------------------*/
/**
* \brief Enable the PIO Capture
*/
/*----------------------------------------------------------------------------*/
void PIO_CaptureEnable( void )
{
/* PDC: Receive Pointer Register */
PIOA->PIO_RPR = (uint32_t)_PioCaptureCopy->pData ;
/* PDC: Receive Counter Register */
/* Starts peripheral data transfer if corresponding channel is active */
PIOA->PIO_RCR = PIO_RCR_RXCTR(_PioCaptureCopy->dPDCsize) ;
/* Parallel capture mode is enabled */
PIOA->PIO_PCMR |= PIO_PCMR_PCEN ;
}
/*----------------------------------------------------------------------------*/
/**
* \brief Disable the PIO Capture
*/
/*----------------------------------------------------------------------------*/
void PIO_CaptureDisable( void )
{
/* Parallel capture mode is disabled */
PIOA->PIO_PCMR &= (uint32_t)(~PIO_PCMR_PCEN) ;
}
/*----------------------------------------------------------------------------*/
/**
* \brief Initialize the PIO Capture
* Be careful to configure the PDC before enable interrupt on pio capture.
* Otherway, the pdc will go in interrupt handler continuously.
* \param dsize :
* 0 = The reception data in the PIO_PCRHR register is a BYTE (8-bit).
* 1 = The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit).
* 2/3 = The reception data in the PIO_PCRHR register is a WORD (32-bit).
* \param alwaysSampling: ALWYS: Parallel Capture Mode Always Sampling
* 0 = The parallel capture mode samples the data when both data enables are active.
* 1 = The parallel capture mode samples the data whatever the data enables are.
* \param halfSampling: HALFS: Parallel Capture Mode Half Sampling
* 0 = The parallel capture mode samples all the data.
* 1 = The parallel capture mode samples the data only one time out of two.
* \param modeFirstSample: FRSTS: Parallel Capture Mode First Sample
* This bit is useful only if the HALFS bit is set to 1. If data are numbered
* in the order that they are received with an index from 0 to n:
* 0 = Only data with an even index are sampled.
* 1 = Only data with an odd index are sampled.
*/
/*----------------------------------------------------------------------------*/
void PIO_CaptureInit( SpioCaptureInit *pInit )
{
PMC_EnablePeripheral( ID_PIOA );
assert( (pInit->dsize < 0x4) ) ;
assert( (pInit->dPDCsize <= PIO_RPR_RXPTR_Msk) ) ;
assert( (pInit->alwaysSampling < 2) );
assert( (pInit->halfSampling < 2) );
assert( (pInit->modeFirstSample < 2) );
/* PDC: Transfer Control Register */
/* Disables the PDC transmitter channel requests */
PIOA->PIO_PTCR = PIO_PTCR_RXTDIS;
/* PDC: Receive Pointer Register */
PIOA->PIO_RPR = (uint32_t)pInit->pData;
/* PDC: Receive Counter Register */
/* Starts peripheral data transfer if corresponding channel is active */
PIOA->PIO_RCR = PIO_RCR_RXCTR(pInit->dPDCsize);
/* PDC: Transfer Control Register */
/* Enables PDC receiver channel requests if RXTDIS is not set */
PIOA->PIO_PTCR = PIO_PTCR_RXTEN ;
/* Copy the API structure for interrupt handler */
_PioCaptureCopy = pInit;
/* PIO Parallel Capture Mode */
PIOA->PIO_PCMR = PIO_PCMR_DSIZE(pInit->dsize)
| ((pInit->alwaysSampling<<9) & PIO_PCMR_ALWYS)
| ((pInit->halfSampling<<10) & PIO_PCMR_HALFS)
| ((pInit->modeFirstSample<<11) & PIO_PCMR_FRSTS);
if ( pInit->CbkDataReady != NULL )
{
PIOA->PIO_PCIER = PIO_PCISR_DRDY;
}
if ( pInit->CbkOverrun != NULL )
{
PIOA->PIO_PCIER = PIO_PCISR_OVRE;
}
if ( pInit->CbkEndReception != NULL )
{
PIOA->PIO_PCIER = PIO_PCISR_ENDRX;
}
if ( pInit->CbkBuffFull != NULL )
{
PIOA->PIO_PCIER = PIO_PCISR_RXBUFF;
}
// else
// {
// TRACE_INFO("No interruption, no callback\n\r");
// }
}

315
firmware/atmel_softpack_libraries/libchip_sam3s/source/pio_it.c
View File

@@ -1,315 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*
* \file
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include <assert.h>
/*----------------------------------------------------------------------------
* Local definitions
*----------------------------------------------------------------------------*/
/* Maximum number of interrupt sources that can be defined. This
* constant can be increased, but the current value is the smallest possible
* that will be compatible with all existing projects. */
#define MAX_INTERRUPT_SOURCES 7
/*----------------------------------------------------------------------------
* Local types
*----------------------------------------------------------------------------*/
/**
* Describes a PIO interrupt source, including the PIO instance triggering the
* interrupt and the associated interrupt handler.
*/
typedef struct _InterruptSource
{
/* Pointer to the source pin instance. */
const Pin *pPin;
/* Interrupt handler. */
void (*handler)( const Pin* ) ;
} InterruptSource ;
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/* List of interrupt sources. */
static InterruptSource _aIntSources[MAX_INTERRUPT_SOURCES] ;
/* Number of currently defined interrupt sources. */
static uint32_t _dwNumSources = 0;
/*----------------------------------------------------------------------------
* Local Functions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/**
* \brief Stub, to handling all PIO Capture interrupts, if not defined.
*/
/*----------------------------------------------------------------------------*/
//extern WEAK void PIO_CaptureHandler( void )
//{
//}
/**
* \brief Handles all interrupts on the given PIO controller.
* \param id PIO controller ID.
* \param pPio PIO controller base address.
*/
extern void PioInterruptHandler( uint32_t id, Pio *pPio )
{
uint32_t status;
uint32_t i;
/* Read PIO controller status */
status = pPio->PIO_ISR;
status &= pPio->PIO_IMR;
/* Check pending events */
if ( status != 0 )
{
TRACE_DEBUG( "PIO interrupt on PIO controller #%" PRIu32 "\n\r", id ) ;
/* Find triggering source */
i = 0;
while ( status != 0 )
{
/* There cannot be an unconfigured source enabled. */
assert(i < _dwNumSources);
/* Source is configured on the same controller */
if (_aIntSources[i].pPin->id == id)
{
/* Source has PIOs whose statuses have changed */
if ( (status & _aIntSources[i].pPin->mask) != 0 )
{
TRACE_DEBUG( "Interrupt source #%" PRIu32 " triggered\n\r", i ) ;
_aIntSources[i].handler(_aIntSources[i].pPin);
status &= ~(_aIntSources[i].pPin->mask);
}
}
i++;
}
}
}
/*----------------------------------------------------------------------------
* Global Functions
*----------------------------------------------------------------------------*/
/**
* \brief Parallel IO Controller A interrupt handler
* \Redefined PIOA interrupt handler for NVIC interrupt table.
*/
extern void PIOA_IrqHandler( void )
{
if ( PIOA->PIO_PCISR != 0 )
{
PIO_CaptureHandler() ;
}
PioInterruptHandler( ID_PIOA, PIOA ) ;
}
/**
* \brief Parallel IO Controller B interrupt handler
* \Redefined PIOB interrupt handler for NVIC interrupt table.
*/
extern void PIOB_IrqHandler( void )
{
PioInterruptHandler( ID_PIOB, PIOB ) ;
}
/**
* \brief Parallel IO Controller C interrupt handler
* \Redefined PIOC interrupt handler for NVIC interrupt table.
*/
extern void PIOC_IrqHandler( void )
{
PioInterruptHandler( ID_PIOC, PIOC ) ;
}
/**
* \brief Initializes the PIO interrupt management logic
*
* The desired priority of PIO interrupts must be provided.
* Calling this function multiple times result in the reset of currently
* configured interrupts.
*
* \param priority PIO controller interrupts priority.
*/
extern void PIO_InitializeInterrupts( uint32_t dwPriority )
{
TRACE_DEBUG( "PIO_Initialize()\n\r" ) ;
/* Reset sources */
_dwNumSources = 0 ;
/* Configure PIO interrupt sources */
TRACE_DEBUG( "PIO_Initialize: Configuring PIOA\n\r" ) ;
PMC_EnablePeripheral( ID_PIOA ) ;
PIOA->PIO_ISR ;
PIOA->PIO_IDR = 0xFFFFFFFF ;
NVIC_DisableIRQ( PIOA_IRQn ) ;
NVIC_ClearPendingIRQ( PIOA_IRQn ) ;
NVIC_SetPriority( PIOA_IRQn, dwPriority ) ;
NVIC_EnableIRQ( PIOA_IRQn ) ;
TRACE_DEBUG( "PIO_Initialize: Configuring PIOB\n\r" ) ;
PMC_EnablePeripheral( ID_PIOB ) ;
PIOB->PIO_ISR ;
PIOB->PIO_IDR = 0xFFFFFFFF ;
NVIC_DisableIRQ( PIOB_IRQn ) ;
NVIC_ClearPendingIRQ( PIOB_IRQn ) ;
NVIC_SetPriority( PIOB_IRQn, dwPriority ) ;
NVIC_EnableIRQ( PIOB_IRQn ) ;
TRACE_DEBUG( "PIO_Initialize: Configuring PIOC\n\r" ) ;
PMC_EnablePeripheral( ID_PIOC ) ;
PIOC->PIO_ISR ;
PIOC->PIO_IDR = 0xFFFFFFFF ;
NVIC_DisableIRQ( PIOC_IRQn ) ;
NVIC_ClearPendingIRQ( PIOC_IRQn ) ;
NVIC_SetPriority( PIOC_IRQn, dwPriority ) ;
NVIC_EnableIRQ( PIOC_IRQn ) ;
}
/**
* Configures a PIO or a group of PIO to generate an interrupt on status
* change. The provided interrupt handler will be called with the triggering
* pin as its parameter (enabling different pin instances to share the same
* handler).
* \param pPin Pointer to a Pin instance.
* \param handler Interrupt handler function pointer.
*/
extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) )
{
Pio* pio ;
InterruptSource* pSource ;
TRACE_DEBUG( "PIO_ConfigureIt()\n\r" ) ;
assert( pPin ) ;
pio = pPin->pio ;
assert( _dwNumSources < MAX_INTERRUPT_SOURCES ) ;
/* Define new source */
TRACE_DEBUG( "PIO_ConfigureIt: Defining new source #%" PRIu32 ".\n\r", _dwNumSources ) ;
pSource = &(_aIntSources[_dwNumSources]) ;
pSource->pPin = pPin ;
pSource->handler = handler ;
_dwNumSources++ ;
/* PIO3 with additional interrupt support
* Configure additional interrupt mode registers */
if ( pPin->attribute & PIO_IT_AIME )
{
// enable additional interrupt mode
pio->PIO_AIMER = pPin->mask ;
// if bit field of selected pin is 1, set as Rising Edge/High level detection event
if ( pPin->attribute & PIO_IT_RE_OR_HL )
{
pio->PIO_REHLSR = pPin->mask ;
}
else
{
pio->PIO_FELLSR = pPin->mask;
}
/* if bit field of selected pin is 1, set as edge detection source */
if (pPin->attribute & PIO_IT_EDGE)
pio->PIO_ESR = pPin->mask;
else
pio->PIO_LSR = pPin->mask;
}
else
{
/* disable additional interrupt mode */
pio->PIO_AIMDR = pPin->mask;
}
}
/**
* Enables the given interrupt source if it has been configured. The status
* register of the corresponding PIO controller is cleared prior to enabling
* the interrupt.
* \param pPin Interrupt source to enable.
*/
extern void PIO_EnableIt( const Pin *pPin )
{
TRACE_DEBUG( "PIO_EnableIt()\n\r" ) ;
assert( pPin != NULL ) ;
#ifndef NOASSERT
uint32_t i = 0;
uint32_t dwFound = 0;
while ( (i < _dwNumSources) && !dwFound )
{
if ( _aIntSources[i].pPin == pPin )
{
dwFound = 1 ;
}
i++ ;
}
assert( dwFound != 0 ) ;
#endif
pPin->pio->PIO_ISR;
pPin->pio->PIO_IER = pPin->mask ;
}
/**
* Disables a given interrupt source, with no added side effects.
*
* \param pPin Interrupt source to disable.
*/
extern void PIO_DisableIt( const Pin *pPin )
{
assert( pPin != NULL ) ;
TRACE_DEBUG( "PIO_DisableIt()\n\r" ) ;
pPin->pio->PIO_IDR = pPin->mask;
}

168
firmware/atmel_softpack_libraries/libchip_sam3s/source/pmc.c
View File

@@ -1,168 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include "trace.h"
#include <assert.h>
/*----------------------------------------------------------------------------
* Local definitions
*----------------------------------------------------------------------------*/
#define MASK_STATUS0 0xFFFFFFFC
#define MASK_STATUS1 0xFFFFFFFF
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Enables the clock of a peripheral. The peripheral ID is used
* to identify which peripheral is targetted.
*
* \note The ID must NOT be shifted (i.e. 1 << ID_xxx).
*
* \param id Peripheral ID (ID_xxx).
*/
extern void PMC_EnablePeripheral( uint32_t dwId )
{
assert( dwId < 35 ) ;
if ( dwId < 32 )
{
if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) )
{
TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral" " %" PRIu32 " is already enabled\n\r", dwId ) ;
}
else
{
PMC->PMC_PCER0 = 1 << dwId ;
}
}
else
{
dwId -= 32;
if ((PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId))
{
TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral" " %" PRIu32 " is already enabled\n\r", dwId + 32 ) ;
}
else
{
PMC->PMC_PCER1 = 1 << dwId ;
}
}
}
/**
* \brief Disables the clock of a peripheral. The peripheral ID is used
* to identify which peripheral is targetted.
*
* \note The ID must NOT be shifted (i.e. 1 << ID_xxx).
*
* \param id Peripheral ID (ID_xxx).
*/
extern void PMC_DisablePeripheral( uint32_t dwId )
{
assert( dwId < 35 ) ;
if ( dwId < 32 )
{
if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) )
{
TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %" PRIu32 " is not enabled\n\r", dwId ) ;
}
else
{
PMC->PMC_PCDR0 = 1 << dwId ;
}
}
else
{
dwId -= 32 ;
if ( (PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) )
{
TRACE_DEBUG( "PMC_DisablePeripheral: clock of peripheral" " %" PRIu32 " is not enabled\n\r", dwId + 32 ) ;
}
else
{
PMC->PMC_PCDR1 = 1 << dwId ;
}
}
}
/**
* \brief Enable all the periph clock via PMC.
*/
extern void PMC_EnableAllPeripherals( void )
{
PMC->PMC_PCER0 = MASK_STATUS0 ;
while ( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0 ) ;
PMC->PMC_PCER1 = MASK_STATUS1 ;
while ( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1 ) ;
TRACE_DEBUG( "Enable all periph clocks\n\r" ) ;
}
/**
* \brief Disable all the periph clock via PMC.
*/
extern void PMC_DisableAllPeripherals( void )
{
PMC->PMC_PCDR0 = MASK_STATUS0 ;
while ( (PMC->PMC_PCSR0 & MASK_STATUS0) != 0 ) ;
PMC->PMC_PCDR1 = MASK_STATUS1 ;
while ( (PMC->PMC_PCSR1 & MASK_STATUS1) != 0 ) ;
TRACE_DEBUG( "Disable all periph clocks\n\r" ) ;
}
/**
* \brief Get Periph Status for the given peripheral ID.
*
* \param id Peripheral ID (ID_xxx).
*/
extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId )
{
assert( dwId < 35 ) ;
if ( dwId < 32 )
{
return ( PMC->PMC_PCSR0 & (1 << dwId) ) ;
}
else {
return ( PMC->PMC_PCSR1 & (1 << (dwId - 32)) ) ;
}
}

352
firmware/atmel_softpack_libraries/libchip_sam3s/source/spi.c
View File

@@ -1,352 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup spi_module Working with SPI
* The SPI driver provides the interface to configure and use the SPI
* peripheral.
*
* The Serial Peripheral Interface (SPI) circuit is a synchronous serial
* data link that provides communication with external devices in Master
* or Slave Mode.
*
* To use the SPI, the user has to follow these few steps:
* -# Enable the SPI pins required by the application (see pio.h).
* -# Configure the SPI using the \ref SPI_Configure(). This enables the
* peripheral clock. The mode register is loaded with the given value.
* -# Configure all the necessary chip selects with \ref SPI_ConfigureNPCS().
* -# Enable the SPI by calling \ref SPI_Enable().
* -# Send/receive data using \ref SPI_Write() and \ref SPI_Read(). Note that \ref SPI_Read()
* must be called after \ref SPI_Write() to retrieve the last value read.
* -# Send/receive data using the PDC with the \ref SPI_WriteBuffer() and
* \ref SPI_ReadBuffer() functions.
* -# Disable the SPI by calling \ref SPI_Disable().
*
* For more accurate information, please look at the SPI section of the
* Datasheet.
*
* Related files :\n
* \ref spi.c\n
* \ref spi.h.\n
*/
/*@{*/
/*@}*/
/**
* \file
*
* Implementation of Serial Peripheral Interface (SPI) controller.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include "pmc.h"
#include "spi.h"
#include <stdint.h>
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Enables a SPI peripheral.
*
* \param spi Pointer to an Spi instance.
*/
extern void SPI_Enable( Spi* spi )
{
spi->SPI_CR = SPI_CR_SPIEN ;
}
/**
* \brief Disables a SPI peripheral.
*
* \param spi Pointer to an Spi instance.
*/
extern void SPI_Disable( Spi* spi )
{
spi->SPI_CR = SPI_CR_SPIDIS ;
}
/**
* \brief Enables one or more interrupt sources of a SPI peripheral.
*
* \param spi Pointer to an Spi instance.
* \param sources Bitwise OR of selected interrupt sources.
*/
extern void SPI_EnableIt( Spi* spi, uint32_t dwSources )
{
spi->SPI_IER = dwSources ;
}
/**
* \brief Disables one or more interrupt sources of a SPI peripheral.
*
* \param spi Pointer to an Spi instance.
* \param sources Bitwise OR of selected interrupt sources.
*/
extern void SPI_DisableIt( Spi* spi, uint32_t dwSources )
{
spi->SPI_IDR = dwSources ;
}
/**
* \brief Configures a SPI peripheral as specified. The configuration can be computed
* using several macros (see \ref spi_configuration_macros).
*
* \param spi Pointer to an Spi instance.
* \param id Peripheral ID of the SPI.
* \param configuration Value of the SPI configuration register.
*/
extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration )
{
PMC_EnablePeripheral( dwId ) ;
spi->SPI_CR = SPI_CR_SPIDIS ;
/* Execute a software reset of the SPI twice */
spi->SPI_CR = SPI_CR_SWRST ;
spi->SPI_CR = SPI_CR_SWRST ;
spi->SPI_MR = dwConfiguration ;
}
/**
* \brief Configures a chip select of a SPI peripheral. The chip select configuration
* is computed using several macros (see \ref spi_configuration_macros).
*
* \param spi Pointer to an Spi instance.
* \param npcs Chip select to configure (0, 1, 2 or 3).
* \param configuration Desired chip select configuration.
*/
void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration )
{
spi->SPI_CSR[dwNpcs] = dwConfiguration ;
}
/**
* \brief Get the current status register of the given SPI peripheral.
* \note This resets the internal value of the status register, so further
* read may yield different values.
* \param spi Pointer to a Spi instance.
* \return SPI status register.
*/
extern uint32_t SPI_GetStatus( Spi* spi )
{
return spi->SPI_SR ;
}
/**
* \brief Reads and returns the last word of data received by a SPI peripheral. This
* method must be called after a successful SPI_Write call.
*
* \param spi Pointer to an Spi instance.
*
* \return readed data.
*/
extern uint32_t SPI_Read( Spi* spi )
{
while ( (spi->SPI_SR & SPI_SR_RDRF) == 0 ) ;
return spi->SPI_RDR & 0xFFFF ;
}
/**
* \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed
* peripheral select, the npcs value is meaningless. Otherwise, it identifies
* the component which shall be addressed.
*
* \param spi Pointer to an Spi instance.
* \param npcs Chip select of the component to address (0, 1, 2 or 3).
* \param data Word of data to send.
*/
extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData )
{
/* Send data */
while ( (spi->SPI_SR & SPI_SR_TXEMPTY) == 0 ) ;
spi->SPI_TDR = wData | SPI_PCS( dwNpcs ) ;
while ( (spi->SPI_SR & SPI_SR_TDRE) == 0 ) ;
}
/**
* \brief Check if SPI transfer finish.
*
* \param spi Pointer to an Spi instance.
*
* \return Returns 1 if there is no pending write operation on the SPI; otherwise
* returns 0.
*/
extern uint32_t SPI_IsFinished( Spi* spi )
{
return ((spi->SPI_SR & SPI_SR_TXEMPTY) != 0) ;
}
/**
* \brief Enable Spi PDC transmit
* \param spi Pointer to an Spi instance.
*/
extern void SPI_PdcEnableTx( Spi* spi )
{
spi->SPI_PTCR = SPI_PTCR_TXTEN ;
}
/**
* \brief Disable Spi PDC transmit
* \param spi Pointer to an Spi instance.
*/
extern void SPI_PdcDisableTx( Spi* spi )
{
spi->SPI_PTCR = SPI_PTCR_TXTDIS ;
}
/**
* \brief Enable Spi PDC receive
* \param spi Pointer to an Spi instance.
*/
extern void SPI_PdcEnableRx( Spi* spi )
{
spi->SPI_PTCR = SPI_PTCR_RXTEN ;
}
/**
* \brief Disable Spi PDC receive
* \param spi Pointer to an Spi instance.
*/
extern void SPI_PdcDisableRx( Spi* spi )
{
spi->SPI_PTCR = SPI_PTCR_RXTDIS ;
}
/**
* \brief Set PDC transmit and next transmit buffer address and size.
*
* \param spi Pointer to an Spi instance.
* \param txBuf PDC transmit buffer address.
* \param txCount Length in bytes of the transmit buffer.
* \param txNextBuf PDC next transmit buffer address.
* \param txNextCount Length in bytes of the next transmit buffer.
*/
extern void SPI_PdcSetTx( Spi* spi, void* pvTxBuf, uint32_t dwTxCount, void* pvTxNextBuf, uint32_t dwTxNextCount )
{
spi->SPI_TPR = (uint32_t)pvTxBuf ;
spi->SPI_TCR = dwTxCount ;
spi->SPI_TNPR = (uint32_t)pvTxNextBuf ;
spi->SPI_TNCR = dwTxNextCount ;
}
/**
* \brief Set PDC receive and next receive buffer address and size.
*
* \param spi Pointer to an Spi instance.
* \param rxBuf PDC receive buffer address.
* \param rxCount Length in bytes of the receive buffer.
* \param rxNextBuf PDC next receive buffer address.
* \param rxNextCount Length in bytes of the next receive buffer.
*/
extern void SPI_PdcSetRx( Spi* spi, void* pvRxBuf, uint32_t dwRxCount, void* pvRxNextBuf, uint32_t dwRxNextCount )
{
spi->SPI_RPR = (uint32_t)pvRxBuf ;
spi->SPI_RCR = dwRxCount ;
spi->SPI_RNPR = (uint32_t)pvRxNextBuf ;
spi->SPI_RNCR = dwRxNextCount ;
}
/**
* \brief Sends the contents of buffer through a SPI peripheral, using the PDC to
* take care of the transfer.
*
* \param spi Pointer to an Spi instance.
* \param buffer Data buffer to send.
* \param length Length of the data buffer.
*/
extern uint32_t SPI_WriteBuffer( Spi* spi, void* pvBuffer, uint32_t dwLength )
{
/* Check if first bank is free */
if ( spi->SPI_TCR == 0 )
{
spi->SPI_TPR = (uint32_t)pvBuffer ;
spi->SPI_TCR = dwLength ;
spi->SPI_PTCR = PERIPH_PTCR_TXTEN ;
return 1 ;
}
/* Check if second bank is free */
else
{
if ( spi->SPI_TNCR == 0 )
{
spi->SPI_TNPR = (uint32_t)pvBuffer ;
spi->SPI_TNCR = dwLength ;
return 1 ;
}
}
/* No free banks */
return 0 ;
}
/**
* \brief Reads data from a SPI peripheral until the provided buffer is filled. This
* method does NOT need to be called after SPI_Write or SPI_WriteBuffer.
*
* \param spi Pointer to an Spi instance.
* \param buffer Data buffer to store incoming bytes.
* \param length Length in bytes of the data buffer.
*/
extern uint32_t SPI_ReadBuffer( Spi* spi, void *pvBuffer, uint32_t dwLength )
{
/* Check if the first bank is free */
if ( spi->SPI_RCR == 0 )
{
spi->SPI_RPR = (uint32_t)pvBuffer ;
spi->SPI_RCR = dwLength ;
spi->SPI_PTCR = PERIPH_PTCR_RXTEN ;
return 1 ;
}
/* Check if second bank is free */
else
{
if ( spi->SPI_RNCR == 0 )
{
spi->SPI_RNPR = (uint32_t)pvBuffer ;
spi->SPI_RNCR = dwLength ;
return 1 ;
}
}
/* No free bank */
return 0 ;
}

175
firmware/atmel_softpack_libraries/libchip_sam3s/source/tc.c
View File

@@ -1,175 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implementation of Timer Counter (TC).
*
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "chip.h"
#include <assert.h>
/*------------------------------------------------------------------------------
* Global functions
*------------------------------------------------------------------------------*/
/**
* \brief Configures a Timer Counter Channel
*
* Configures a Timer Counter to operate in the given mode. Timer is stopped
* after configuration and must be restarted with TC_Start(). All the
* interrupts of the timer are also disabled.
*
* \param pTc Pointer to a Tc instance.
* \param channel Channel number.
* \param mode Operating mode (TC_CMR value).
*/
extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode )
{
TcChannel* pTcCh ;
assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;
pTcCh = pTc->TC_CHANNEL+dwChannel ;
/* Disable TC clock */
pTcCh->TC_CCR = TC_CCR_CLKDIS ;
/* Disable interrupts */
pTcCh->TC_IDR = 0xFFFFFFFF ;
/* Clear status register */
pTcCh->TC_SR ;
/* Set mode */
pTcCh->TC_CMR = dwMode ;
}
/**
* \brief Reset and Start the TC Channel
*
* Enables the timer clock and performs a software reset to start the counting.
*
* \param pTc Pointer to a Tc instance.
* \param dwChannel Channel number.
*/
extern void TC_Start( Tc *pTc, uint32_t dwChannel )
{
TcChannel* pTcCh ;
assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;
pTcCh = pTc->TC_CHANNEL+dwChannel ;
pTcCh->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG ;
}
/**
* \brief Stop TC Channel
*
* Disables the timer clock, stopping the counting.
*
* \param pTc Pointer to a Tc instance.
* \param dwChannel Channel number.
*/
extern void TC_Stop(Tc *pTc, uint32_t dwChannel )
{
TcChannel* pTcCh ;
assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;
pTcCh = pTc->TC_CHANNEL+dwChannel ;
pTcCh->TC_CCR = TC_CCR_CLKDIS ;
}
/**
* \brief Find best MCK divisor
*
* Finds the best MCK divisor given the timer frequency and MCK. The result
* is guaranteed to satisfy the following equation:
* \code
* (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)
* \endcode
* with DIV being the highest possible value.
*
* \param dwFreq Desired timer frequency.
* \param dwMCk Master clock frequency.
* \param dwDiv Divisor value.
* \param dwTcClks TCCLKS field value for divisor.
* \param dwBoardMCK Board clock frequency.
*
* \return 1 if a proper divisor has been found, otherwise 0.
*/
extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK )
{
const uint32_t adwDivisors[5] = { 2, 8, 32, 128, dwBoardMCK / 32768 } ;
uint32_t dwIndex = 0 ;
/* Satisfy lower bound */
while ( dwFreq < ((dwMCk / adwDivisors[dwIndex]) / 65536) )
{
dwIndex++ ;
/* If no divisor can be found, return 0 */
if ( dwIndex == (sizeof( adwDivisors )/sizeof( adwDivisors[0] )) )
{
return 0 ;
}
}
/* Try to maximize DIV while satisfying upper bound */
while ( dwIndex < 4 )
{
if ( dwFreq > (dwMCk / adwDivisors[dwIndex + 1]) )
{
break ;
}
dwIndex++ ;
}
/* Store results */
if ( dwDiv )
{
*dwDiv = adwDivisors[dwIndex] ;
}
if ( dwTcClks )
{
*dwTcClks = dwIndex ;
}
return 1 ;
}

410
firmware/atmel_softpack_libraries/libchip_sam3s/source/usart.c
View File

@@ -1,410 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup usart_module Working with USART
* The USART driver provides the interface to configure and use the USART peripheral.\n
*
* The USART supports several kinds of comminication modes such as full-duplex asynchronous/
* synchronous serial commnunication,RS485 with driver control signal,ISO7816,SPI and Test modes.
*
* To start a USART transfer with \ref AT91SAM3S_PDC "PDC" support, the user could follow these steps:
* <ul>
* <li> Configure USART with expected mode and baudrate(see \ref USART_Configure), which could be done by:
* -# Resetting and disabling transmitter and receiver by setting US_CR(Control Register). </li>
* -# Conifguring the USART in a specific mode by setting USART_MODE bits in US_MR(Mode Register) </li>
* -# Setting baudrate which is different from mode to mode.
</li>
* <li> Enable transmitter or receiver respectively by set US_CR_TXEN or US_CR_RXEN in US_CR.</li>
* <li> Read from or write to the peripheral with \ref USART_ReadBuffer or \ref USART_WriteBuffer.
These operations could be done by polling or interruption. </li>
* <li> For polling, check the status bit US_CSR_ENDRX/US_CSR_RXBUFF (READ) or US_CSR_ENDTX/
US_CSR_TXBUFE (WRITE). </li>
* <li> For interruption,"enable" the status bit through US_IER and
realize the hanler with USARTx_IrqHandler according to IRQ vector
table which is defined in board_cstartup_<toolchain>.c
To enable the interruption of USART,it should be configured with priority and enabled first through
NVIC .</li>
* </ul>
*
* For more accurate information, please look at the USART section of the
* Datasheet.
*
* Related files :\n
* \ref usart.c\n
* \ref usart.h\n
*/
/**
* \file
*
* Implementation of USART (Universal Synchronous Asynchronous Receiver Transmitter)
* controller.
*
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "chip.h"
#include "trace.h"
#include <assert.h>
#include <string.h>
/*----------------------------------------------------------------------------
* Local definitions
*----------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
/**
* \brief Configures an USART peripheral with the specified parameters.
*
*
* \param usart Pointer to the USART peripheral to configure.
* \param mode Desired value for the USART mode register (see the datasheet).
* \param baudrate Baudrate at which the USART should operate (in Hz).
* \param masterClock Frequency of the system master clock (in Hz).
*/
void USART_Configure(Usart *usart,
uint32_t mode,
uint32_t baudrate,
uint32_t masterClock)
{
/* Reset and disable receiver & transmitter*/
usart->US_CR = US_CR_RSTRX | US_CR_RSTTX
| US_CR_RXDIS | US_CR_TXDIS;
/* Configure mode*/
usart->US_MR = mode;
/* Configure baudrate*/
/* Asynchronous, no oversampling*/
if ( ((mode & US_MR_SYNC) == 0) && ((mode & US_MR_OVER) == 0) )
{
usart->US_BRGR = (masterClock / baudrate) / 16;
}
if( ((mode & US_MR_USART_MODE_SPI_MASTER) == US_MR_USART_MODE_SPI_MASTER)
|| ((mode & US_MR_SYNC) == US_MR_SYNC))
{
if( (mode & US_MR_USCLKS_Msk) == US_MR_USCLKS_MCK)
{
usart->US_BRGR = masterClock / baudrate;
}
else
{
if ( (mode & US_MR_USCLKS_DIV) == US_MR_USCLKS_DIV)
{
usart->US_BRGR = masterClock / baudrate / 8;
}
}
}
/* TODO other modes*/
}
/**
* \brief Enables or disables the transmitter of an USART peripheral.
*
*
* \param usart Pointer to an USART peripheral
* \param enabled If true, the transmitter is enabled; otherwise it is
* disabled.
*/
void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled)
{
if (enabled) {
usart->US_CR = US_CR_TXEN;
}
else {
usart->US_CR = US_CR_TXDIS;
}
}
/**
* \brief Enables or disables the receiver of an USART peripheral
*
*
* \param usart Pointer to an USART peripheral
* \param enabled If true, the receiver is enabled; otherwise it is disabled.
*/
void USART_SetReceiverEnabled(Usart *usart,
uint8_t enabled)
{
if (enabled) {
usart->US_CR = US_CR_RXEN;
}
else {
usart->US_CR = US_CR_RXDIS;
}
}
/**
* \brief Sends one packet of data through the specified USART peripheral. This
* function operates synchronously, so it only returns when the data has been
* actually sent.
*
*
* \param usart Pointer to an USART peripheral.
* \param data Data to send including 9nth bit and sync field if necessary (in
* the same format as the US_THR register in the datasheet).
* \param timeOut Time out value (0 = no timeout).
*/
void USART_Write(
Usart *usart,
uint16_t data,
volatile uint32_t timeOut)
{
if (timeOut == 0) {
while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
}
else {
while ((usart->US_CSR & US_CSR_TXEMPTY) == 0) {
if (timeOut == 0) {
TRACE_ERROR("USART_Write: Timed out.\n\r");
return;
}
timeOut--;
}
}
usart->US_THR = data;
}
/**
* \brief Sends the contents of a data buffer through the specified USART peripheral.
* This function returns immediately (1 if the buffer has been queued, 0
* otherwise); poll the ENDTX and TXBUFE bits of the USART status register
* to check for the transfer completion.
*
* \param usart Pointer to an USART peripheral.
* \param buffer Pointer to the data buffer to send.
* \param size Size of the data buffer (in bytes).
*/
uint8_t USART_WriteBuffer(
Usart *usart,
void *buffer,
uint32_t size)
{
/* Check if the first PDC bank is free*/
if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) {
usart->US_TPR = (uint32_t) buffer;
usart->US_TCR = size;
usart->US_PTCR = US_PTCR_TXTEN;
return 1;
}
/* Check if the second PDC bank is free*/
else if (usart->US_TNCR == 0) {
usart->US_TNPR = (uint32_t) buffer;
usart->US_TNCR = size;
return 1;
}
else {
return 0;
}
}
/**
* \brief Reads and return a packet of data on the specified USART peripheral. This
* function operates asynchronously, so it waits until some data has been
* received.
*
* \param usart Pointer to an USART peripheral.
* \param timeOut Time out value (0 -> no timeout).
*/
uint16_t USART_Read(
Usart *usart,
volatile uint32_t timeOut)
{
if (timeOut == 0) {
while ((usart->US_CSR & US_CSR_RXRDY) == 0);
}
else {
while ((usart->US_CSR & US_CSR_RXRDY) == 0) {
if (timeOut == 0) {
TRACE_ERROR( "USART_Read: Timed out.\n\r" ) ;
return 0;
}
timeOut--;
}
}
return usart->US_RHR;
}
/**
* \brief Reads data from an USART peripheral, filling the provided buffer until it
* becomes full. This function returns immediately with 1 if the buffer has
* been queued for transmission; otherwise 0.
*
* \param usart Pointer to an USART peripheral.
* \param buffer Pointer to the buffer where the received data will be stored.
* \param size Size of the data buffer (in bytes).
*/
uint8_t USART_ReadBuffer(Usart *usart,
void *buffer,
uint32_t size)
{
/* Check if the first PDC bank is free*/
if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) {
usart->US_RPR = (uint32_t) buffer;
usart->US_RCR = size;
usart->US_PTCR = US_PTCR_RXTEN;
return 1;
}
/* Check if the second PDC bank is free*/
else if (usart->US_RNCR == 0) {
usart->US_RNPR = (uint32_t) buffer;
usart->US_RNCR = size;
return 1;
}
else {
return 0;
}
}
/**
* \brief Returns 1 if some data has been received and can be read from an USART;
* otherwise returns 0.
*
* \param usart Pointer to an Usart instance.
*/
uint8_t USART_IsDataAvailable(Usart *usart)
{
if ((usart->US_CSR & US_CSR_RXRDY) != 0) {
return 1;
}
else {
return 0;
}
}
/**
* \brief Sets the filter value for the IRDA demodulator.
*
* \param pUsart Pointer to an Usart instance.
* \param filter Filter value.
*/
void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter)
{
assert( pUsart != NULL ) ;
pUsart->US_IF = filter;
}
/**
* \brief Sends one packet of data through the specified USART peripheral. This
* function operates synchronously, so it only returns when the data has been
* actually sent.
*
* \param usart Pointer to an USART peripheral.
* \param c Character to send
*/
void USART_PutChar(
Usart *usart,
uint8_t c)
{
/* Wait for the transmitter to be ready*/
while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
/* Send character*/
usart->US_THR = c;
/* Wait for the transfer to complete*/
while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
}
/**
* \brief Return 1 if a character can be read in USART
*/
uint32_t USART_IsRxReady(Usart *usart)
{
return (usart->US_CSR & US_CSR_RXRDY);
}
/**
* \brief Get present status
*/
uint32_t USART_GetStatus(Usart *usart)
{
return usart->US_CSR;
}
/**
* \brief Enable interrupt
*/
void USART_EnableIt(Usart *usart,uint32_t mode)
{
usart->US_IER = mode;
}
/**
* \brief Disable interrupt
*/
void USART_DisableIt(Usart *usart,uint32_t mode)
{
usart->US_IDR = mode;
}
/**
* \brief Reads and returns a character from the USART.
*
* \note This function is synchronous (i.e. uses polling).
* \param usart Pointer to an USART peripheral.
* \return Character received.
*/
uint8_t USART_GetChar(Usart *usart)
{
while ((usart->US_CSR & US_CSR_RXRDY) == 0);
return usart->US_RHR;
}

132
firmware/atmel_softpack_libraries/libchip_sam3s/source/wdt.c
View File

@@ -1,132 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implementation of Watchdog Timer (WDT) controller.
*
*/
/** \addtogroup wdt_module Working with WDT
* The WDT driver provides the interface to configure and use the WDT
* peripheral.
*
* The WDT can be used to prevent system lock-up if the software becomes
* trapped in a deadlock. It can generate a general reset or a processor
* reset only. It is clocked by slow clock divided by 128.
*
* The WDT is running at reset with 16 seconds watchdog period (slow clock at 32.768 kHz)
* and external reset generation enabled. The user must either disable it or
* reprogram it to meet the application requires.
*
* To use the WDT, the user could follow these few steps:
* <ul>
* <li>Enable watchdog with given mode using \ref WDT_Enable().
* <li>Restart the watchdog using \ref WDT_Restart() within the watchdog period.
* </ul>
*
* For more accurate information, please look at the WDT section of the
* Datasheet.
*
* \note
* The Watchdog Mode Register (WDT_MR) can be written only once.\n
*
* Related files :\n
* \ref wdt.c\n
* \ref wdt.h.\n
*/
/*@{*/
/*@}*/
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include "chip.h"
#include <stdint.h>
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Enable watchdog with given mode.
*
* \note The Watchdog Mode Register (WDT_MR) can be written only once.
* Only a processor reset resets it.
*
* \param dwMode WDT mode to be set
*/
extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode )
{
pWDT->WDT_MR = dwMode ;
}
/**
* \brief Disable watchdog.
*
* \note The Watchdog Mode Register (WDT_MR) can be written only once.
* Only a processor reset resets it.
*/
extern void WDT_Disable( Wdt* pWDT )
{
pWDT->WDT_MR = WDT_MR_WDDIS;
}
/**
* \brief Watchdog restart.
*/
extern void WDT_Restart( Wdt* pWDT )
{
pWDT->WDT_CR = 0xA5000001;
}
/**
* \brief Watchdog get status.
*/
extern uint32_t WDT_GetStatus( Wdt* pWDT )
{
return (pWDT->WDT_SR & 0x3) ;
}
/**
* \brief Watchdog get period.
*
* \param dwMs desired watchdog period in millisecond.
*/
extern uint32_t WDT_GetPeriod( uint32_t dwMs )
{
if ( (dwMs < 4) || (dwMs > 16000) )
{
return 0 ;
}
return ((dwMs << 8) / 1000) ;
}