This adds an unconditional endpoint reset procedure to every SET_FEATURE(UnHalt).
It doesn't really make sense that this is required, *particularly* as
we *MUST NOT* set bEndpoint->bank to 0 here.
Without this patch, I'm observing the following problem:
Every first OUT transfer after a SET_INTERFACE + UNHALT on a bulk endpoint
is lost. "lost" means that it completes successfully on the host, can
be seen completing successfully with an ACK on a USB bus analyzer,
but still doesn't show up in the firmware. No Endpoint Interrupt
is generated.
This can be reproduced by calling libusb_set_interface_alt_setting()
from the host and then submitting a single OUT transfer.
Change-Id: I18ed530e617baddf76e8f9829512443ce2a76e0d
This should help debug watchdog triggers. Also reduce the timer to 1s
to hopefully increase the chance of triggering it.
Change-Id: Ie3f47e5612cdf501abff8cb6954600b785b3a3fa
When the uC firmware starts, assert the (high-active) _RESET GPIOs,
which will cause the transistors to drive the mPCIe slot !PERST
low.
There is of course a short instance of time between the uC reset
until it executes wwan_perst_init(). To avoid this, a hardware
pull-up would have to be re-worked onto the _RESET[1..4] signals
on the PCBA
Change-Id: I8742fefa4bf02e728e34d5d8cbc0fda771e78ffb
SIMtrace should reject any card activation at 1.8V as it is a 3[.3]V device
without level shifters. For this, we must include the ADC in
determining the VCC voltage.
Change-Id: Ic76f06037590ff1c0dae818d5eb2c2019dd75f2d
FIXME: reporting uses raw ADC voltage, not the voltage before divider
Particularly the VCC/RST/CLK changes can happen quite frequent, and
we were seeing quite a number of overflows of the usb_buf queue for EP06
(interrupt endpoint) in cardem.
I first tried increasing the maximum queue size to up to 10, but that
still didn't resolve those EP06 overflow error log messages.
Reducing the bInterval from 16 to 1 made them go away in all my
tests.
Change-Id: I5c272c31983de7201cfbd445c4484f6832d878ab
the ISO7816 UARTs have highest priority, while console has lowest.
remaining sources (USB, ADC, GPIO) are in between.
Change-Id: Ie6c97d61d8da3990b6e44144f36cb6d37d194307
This is what we do in all other functions, not sure why this one
wants to silently ignore any such programming errors.
Change-Id: I022eee86a5a3b5077abe59897161578ed960f1b1
The SIMtrace2 protocol alwasy contained a field for the VCC voltage,
the cardem firmware just never populated that field, even on those
boards that use the ADC to determine its voltage.
Change-Id: Idcecad553fb36380e916378e1420488acbbfa8e3
Add new board.h definition BOARD_MAINOSC_BYPASS to configure the clock module to use an external oscillator rather than a crystal. The qmod board is one such board.
Change-Id: If62f55cd4c8b0cf758534f09d25a9bcb028814a7
DFU flashing of apps sometimes aborts, and although rare this leads to
broken devices if no boot button or serial/jtag access exists, because
the bootloader will keep trying to start a half-flashed app that then
crashes at some point.
The easiest fix that works with existing bootloaders is to prepend a
small 512 byte stub that calculcates the crc and compares it with the
crc calculated at build time, and then either starts the actual app, or
sets the dfu flag and resets. This ensures we either have a working,
running app, or end up in the bootloader, ready to flash again.
For obvious reasons this only applies to dfu apps, and not to flash
targets like the actual bootloader itself.
Change-Id: Id6df0486c8b779889d21800dc2441b3aa9af8a5f
Remove the paragraph about writing to the Free Software Foundation's
mailing address. The FSF has changed addresses in the past, and may do
so again. In 2021 this is not useful, let's rather have a bit less
boilerplate at the start of source files.
Change-Id: Ie0a3b2273383adbb3303faffd6ff96be7f4cae99
The previous value was way too low and led to reenumeration issues when
switching from app to bl because the hosts are fairly lenient and
feature long delays until they accept disappearing devices as gone for
good instead of ignoring a presuambly flaky usb cable or connection.
Related: SYS5061
Change-Id: I9b8c8bf794ad5b94fc7ea2a01d1ebf4e36862c36
All the parts are DNP and never existed on the simtrace2 with sam3; the
sam3 has internal pullups that are part of the usb peripheral.
Change-Id: I04a703a2eba6ff1dc64692c089213389d0c1066d
This bl updater can be flashed as app and will update the bootloader and
then
delete itself before resetting the sam3, so the device will end up in
the newly
updated dfu bootloader afterwards, without having to press the
bootloader button
or requring any other manual interaction, ready to receive a new
application image.
Building the blupdater requires a previously built dfu-flash bootloader
bin file that
will then be embedded into the app during building.
Related: OS#1704
Related: SYS5061
Change-Id: I53dea57bba790a2ab3245d9483e0ff1c8d19d5e3
This led to occasional crashes for targets with leds since it was
introduced 3 years ago
The interesting thing is that most of the time it didn't crash...
Change-Id: Ia6a1b1fc0e44a301b4fb1d9c9fdbc27d61dcab97
Supposed to be used with https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm
+ distro provided binutils-arm-none-eabi package, might provide better and more reliable
binary sizes, especially for the bootloader.
Just run USE_CLANG=1 make
Change-Id: I1a19f40d44797efad5c46121e73115ed738a095b
This reverts commit e6a76c7bf4.
Might or might not cause weird issues depending on gcc and binutils
versions, let's see if this helps.
Change-Id: I2f593fd5e0f1494aae6b9fcfb2160a6c9168f5b8
We keep running out of rom space, so reduce tracing to nothing for alle
dfu targets, and let's hope newer gcc versions stop producing more
code...
Change-Id: I7d2947c84097035bed00ad489a175d614b4c388e
The "wait time extension timer" was apparently not being reset during
normal tx operations, which led to occasional NULL (0x60) bytes getting
injected into transfers, which in turn led to more tx bytes than what
the reader side expects...
The odd thing is that this was only noticeable with high baud rates,
probably due to the very long default WT of 9600 ETU, and even then only
because it led to weird ngff modem resets after benign transfers.
Change-Id: I15b0b83b7d93b8e5589f3640bd6eb2fc82f93394
Related: SYS#5553
Single threaded evaluation is (assumed to be!) left to right, depth
first - but with concurrent make using -j this breaks, because the
actual usb string header is generated after the attempt to concurrently
compile the code that needs it, since there is no explicit order among
the all: dependencies.
This is fixed by properly adding a dependency on that header.
Change-Id: I0bdf915deabeda861f6398e654764918e58a64c2
This adds support for the new ngff_cardem board, a board that
basically combines a ngff breakout board with a built-in SIMtrace2.
Cardem works, but depending on the modem it might need a adjusted ATR to
ensure a lower baud rate is used by the modem, high rates might lead
to weird power cycling of the card after a few transfers.
Trace was also tested and appears to work as expected.
Change-Id: Ia96124fbe8a752c98e7fd4096d542a3b2b9bc255
The tester has shifters, while the original simtrace relies upon the
reader restarting the powerup attempt with > 1v8 after not respondig due
to a lack of shifters and therefore 1v8 support.
Change-Id: I520aa26c6e0fb34568a4f632943efa59a0da831c
Back in I8c9b0c3d862a967832134b24252577739182da62 we added support
for enabling the card_insert signal, but not for explicit disable
of it. Let's fix that.
Change-Id: I6f32bde60674119c9912e51059a53b5ee74d074a
The octsimtest board can control the card-insert contact of the OCTSIM
under test via an external I2C gpio multiplexer; let's add support for
that.
Change-Id: I8c9b0c3d862a967832134b24252577739182da62
* driver should not have hard-coded understanding about I/O directions
* board code should pass the I/O direction to driver
* board code should use the correct I/O directions (A0..7, B0: output)
Change-Id: Id4a8e012a33cee01bb489e612e17920760b9be59
octsimtest has a resistive voltage divider in front of the VCC ADC
in order to also detect 5V. We must make the thresholds board-specific
and adjust them for octsimtest.
Change-Id: I9e4adb4f349d2d838ea4100eb49271f3a0e7a2a5
Contrary to other hardware designs, octsimtest has a level-shifter in
the I/O line to support testing with 1.8, 3 and 5V. This level shifter
is bi-directional, but the direction needs to be explicitly specified
via the SIM_IO_DIR signal attached to PA26.
Change-Id: I44171363b5bd69d6049b12c86f8143be83557cb2
* code for controlling the Card slot + frequencyt divider muxes
* put everything in place to build cardem application for it
Change-Id: I7e03e0c0f2999a1ce2dad966d98e22033fa58465
The octsimtest board only supports cardem mode, not 'ccid'
nor 'sniffer'. Remove related GPIO pin #defines from board.h
Change-Id: I43e8631d945ba183a1e5b1e37dd4565adb377154
likewise, enable HAVE_SNIFFER currently only if we build the sniffer
firmware.
It's been many years too long to finally get those all merged in one
firmware :(
Change-Id: Ib433f180746f75458a44f4988643465bd846b04b
As we store the waiting time (WT) in 'etu', we must adjust the formula
from ISO 7816-3. The 'Fi' component in the formula only exists to
compute clock cycles from the etu, which we don't need here.
Without this patch, the waiting time would be way too large (by a factor
of 372 in the default case).
Change-Id: Ia21bc7303f9b38834b5b1753983ed2a99bfc7d95
Related: OS#1704
The existing code started the timer once (and expired once) but didn't
properly handle re-starting of the timer. Neither did it handle
the 'half time expiration' case. If we want to call a function after
half the WT expiring, we must of course program the hardware for half
the timeout, and not the full timeout...
Change-Id: Ia999d97f835c27597fcd1cf7ac78bac0ab9c98c1
Related: OS#1704
Instead of using the timer/counter peripheral to handle the waiting time
and corresponding timeout, the USART peripheral internal timeout
mechanism is used.
This is particularly important for the SIMtrace board since there
(contrary to other boards) the I/O signal is not wired to a TIO pin
of the timer/counter block, and hence Rx/Tx data cannot reset that
timer/counter.
As a result of this migration, cardem is now supported not only on
owhw + qmod, but also on the simtrace board.
The guts of this change have been lifted out of Change-Id
Ibcb2c8cace9137695adf5fb3de43566f7cfb93b5 by Kevin Redon, which was
unfortunately touching various different topics at the same time and
hence was split up. Some improvements are the introduction of the
ENABLE_TX_TIMER_ONLY mode, which avoids the USART interrupt handler
getting hammered with TXRDY between release of RST and start of the ATR.
Change-Id: Ibcb2c8cace9137695adf5fb3de43566f7cfb93b5
Related: OS#1704
Those are already initialized at various transitions of the master
7816 FSM, but let's properly initialize them at start-up, too.
Change-Id: I81b2a8ef3284559164700d94717e4ccf008f53df
