mirror of
https://gitea.osmocom.org/sim-card/simtrace2.git
synced 2026-03-17 05:38:33 +03:00
disabling the ERASE pin prevents accidental erase for the flash memory while the board is powered on (e.g. in case the user overcomes the weak 100 kOhm pull-down for more than 220 ms by touching or shorting the pin). the flash is still erasable using the ERASE pin during power up. it is only disabled after boot completed. Change-Id: Ic3332eb1d4247a07988b2fd841f40e79862d06a7
221 lines
7.9 KiB
C
221 lines
7.9 KiB
C
/* ----------------------------------------------------------------------------
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* ATMEL Microcontroller Software Support
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* ----------------------------------------------------------------------------
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* Copyright (c) 2009, Atmel Corporation
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* Copyright (c) 2018, sysmocom -s.f.m.c. GmbH, Author: Kevin Redon <kredon@sysmocom.de>
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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/**
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* \file
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*
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* Provides the low-level initialization function that called on chip startup.
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*/
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/*----------------------------------------------------------------------------
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* Headers
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*----------------------------------------------------------------------------*/
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#include "board.h"
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/*----------------------------------------------------------------------------
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* Local definitions
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*----------------------------------------------------------------------------*/
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#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
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#define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
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/** configure PLL to generate main clock based on main oscillator frequency */
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#if (BOARD_MAINOSC == 12000000) && (BOARD_MCK == 48000000)
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(8-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(2))
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#elif (BOARD_MAINOSC == 12000000) && (BOARD_MCK == 58000000)
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(29-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(6))
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#elif (BOARD_MAINOSC == 12000000) && (BOARD_MCK == 60000000)
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(10-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(2))
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#elif (BOARD_MAINOSC == 18432000) && (BOARD_MCK == 47923200)
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(13-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(5))
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#elif (BOARD_MAINOSC == 18432000) && (BOARD_MCK == 58982400)
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(16-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(5))
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#elif (BOARD_MAINOSC == 18432000) && (BOARD_MCK == 64512000)
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(7-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(2))
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#else
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#error "Please define PLLA config for your BOARD_MCK/MAINOSC frequency"
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#endif
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#if (BOARD_MAINOSC == 12000000)
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#define PLLB_CFG (CKGR_PLLBR_DIVB(2)|CKGR_PLLBR_MULB(8-1)|CKGR_PLLBR_PLLBCOUNT_Msk)
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#elif (BOARD_MAINOSC == 18432000)
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#define PLLB_CFG (CKGR_PLLBR_DIVB(5)|CKGR_PLLBR_MULB(13-1)|CKGR_PLLBR_PLLBCOUNT_Msk)
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#else
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#error "Please configure PLLB for your MAINOSC freq"
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#endif
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/* Define clock timeout */
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#define CLOCK_TIMEOUT 0xFFFFFFFF
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/**
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* \brief Configure 48MHz Clock for USB
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*/
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static void _ConfigureUsbClock(void)
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{
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/* Enable PLLB for USB */
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PMC->CKGR_PLLBR = PLLB_CFG;
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while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0) ;
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/* USB Clock uses PLLB */
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PMC->PMC_USB = PMC_USB_USBDIV(0) /* /1 (no divider) */
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| PMC_USB_USBS; /* PLLB */
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}
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/*----------------------------------------------------------------------------
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* Exported functions
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*----------------------------------------------------------------------------*/
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/**
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* \brief Performs the low-level initialization of the chip.
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* This includes EFC and master clock configuration.
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* It also enable a low level on the pin NRST triggers a user reset.
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*/
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extern WEAK void LowLevelInit( void )
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{
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uint32_t timeout = 0;
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/* Configure the Supply Monitor to reset the CPU in case VDDIO is
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* lower than 3.0V. As we run the board on 3.3V, any lower voltage
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* might be some kind of leakage that creeps in some way, but is not
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* the "official" power supply */
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SUPC->SUPC_SMMR = SUPC_SMMR_SMTH_3_0V | SUPC_SMMR_SMSMPL_CSM |
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SUPC_SMMR_SMRSTEN_ENABLE;
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/* disable ERASE pin to prevent accidental flash erase */
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MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12;
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/* enable both LED and green LED */
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PIOA->PIO_PER |= PIO_LED_RED | PIO_LED_GREEN;
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PIOA->PIO_OER |= PIO_LED_RED | PIO_LED_GREEN;
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PIOA->PIO_CODR |= PIO_LED_RED | PIO_LED_GREEN;
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/* Set 3 FWS for Embedded Flash Access */
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EFC->EEFC_FMR = EEFC_FMR_FWS(3);
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/* Select external slow clock */
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/* if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST)
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{
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SUPC->SUPC_CR = (uint32_t)(SUPC_CR_XTALSEL_CRYSTAL_SEL | SUPC_CR_KEY(0xA5));
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timeout = 0;
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while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST) );
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}
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*/
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#ifndef qmod
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/* Initialize main oscillator */
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if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
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{
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PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
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timeout = 0;
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while (!(PMC->PMC_SR & PMC_SR_MOSCXTS) && (timeout++ < CLOCK_TIMEOUT));
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}
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/* Switch to 3-20MHz Xtal oscillator */
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PIOB->PIO_PDR = (1 << 8) | (1 << 9);
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PIOB->PIO_PUDR = (1 << 8) | (1 << 9);
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PIOB->PIO_PPDDR = (1 << 8) | (1 << 9);
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PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
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/* wait for Main XTAL oscillator stabilization */
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timeout = 0;
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while (!(PMC->PMC_SR & PMC_SR_MOSCSELS) && (timeout++ < CLOCK_TIMEOUT));
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#else
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/* QMOD has external 12MHz clock source */
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PIOB->PIO_PDR = (1 << 9);
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PIOB->PIO_PUDR = (1 << 9);
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PIOB->PIO_PPDDR = (1 << 9);
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PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTBY| CKGR_MOR_MOSCSEL;
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#endif
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/* disable the red LED after main clock initialization */
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PIOA->PIO_SODR = PIO_LED_RED;
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/* "switch" to main clock as master clock source (should already be the case */
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PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
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/* wait for master clock to be ready */
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for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; );
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/* Initialize PLLA */
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PMC->CKGR_PLLAR = BOARD_PLLAR;
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/* Wait for PLLA to lock */
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timeout = 0;
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while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT));
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/* Switch to main clock (again ?!?) */
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PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
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/* wait for master clock to be ready */
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for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; );
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/* switch to PLLA as master clock source */
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PMC->PMC_MCKR = BOARD_MCKR ;
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/* wait for master clock to be ready */
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for ( timeout = 0; !(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT) ; );
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/* Configure SysTick for 1ms */
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SysTick_Config(BOARD_MCK/1000);
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_ConfigureUsbClock();
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}
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/* SysTick based delay function */
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volatile uint32_t jiffies;
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/* Interrupt handler for SysTick interrupt */
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void SysTick_Handler(void)
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{
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jiffies++;
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}
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void mdelay(unsigned int msecs)
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{
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uint32_t jiffies_start = jiffies;
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do {
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} while ((jiffies - jiffies_start) < msecs);
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}
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