From ed0666863b40ea458af8265e03bcece8cf1182fa Mon Sep 17 00:00:00 2001 From: Andrew Gillham Date: Thu, 5 Oct 2023 22:32:52 -0500 Subject: [PATCH] Rearrange the repository and add a library.properties file to make this installable as a .ZIP library in the Arduino IDE. --- LICENSE | 2 +- README.md | 11 ++++++++++ .../logic_analyzer}/logic_analyzer.ino | 4 ++-- .../logic_analyzer_inline_2mhz.ino | 2 +- .../logic_analyzer_inline_4mhz.ino | 2 +- .../logic_analyzer_leonardo}/Makefile | 0 .../logic_analyzer_inline_2mhz.ino | 2 +- .../logic_analyzer_inline_4mhz.ino | 2 +- .../logic_analyzer_leonardo.ino | 4 ++-- .../logic_analyzer_inline_2mhz.ino | 0 .../logic_analyzer_inline_4mhz.ino | 0 .../logic_analyzer_sigrok.ino | 4 ++-- .../ols.profile-agla.cfg | 0 .../ols.profile-aglam.cfg | 0 library.properties | 9 ++++++++ logic_analyzer/LICENSE | 22 ------------------- logic_analyzer_leonardo/LICENSE | 22 ------------------- logic_analyzer_sigrok/LICENSE | 22 ------------------- src/use_examples_for_logic_analyzer.h | 2 ++ 19 files changed, 33 insertions(+), 77 deletions(-) rename {logic_analyzer => examples/logic_analyzer}/logic_analyzer.ino (99%) rename {logic_analyzer_leonardo => examples/logic_analyzer}/logic_analyzer_inline_2mhz.ino (99%) rename {logic_analyzer => examples/logic_analyzer}/logic_analyzer_inline_4mhz.ino (99%) rename {logic_analyzer_leonardo => examples/logic_analyzer_leonardo}/Makefile (100%) rename {logic_analyzer => examples/logic_analyzer_leonardo}/logic_analyzer_inline_2mhz.ino (99%) rename {logic_analyzer_leonardo => examples/logic_analyzer_leonardo}/logic_analyzer_inline_4mhz.ino (99%) rename {logic_analyzer_leonardo => examples/logic_analyzer_leonardo}/logic_analyzer_leonardo.ino (99%) rename {logic_analyzer_sigrok => examples/logic_analyzer_sigrok}/logic_analyzer_inline_2mhz.ino (100%) rename {logic_analyzer_sigrok => examples/logic_analyzer_sigrok}/logic_analyzer_inline_4mhz.ino (100%) rename {logic_analyzer_sigrok => examples/logic_analyzer_sigrok}/logic_analyzer_sigrok.ino (99%) rename ols.profile-agla.cfg => extras/ols.profile-agla.cfg (100%) rename ols.profile-aglam.cfg => extras/ols.profile-aglam.cfg (100%) create mode 100644 library.properties delete mode 100644 logic_analyzer/LICENSE delete mode 100644 logic_analyzer_leonardo/LICENSE delete mode 100644 logic_analyzer_sigrok/LICENSE create mode 100644 src/use_examples_for_logic_analyzer.h diff --git a/LICENSE b/LICENSE index 6b9421f..34ce5b0 100644 --- a/LICENSE +++ b/LICENSE @@ -1,4 +1,4 @@ -Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham +Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021,2022,2023 Andrew Gillham All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/README.md b/README.md index 4b471dd..9ab7e36 100644 --- a/README.md +++ b/README.md @@ -14,6 +14,17 @@ LED pin for an input. On the Arduino Mega board 8 channels are supported and 7k of samples. Pins 22-29 (Port A) are used by default. +Installation +============ + +You can use the GitHub 'Download ZIP' feature to get an installable "library" +for use with the Arduino IDE. Select 'Sketch -> Include Library -> Add .ZIP Libary' +from the Arduino IDE 2.x and select the zip file you downloaded from GitHub, then select open. + +Once installed you can use the 'File -> Examples -> LogicAnalyzer' menu to find +different versions of the sketches. You might want to start with `logic_analyzer_sigrok` +and use PulseView. + Client Software =============== diff --git a/logic_analyzer/logic_analyzer.ino b/examples/logic_analyzer/logic_analyzer.ino similarity index 99% rename from logic_analyzer/logic_analyzer.ino rename to examples/logic_analyzer/logic_analyzer.ino index 9b9a6a2..da2c4ff 100644 --- a/logic_analyzer/logic_analyzer.ino +++ b/examples/logic_analyzer/logic_analyzer.ino @@ -62,7 +62,7 @@ * until after the trigger fires. * Please try it out and report back. * - * Release: v0.16 October 3, 2023. + * Release: v0.17 October 5, 2023. * */ @@ -949,7 +949,7 @@ void get_metadata() { Serial.write('0'); Serial.write('.'); Serial.write('1'); - Serial.write('6'); + Serial.write('7'); Serial.write((uint8_t)0x00); /* sample memory */ diff --git a/logic_analyzer_leonardo/logic_analyzer_inline_2mhz.ino b/examples/logic_analyzer/logic_analyzer_inline_2mhz.ino similarity index 99% rename from logic_analyzer_leonardo/logic_analyzer_inline_2mhz.ino rename to examples/logic_analyzer/logic_analyzer_inline_2mhz.ino index ee9a535..7138cc9 100644 --- a/logic_analyzer_leonardo/logic_analyzer_inline_2mhz.ino +++ b/examples/logic_analyzer/logic_analyzer_inline_2mhz.ino @@ -2,7 +2,7 @@ * * SUMP Protocol Implementation for Arduino boards. * - * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham + * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021,2022,2023 Andrew Gillham * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/logic_analyzer/logic_analyzer_inline_4mhz.ino b/examples/logic_analyzer/logic_analyzer_inline_4mhz.ino similarity index 99% rename from logic_analyzer/logic_analyzer_inline_4mhz.ino rename to examples/logic_analyzer/logic_analyzer_inline_4mhz.ino index 2702736..d9dc848 100644 --- a/logic_analyzer/logic_analyzer_inline_4mhz.ino +++ b/examples/logic_analyzer/logic_analyzer_inline_4mhz.ino @@ -2,7 +2,7 @@ * * SUMP Protocol Implementation for Arduino boards. * - * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham + * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021,2022,2023 Andrew Gillham * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/logic_analyzer_leonardo/Makefile b/examples/logic_analyzer_leonardo/Makefile similarity index 100% rename from logic_analyzer_leonardo/Makefile rename to examples/logic_analyzer_leonardo/Makefile diff --git a/logic_analyzer/logic_analyzer_inline_2mhz.ino b/examples/logic_analyzer_leonardo/logic_analyzer_inline_2mhz.ino similarity index 99% rename from logic_analyzer/logic_analyzer_inline_2mhz.ino rename to examples/logic_analyzer_leonardo/logic_analyzer_inline_2mhz.ino index ee9a535..7138cc9 100644 --- a/logic_analyzer/logic_analyzer_inline_2mhz.ino +++ b/examples/logic_analyzer_leonardo/logic_analyzer_inline_2mhz.ino @@ -2,7 +2,7 @@ * * SUMP Protocol Implementation for Arduino boards. * - * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham + * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021,2022,2023 Andrew Gillham * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/logic_analyzer_leonardo/logic_analyzer_inline_4mhz.ino b/examples/logic_analyzer_leonardo/logic_analyzer_inline_4mhz.ino similarity index 99% rename from logic_analyzer_leonardo/logic_analyzer_inline_4mhz.ino rename to examples/logic_analyzer_leonardo/logic_analyzer_inline_4mhz.ino index 2702736..d9dc848 100644 --- a/logic_analyzer_leonardo/logic_analyzer_inline_4mhz.ino +++ b/examples/logic_analyzer_leonardo/logic_analyzer_inline_4mhz.ino @@ -2,7 +2,7 @@ * * SUMP Protocol Implementation for Arduino boards. * - * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham + * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021,2022,2023 Andrew Gillham * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/logic_analyzer_leonardo/logic_analyzer_leonardo.ino b/examples/logic_analyzer_leonardo/logic_analyzer_leonardo.ino similarity index 99% rename from logic_analyzer_leonardo/logic_analyzer_leonardo.ino rename to examples/logic_analyzer_leonardo/logic_analyzer_leonardo.ino index 246c60f..182527a 100644 --- a/logic_analyzer_leonardo/logic_analyzer_leonardo.ino +++ b/examples/logic_analyzer_leonardo/logic_analyzer_leonardo.ino @@ -62,7 +62,7 @@ * until after the trigger fires. * Please try it out and report back. * - * Release: v0.16 October 3, 2023. + * Release: v0.17 October 5, 2023. * */ @@ -918,7 +918,7 @@ void get_metadata() { Serial.write('0'); Serial.write('.'); Serial.write('1'); - Serial.write('6'); + Serial.write('7'); Serial.write((uint8_t)0x00); /* sample memory */ diff --git a/logic_analyzer_sigrok/logic_analyzer_inline_2mhz.ino b/examples/logic_analyzer_sigrok/logic_analyzer_inline_2mhz.ino similarity index 100% rename from logic_analyzer_sigrok/logic_analyzer_inline_2mhz.ino rename to examples/logic_analyzer_sigrok/logic_analyzer_inline_2mhz.ino diff --git a/logic_analyzer_sigrok/logic_analyzer_inline_4mhz.ino b/examples/logic_analyzer_sigrok/logic_analyzer_inline_4mhz.ino similarity index 100% rename from logic_analyzer_sigrok/logic_analyzer_inline_4mhz.ino rename to examples/logic_analyzer_sigrok/logic_analyzer_inline_4mhz.ino diff --git a/logic_analyzer_sigrok/logic_analyzer_sigrok.ino b/examples/logic_analyzer_sigrok/logic_analyzer_sigrok.ino similarity index 99% rename from logic_analyzer_sigrok/logic_analyzer_sigrok.ino rename to examples/logic_analyzer_sigrok/logic_analyzer_sigrok.ino index 7feecc0..e7dc087 100644 --- a/logic_analyzer_sigrok/logic_analyzer_sigrok.ino +++ b/examples/logic_analyzer_sigrok/logic_analyzer_sigrok.ino @@ -62,7 +62,7 @@ * until after the trigger fires. * Please try it out and report back. * - * Release: v0.16 October 3, 2023. + * Release: v0.17 October 5, 2023. * */ @@ -949,7 +949,7 @@ void get_metadata() { Serial.write('0'); Serial.write('.'); Serial.write('1'); - Serial.write('6'); + Serial.write('7'); Serial.write((uint8_t)0x00); /* sample memory */ diff --git a/ols.profile-agla.cfg b/extras/ols.profile-agla.cfg similarity index 100% rename from ols.profile-agla.cfg rename to extras/ols.profile-agla.cfg diff --git a/ols.profile-aglam.cfg b/extras/ols.profile-aglam.cfg similarity index 100% rename from ols.profile-aglam.cfg rename to extras/ols.profile-aglam.cfg diff --git a/library.properties b/library.properties new file mode 100644 index 0000000..4a664e3 --- /dev/null +++ b/library.properties @@ -0,0 +1,9 @@ +name=LogicAnalyzer +version=0.17.0 +author=Andrew Gillham +maintainer=Andrew Gillham +sentence=A SUMP protocol compatible logic analyzer firmware +paragraph=These firmware sketches provide a 6 channel logic analyzer for use with the SUMP protocol based OLS clients. There is also a Sigrok compatible firmware using the OpenBench Logic Sniffer (ols) driver . +category=Signal Input/Output +url=https://github.com/gillham/logic_analyzer +architectures=avr diff --git a/logic_analyzer/LICENSE b/logic_analyzer/LICENSE deleted file mode 100644 index 6b9421f..0000000 --- a/logic_analyzer/LICENSE +++ /dev/null @@ -1,22 +0,0 @@ -Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions -are met: -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY ANDREW GILLHAM ``AS IS'' AND ANY EXPRESS OR -IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL ANDREW GILLHAM BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/logic_analyzer_leonardo/LICENSE b/logic_analyzer_leonardo/LICENSE deleted file mode 100644 index 6b9421f..0000000 --- a/logic_analyzer_leonardo/LICENSE +++ /dev/null @@ -1,22 +0,0 @@ -Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions -are met: -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY ANDREW GILLHAM ``AS IS'' AND ANY EXPRESS OR -IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL ANDREW GILLHAM BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/logic_analyzer_sigrok/LICENSE b/logic_analyzer_sigrok/LICENSE deleted file mode 100644 index 6b9421f..0000000 --- a/logic_analyzer_sigrok/LICENSE +++ /dev/null @@ -1,22 +0,0 @@ -Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions -are met: -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY ANDREW GILLHAM ``AS IS'' AND ANY EXPRESS OR -IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL ANDREW GILLHAM BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/src/use_examples_for_logic_analyzer.h b/src/use_examples_for_logic_analyzer.h new file mode 100644 index 0000000..93f93d6 --- /dev/null +++ b/src/use_examples_for_logic_analyzer.h @@ -0,0 +1,2 @@ +// This is a placeholder. Use File->Examples->LogicAnalyzer menu +// for the logic analyzer sketches.