pylint: transport/serial.py

pySim/transport/serial.py:54:0: C0325: Unnecessary parens after 'if' keyword (superfluous-parens)
pySim/transport/serial.py:89:0: C0325: Unnecessary parens after 'if' keyword (superfluous-parens)
pySim/transport/serial.py:225:0: C0325: Unnecessary parens after 'while' keyword (superfluous-parens)
pySim/transport/serial.py:63:12: R1705: Unnecessary "else" after "return", remove the "else" and de-indent the code inside it (no-else-return)
pySim/transport/serial.py:106:8: R1720: Unnecessary "elif" after "raise", remove the leading "el" from "elif" (no-else-raise)
pySim/transport/serial.py:124:12: W0707: Consider explicitly re-raising using 'except Exception as exc' and 'raise ValueError('Invalid reset pin %s' % self._rst_pin) from exc' (raise-missing-from)
pySim/transport/serial.py:204:12: R1723: Unnecessary "elif" after "break", remove the leading "el" from "elif" (no-else-break)
pySim/transport/serial.py:20:0: C0411: standard import "import time" should be placed before "import serial" (wrong-import-order)
pySim/transport/serial.py:21:0: C0411: standard import "import os" should be placed before "import serial" (wrong-import-order)
pySim/transport/serial.py:22:0: C0411: standard import "import argparse" should be placed before "import serial" (wrong-import-order)
pySim/transport/serial.py:23:0: C0411: standard import "from typing import Optional" should be placed before "import serial" (wrong-import-order)

Change-Id: I82ef12492615a18a13cbdecf0371b3a5d02bbd5c
This commit is contained in:
Harald Welte
2024-02-04 22:41:12 +01:00
parent 7781c70c09
commit fdaefd9a8a

View File

@@ -16,11 +16,11 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>. # along with this program. If not, see <http://www.gnu.org/licenses/>.
# #
import serial
import time import time
import os import os
import argparse import argparse
from typing import Optional from typing import Optional
import serial
from pySim.exceptions import NoCardError, ProtocolError from pySim.exceptions import NoCardError, ProtocolError
from pySim.transport import LinkBase from pySim.transport import LinkBase
@@ -51,7 +51,7 @@ class SerialSimLink(LinkBase):
self._atr = None self._atr = None
def __del__(self): def __del__(self):
if (hasattr(self, "_sl")): if hasattr(self, "_sl"):
self._sl.close() self._sl.close()
def wait_for_card(self, timeout: Optional[int] = None, newcardonly: bool = False): def wait_for_card(self, timeout: Optional[int] = None, newcardonly: bool = False):
@@ -62,8 +62,7 @@ class SerialSimLink(LinkBase):
self.reset_card() self.reset_card()
if not newcardonly: if not newcardonly:
return return
else: existing = True
existing = True
except NoCardError: except NoCardError:
pass pass
@@ -86,7 +85,7 @@ class SerialSimLink(LinkBase):
# Tolerate a couple of protocol error ... can happen if # Tolerate a couple of protocol error ... can happen if
# we try when the card is 'half' inserted # we try when the card is 'half' inserted
pe += 1 pe += 1
if (pe > 2): if pe > 2:
raise raise
# Timed out ... # Timed out ...
@@ -105,7 +104,7 @@ class SerialSimLink(LinkBase):
rv = self._reset_card() rv = self._reset_card()
if rv == 0: if rv == 0:
raise NoCardError() raise NoCardError()
elif rv < 0: if rv < 0:
raise ProtocolError() raise ProtocolError()
return rv return rv
@@ -120,8 +119,8 @@ class SerialSimLink(LinkBase):
try: try:
rst_meth = rst_meth_map[self._rst_pin[1:]] rst_meth = rst_meth_map[self._rst_pin[1:]]
rst_val = rst_val_map[self._rst_pin[0]] rst_val = rst_val_map[self._rst_pin[0]]
except: except Exception as exc:
raise ValueError('Invalid reset pin %s' % self._rst_pin) raise ValueError('Invalid reset pin %s' % self._rst_pin) from exc
rst_meth(rst_val) rst_meth(rst_val)
time.sleep(0.1) # 100 ms time.sleep(0.1) # 100 ms
@@ -203,7 +202,7 @@ class SerialSimLink(LinkBase):
b = self._rx_byte() b = self._rx_byte()
if ord(b) == pdu[1]: if ord(b) == pdu[1]:
break break
elif b != '\x60': if b != '\x60':
# Ok, it 'could' be SW1 # Ok, it 'could' be SW1
sw1 = b sw1 = b
sw2 = self._rx_byte() sw2 = self._rx_byte()
@@ -222,7 +221,7 @@ class SerialSimLink(LinkBase):
to_recv = data_len - len(pdu) + 5 + 2 to_recv = data_len - len(pdu) + 5 + 2
data = bytes(0) data = bytes(0)
while (len(data) < to_recv): while len(data) < to_recv:
b = self._rx_byte() b = self._rx_byte()
if (to_recv == 2) and (b == '\x60'): # Ignore NIL if we have no RX data (hack ?) if (to_recv == 2) and (b == '\x60'): # Ignore NIL if we have no RX data (hack ?)
continue continue