pylint: transport/serial.py
pySim/transport/serial.py:54:0: C0325: Unnecessary parens after 'if' keyword (superfluous-parens)
pySim/transport/serial.py:89:0: C0325: Unnecessary parens after 'if' keyword (superfluous-parens)
pySim/transport/serial.py:225:0: C0325: Unnecessary parens after 'while' keyword (superfluous-parens)
pySim/transport/serial.py:63:12: R1705: Unnecessary "else" after "return", remove the "else" and de-indent the code inside it (no-else-return)
pySim/transport/serial.py:106:8: R1720: Unnecessary "elif" after "raise", remove the leading "el" from "elif" (no-else-raise)
pySim/transport/serial.py:124:12: W0707: Consider explicitly re-raising using 'except Exception as exc' and 'raise ValueError('Invalid reset pin %s' % self._rst_pin) from exc' (raise-missing-from)
pySim/transport/serial.py:204:12: R1723: Unnecessary "elif" after "break", remove the leading "el" from "elif" (no-else-break)
pySim/transport/serial.py:20:0: C0411: standard import "import time" should be placed before "import serial" (wrong-import-order)
pySim/transport/serial.py:21:0: C0411: standard import "import os" should be placed before "import serial" (wrong-import-order)
pySim/transport/serial.py:22:0: C0411: standard import "import argparse" should be placed before "import serial" (wrong-import-order)
pySim/transport/serial.py:23:0: C0411: standard import "from typing import Optional" should be placed before "import serial" (wrong-import-order)
Change-Id: I82ef12492615a18a13cbdecf0371b3a5d02bbd5c
This commit is contained in:
@@ -16,11 +16,11 @@
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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import serial
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import time
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import os
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import argparse
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from typing import Optional
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import serial
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from pySim.exceptions import NoCardError, ProtocolError
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from pySim.transport import LinkBase
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@@ -51,7 +51,7 @@ class SerialSimLink(LinkBase):
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self._atr = None
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def __del__(self):
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if (hasattr(self, "_sl")):
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if hasattr(self, "_sl"):
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self._sl.close()
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def wait_for_card(self, timeout: Optional[int] = None, newcardonly: bool = False):
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@@ -62,8 +62,7 @@ class SerialSimLink(LinkBase):
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self.reset_card()
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if not newcardonly:
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return
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else:
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existing = True
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existing = True
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except NoCardError:
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pass
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@@ -86,7 +85,7 @@ class SerialSimLink(LinkBase):
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# Tolerate a couple of protocol error ... can happen if
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# we try when the card is 'half' inserted
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pe += 1
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if (pe > 2):
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if pe > 2:
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raise
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# Timed out ...
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@@ -105,7 +104,7 @@ class SerialSimLink(LinkBase):
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rv = self._reset_card()
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if rv == 0:
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raise NoCardError()
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elif rv < 0:
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if rv < 0:
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raise ProtocolError()
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return rv
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@@ -120,8 +119,8 @@ class SerialSimLink(LinkBase):
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try:
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rst_meth = rst_meth_map[self._rst_pin[1:]]
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rst_val = rst_val_map[self._rst_pin[0]]
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except:
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raise ValueError('Invalid reset pin %s' % self._rst_pin)
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except Exception as exc:
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raise ValueError('Invalid reset pin %s' % self._rst_pin) from exc
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rst_meth(rst_val)
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time.sleep(0.1) # 100 ms
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@@ -203,7 +202,7 @@ class SerialSimLink(LinkBase):
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b = self._rx_byte()
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if ord(b) == pdu[1]:
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break
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elif b != '\x60':
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if b != '\x60':
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# Ok, it 'could' be SW1
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sw1 = b
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sw2 = self._rx_byte()
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@@ -222,7 +221,7 @@ class SerialSimLink(LinkBase):
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to_recv = data_len - len(pdu) + 5 + 2
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data = bytes(0)
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while (len(data) < to_recv):
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while len(data) < to_recv:
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b = self._rx_byte()
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if (to_recv == 2) and (b == '\x60'): # Ignore NIL if we have no RX data (hack ?)
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continue
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