Change directory structure to align with Atmel softpack

This way we can easily check with 'diff' for differences in our code and
Atmel softpack.  Also, this layout is more suitable for building various
different firmware images (e.g. factory-test, dfu-loader, main
application) for a variety of different boards (simtrace, owhw, qmod).

firmware/atmel_softpack_libraries/libchip_sam3s/chip.h

@@ -0,0 +1,59 @@
+#ifndef _LIB_SAM3S_
+#define _LIB_SAM3S_
+
+/*
+ * Peripherals registers definitions
+ */
+#if defined sam3s4
+#elif defined sam3s2
+#elif defined sam3s1
+#else
+    #warning Library does not support the specified chip, specifying sam3s4.
+    #define sam3s4
+#endif
+#include "SAM3S.h"
+
+
+/* Define attribute */
+#if defined   ( __CC_ARM   ) /* Keil µVision 4 */
+    #define WEAK __attribute__ ((weak))
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+    #define WEAK __weak
+#elif defined (  __GNUC__  ) /* GCC CS3 2009q3-68 */
+    #define WEAK __attribute__ ((weak))
+#endif
+
+/* Define NO_INIT attribute */
+#if defined   ( __CC_ARM   )
+    #define NO_INIT
+#elif defined ( __ICCARM__ )
+    #define NO_INIT __no_init
+#elif defined (  __GNUC__  )
+    #define NO_INIT
+#endif
+
+
+/*
+ * Core
+ */
+
+#include "exceptions.h"
+
+/*
+ * Peripherals
+ */
+#include "pio.h"
+#include "pio_it.h"
+#include "pio_capture.h"
+#include "pmc.h"
+#include "tc.h"
+#include "usart.h"
+//#include "USBD_Config.h"
+
+#include "trace.h"
+#include "wdt.h"
+#include "unique_id.h"
+#include "efc.h"
+#include "flashd.h"
+
+#endif /* _LIB_SAM3S_ */

firmware/atmel_softpack_libraries/libchip_sam3s/cmsis/core_cm3.c

@@ -0,0 +1,807 @@
+/**************************************************************************//**
+ * @file     core_cm3.c
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version  V1.30
+ * @date     30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+uint32_t __get_PSP(void) ;
+void __set_PSP(uint32_t topOfProcStack) ;
+uint32_t __get_MSP(void) ;
+void __set_MSP(uint32_t mainStackPointer) ;
+uint32_t __REV16(uint16_t value) ;
+int32_t __REVSH(int16_t value) ;
+uint32_t __RBIT(uint32_t value) ;
+uint8_t __LDREXB(uint8_t *addr) ;
+uint16_t __LDREXH(uint16_t *addr) ;
+uint32_t __LDREXW(uint32_t *addr) ;
+uint32_t __STREXB(uint8_t value, uint8_t *addr) ;
+uint32_t __STREXH(uint16_t value, uint16_t *addr) ;
+uint32_t __STREXW(uint32_t value, uint32_t *addr) ;
+
+uint32_t  __get_BASEPRI(void) ;
+void __set_BASEPRI(uint32_t basePri) ;
+uint32_t __get_PRIMASK(void) ;
+void __set_PRIMASK(uint32_t priMask) ;
+uint32_t  __get_FAULTMASK(void) ;
+void __set_FAULTMASK(uint32_t faultMask) ;
+uint32_t __get_CONTROL(void) ;
+void __set_CONTROL(uint32_t control) ;
+uint32_t __REV(uint32_t value) ;
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+  mrs r0, psp
+  bx lr
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+  msr psp, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+  mrs r0, msp
+  bx lr
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+  msr msp, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief  Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+  clrex
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t  __get_BASEPRI(void)
+{
+  mrs r0, basepri
+  bx lr
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+  msr basepri, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+  mrs r0, primask
+  bx lr
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+  msr primask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t  __get_FAULTMASK(void)
+{
+  mrs r0, faultmask
+  bx lr
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+  msr faultmask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+  mrs r0, control
+  bx lr
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+  msr control, r0
+  bx lr
+}
+
+#endif /* __ARMCC_VERSION  */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+  __ASM("mrs r0, psp");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM("msr psp, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+  __ASM("mrs r0, msp");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM("msr msp, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  __ASM("rev16 r0, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+  __ASM("rbit r0, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+  __ASM("ldrexb r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+  __ASM("ldrexh r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+  __ASM("ldrex r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+  __ASM("strexb r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+  __ASM("strexh r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+  __ASM("strex r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+/*extern uint32_t __get_PSP(void) __attribute__( ( naked ) ); */
+uint32_t __get_PSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, psp\n\t"
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+/*void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); */
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+/*uint32_t __get_MSP(void) __attribute__( ( naked ) ); */
+uint32_t __get_MSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, msp\n\t"
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+/*void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); */
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfMainStack) );
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+uint32_t __get_PRIMASK(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+/**
+ * @brief  Return the Control Register value
+*
+*  @return Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/**
+ * @brief  Reverse byte order in integer value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result=0;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+    uint8_t result=0;
+
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+    uint16_t result=0;
+
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+    uint32_t result=0;
+
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+   uint32_t result=0;
+
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+   uint32_t result=0;
+
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+   uint32_t result=0;
+
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif

firmware/atmel_softpack_libraries/libchip_sam3s/include/USBD_Config.h

@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * USB Device Framework configurations.
+ *
+ */
+
+#ifndef USBD_CONFIG_H
+#define USBD_CONFIG_H
+
+/*----------------------------------------------------------------------------
+ *      Headers
+ *----------------------------------------------------------------------------*/
+
+/** \addtogroup usbd_config
+ *@{
+ */
+/*----------------------------------------------------------------------------
+ *      Constants
+ *----------------------------------------------------------------------------*/
+
+/** \addtogroup usbd_ids USBD Device IDs
+ *      @{
+ */
+#define USBD_VID_ATMEL              0x03EB  /**< Vendor ID: Atmel */
+
+#define USBD_PID_ENUM               0x0001  /**< Product ID: Enum (Core) */
+#define USBD_PID_CDCDSERIAL         0x6119  /**< Product ID: CDC Serial */
+#define USBD_PID_HIDKEYBOARD        0x6127  /**< Product ID: HID Keyboard */
+#define USBD_PID_AUDIO              0x6128  /**< Product ID: Audio devices */
+#define USBD_PID_MSD                0x6129  /**< Product ID: Massstorage */
+#define USBD_PID_CDCHID             0x6130  /**< Product ID: composite */
+#define USBD_PID_CDCAUDIO           0x6131  /**< Product ID: composite */
+#define USBD_PID_CDCMSD             0x6132  /**< Product ID: composite */
+#define USBD_PID_CDCCDC             0x6133  /**< Product ID: composite */
+#define USBD_PID_HIDAUDIO           0x6134  /**< Product ID: composite */
+#define USBD_PID_HIDMSD             0x6135  /**< Product ID: composite */
+#define USBD_PID_HIDMOUSE           0x6200  /**< Product ID: HID Mouse */
+#define USBD_PID_HIDTRANSFER        0x6201  /**< Product ID: HID Transfer */
+#define USBD_PID_CCID               0x6203  /**< Product ID: CCID */
+
+#define USBD_RELEASE_1_00           0x0100  /**< Release: 1.00 */
+/**     @}*/
+
+/** \addtogroup usbd_general_config USBD General Configure
+ *      @{
+ * This page lists general configurations for all USB device drivers.
+ * - \ref USBD_BMATTRIBUTES
+ */
+/** default USB Device attributes configuration descriptor
+ *  (bus or self powered, remote wakeup) */
+#define USBD_BMATTRIBUTES           BOARD_USB_BMATTRIBUTES
+/**     @}*/
+
+/*----------------------------------------------------------------------------
+ *      USB Device - Mass storage
+ *----------------------------------------------------------------------------*/
+
+/** \addtogroup usbd_msdd_config USB MassStorage Configure
+ *      @{
+ * This page lists the defines used by the Mass Storage driver.
+ *
+ * \section msd_ep_addr Endpoint Addresses
+ * - \ref MSDDriverDescriptors_BULKOUT
+ * - \ref MSDDriverDescriptors_BULKIN
+ */
+/** Address of the Mass Storage bulk-out endpoint.*/
+#define MSDDriverDescriptors_BULKOUT                1
+/** Address of the Mass Storage bulk-in endpoint.*/
+#define MSDDriverDescriptors_BULKIN                 2
+/**      @}*/
+
+/*----------------------------------------------------------------------------
+ *      USB Device - CDC Serial
+ *----------------------------------------------------------------------------*/
+
+/** \addtogroup usbd_cdc_serial_config USB CDC Serial Configure
+ *      @{
+ * This page lists the defines used by the CDC Serial Device Driver.
+ *
+ * \section cdcd_ep_addr Endpoint Addresses
+ * - \ref CDCDSerialDriverDescriptors_DATAOUT
+ * - \ref CDCDSerialDriverDescriptors_DATAIN
+ * - \ref CDCDSerialDriverDescriptors_NOTIFICATION
+ */
+/** Data OUT endpoint number */
+#define CDCDSerialDriverDescriptors_DATAOUT             1
+/** Data IN endpoint number */
+#define CDCDSerialDriverDescriptors_DATAIN              2
+/** Notification endpoint number */
+#define CDCDSerialDriverDescriptors_NOTIFICATION        3
+/**      @}*/
+
+/*----------------------------------------------------------------------------
+ *      USB Device - Audio
+ *----------------------------------------------------------------------------*/
+
+/** \addtogroup usbd_audio_config USB Audio General Configure
+ *      @{
+ * This page lists definitions for USB Audio Devices Drivers.
+ * - \ref
+ */
+#if defined(at91sam7s) || defined(at91sam9xe)
+ /** Sample rate in Hz. */
+ #define AUDDevice_SAMPLERATE        32000UL
+ /** Number of channels in audio stream. */
+ #define AUDDevice_NUMCHANNELS       1
+ /** Number of bytes in one sample. */
+ #define AUDDevice_BYTESPERSAMPLE    2
+#else
+ /** Sample rate in Hz. */
+ #define AUDDevice_SAMPLERATE        48000UL
+ /** Number of channels in audio stream. */
+ #define AUDDevice_NUMCHANNELS       2
+ /** Number of bytes in one sample. */
+ #define AUDDevice_BYTESPERSAMPLE    2
+#endif
+/** Number of bits in one sample. */
+#define AUDDevice_BITSPERSAMPLE     (AUDDevice_BYTESPERSAMPLE * 8)
+/** Number of bytes in one USB subframe. */
+#define AUDDevice_BYTESPERSUBFRAME  (AUDDevice_NUMCHANNELS * \
+                                     AUDDevice_BYTESPERSAMPLE)
+/** Number of samples in one USB frame. */
+#define AUDDevice_SAMPLESPERFRAME   (AUDDevice_SAMPLERATE / 1000 \
+                                     * AUDDevice_NUMCHANNELS)
+/** Number of bytes in one USB frame. */
+#define AUDDevice_BYTESPERFRAME     (AUDDevice_SAMPLESPERFRAME * \
+                                     AUDDevice_BYTESPERSAMPLE)
+/**     @}*/
+
+/*----------------------------------------------------------------------------
+ *      USB Device - Audio - Desktop Speaker
+ *----------------------------------------------------------------------------*/
+
+/** \addtogroup usbd_audio_speaker_config USB Speaker Configure
+ *      @{
+ * This page lists the definitions for USB Audio Speaker Device Driver.
+ * - \ref AUDDSpeakerDriverDescriptors_DATAOUT
+ * - \ref AUDDSpeakerDriverDescriptors_FS_INTERVAL
+ * - \ref AUDDSpeakerDriverDescriptors_HS_INTERVAL
+ *
+ * \note for UDP, uses IN EPs that support double buffer; for UDPHS, uses
+ *       IN EPs that support DMA and High bandwidth.
+ */
+/** Data out endpoint number. */
+#define AUDDSpeakerDriverDescriptors_DATAOUT            0x04
+/** Endpoint polling interval 2^(x-1) * 125us */
+#define AUDDSpeakerDriverDescriptors_HS_INTERVAL        0x04
+/** Endpoint polling interval 2^(x-1) * ms */
+#define AUDDSpeakerDriverDescriptors_FS_INTERVAL        0x01
+/**     @}*/
+
+/*----------------------------------------------------------------------------
+ *      USB Device - Audio - Speaker Phone
+ *----------------------------------------------------------------------------*/
+
+/** \addtogroup usbd_audio_speakerphone_config USB Speaker Phone Configure
+ *      @{
+ * This page lists the definitions for USB Audio Speaker Phone Device Driver.
+ * - \ref AUDDSpeakerPhoneDriverDescriptors_DATAOUT
+ * - \ref AUDDSpeakerPhoneDriverDescriptors_DATAIN
+ * - \ref AUDDSpeakerPhoneDriverDescriptors_HS_INTERVAL
+ * - \ref AUDDSpeakerPhoneDriverDescriptors_FS_INTERVAL
+ */
+
+#if defined(at91sam7s) || defined(at91sam9xe)
+    /** Data out endpoint number, size 64B */
+    #define AUDDSpeakerPhoneDriverDescriptors_DATAOUT        0x01
+    /** Data in endpoint number, size 64B */
+    #define AUDDSpeakerPhoneDriverDescriptors_DATAIN         0x02
+#elif defined(CHIP_USB_UDP)
+    /** Data out endpoint number, size 192B */
+    #define AUDDSpeakerPhoneDriverDescriptors_DATAOUT        0x04
+    /** Data in endpoint number, size 192B */
+    #define AUDDSpeakerPhoneDriverDescriptors_DATAIN         0x05
+#elif defined(at91sam9m10ek)
+    /** Data out endpoint number, size 192B */
+    #define AUDDSpeakerPhoneDriverDescriptors_DATAOUT        0x01
+    /** Data in endpoint number, size 192B */
+    #define AUDDSpeakerPhoneDriverDescriptors_DATAIN         0x06
+#else
+    /** Data out endpoint number, size 192B */
+    #define AUDDSpeakerPhoneDriverDescriptors_DATAOUT        0x05
+    /** Data in endpoint number, size 192B */
+    #define AUDDSpeakerPhoneDriverDescriptors_DATAIN         0x06
+#endif
+/** Endpoint polling interval 2^(x-1) * 125us */
+#define AUDDSpeakerPhoneDriverDescriptors_HS_INTERVAL        0x04
+/** Endpoint polling interval 2^(x-1) * ms */
+#define AUDDSpeakerPhoneDriverDescriptors_FS_INTERVAL        0x01
+/**      @}*/
+
+/*----------------------------------------------------------------------------
+ *      USB Device - HID - Keyboard
+ *----------------------------------------------------------------------------*/
+
+/** \addtogroup usbd_hid_keyboard_config USB HID Keyboard Device Configure
+ *      @{
+ * This page lists the defines used by the HID Keyboard Device Driver.
+ *
+ * \section hidd_k_ep_addr Endpoint Addresses
+ * - \ref HIDDKeyboardDriverDescriptors_INTERRUPTIN
+ * - \ref HIDDKeyboardDriverDescriptors_INTERRUPTOUT
+ * \section hidd_k_ep_polling Endpoint Polling Rate
+ * - \ref HIDDKeyboardDriverDescriptors_INTERRUPTIN_POLLING
+ * - \ref HIDDKeyboardDriverDescriptors_INTERRUPTOUT_POLLING
+ */
+/** Interrupt IN endpoint number */
+#define HIDDKeyboardDriverDescriptors_INTERRUPTIN           1
+/** Interrupt IN endpoint polling rate (in milliseconds) */
+#define HIDDKeyboardDriverDescriptors_INTERRUPTIN_POLLING   10
+/** Interrupt OUT endpoint number */
+#define HIDDKeyboardDriverDescriptors_INTERRUPTOUT          2
+/** Interrupt OUT endpoint polling rate (in milliseconds) */
+#define HIDDKeyboardDriverDescriptors_INTERRUPTOUT_POLLING  10
+/**     @}*/
+
+/*----------------------------------------------------------------------------
+ *      USB Device - HID  - Mouse
+ *----------------------------------------------------------------------------*/
+
+/** \addtogroup usbd_hid_mouse_config USB HID Mouse Device Configure
+ *      @{
+ * This page lists the defines used by the HID Mouse Device Driver.
+ *
+ * \section hidd_m_ep_addr Endpoint Addresses
+ * - \ref HIDDMouseDriverDescriptors_INTERRUPTIN
+ * \section hidd_m_ep_polling Endpoint Polling Rate
+ * - \ref HIDDMouseDriverDescriptors_INTERRUPTIN_POLLING
+ */
+/** Interrupt IN endpoint number */
+#define HIDDMouseDriverDescriptors_INTERRUPTIN           1
+/** Interrupt IN endpoint polling rate (in milliseconds) */
+#define HIDDMouseDriverDescriptors_INTERRUPTIN_POLLING   10
+/**     @}*/
+
+/*----------------------------------------------------------------------------
+ *      USB Device - HID  - Transfer (Customize device)
+ *----------------------------------------------------------------------------*/
+
+/** \addtogroup usbd_hid_xfr_config USB HID Transfer Device Configure
+ *      @{
+ * This page lists the defines used by the HID Transfer Device Driver.
+ *
+ * \section hidd_t_ep_addr Endpoint Addresses
+ * - \ref HIDDTransferDriverDescriptors_INTERRUPTIN
+ * - \ref HIDDTransferDriverDescriptors_INTERRUPTOUT
+ * \section hidd_t_ep_polling Endpoint Polling Rate
+ * - \ref HIDDTransferDriverDescriptors_INTERRUPTIN_POLLING
+ * - \ref HIDDTransferDriverDescriptors_INTERRUPTOUT_POLLING
+ */
+/** Interrupt IN endpoint number. */
+#define HIDDTransferDriverDescriptors_INTERRUPTIN           1
+/** Polling rate in ms */
+#define HIDDTransferDriverDescriptors_INTERRUPTIN_POLLING   50
+/** Interrupt IN endpoint polling rate (in milliseconds). */
+#define HIDDTransferDriverDescriptors_INTERRUPTOUT          2
+/** Polling rate in ms */
+#define HIDDTransferDriverDescriptors_INTERRUPTOUT_POLLING  50
+/**     @}*/
+
+/*----------------------------------------------------------------------------
+ *      USB Device - Composite
+ *----------------------------------------------------------------------------*/
+
+/** \addtogroup usbd_composite_config USB Composite Device Configure
+ *  @{
+ */
+/** @}*/
+
+/**@}*/
+#endif //#ifndef USBD_CONFIG_H
+
+

firmware/atmel_softpack_libraries/libchip_sam3s/include/efc.h

@@ -0,0 +1,113 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \section Purpose
+ *
+ * Interface for configuration the Enhanced Embedded Flash Controller (EEFC) peripheral.
+ *
+ * \section Usage
+ *
+ * -# Enable/disable %flash ready interrupt sources using EFC_EnableFrdyIt()
+ *    and EFC_DisableFrdyIt().
+ * -# Translates the given address into which EEFC, page and offset values
+ *    for difference density %flash memory using EFC_TranslateAddress().
+ * -# Computes the address of a %flash access given the EFC, page and offset
+ *    for difference density %flash memory using EFC_ComputeAddress().
+ * -# Start the executing command with EFC_StartCommand()
+ * -# Retrieve the current status of the EFC using EFC_GetStatus().
+ * -# Retrieve the result of the last executed command with EFC_GetResult().
+ */
+
+#ifndef _EEFC_
+#define _EEFC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ *        Definitions
+ *----------------------------------------------------------------------------*/
+/* EFC command */
+#define EFC_FCMD_GETD    0x00
+#define EFC_FCMD_WP      0x01
+#define EFC_FCMD_WPL     0x02
+#define EFC_FCMD_EWP     0x03
+#define EFC_FCMD_EWPL    0x04
+#define EFC_FCMD_EA      0x05
+#define EFC_FCMD_SLB     0x08
+#define EFC_FCMD_CLB     0x09
+#define EFC_FCMD_GLB     0x0A
+#define EFC_FCMD_SFB     0x0B
+#define EFC_FCMD_CFB     0x0C
+#define EFC_FCMD_GFB     0x0D
+#define EFC_FCMD_STUI    0x0E /* Start unique ID */
+#define EFC_FCMD_SPUI    0x0F /* Stop unique ID */
+
+/* The IAP function entry addreass */
+#define CHIP_FLASH_IAP_ADDRESS  (0x00800008)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void EFC_EnableFrdyIt( Efc* efc ) ;
+
+extern void EFC_DisableFrdyIt( Efc* efc ) ;
+
+extern void EFC_SetWaitState( Efc* efc, uint8_t cycles ) ;
+
+extern void EFC_TranslateAddress( Efc** pEfc, uint32_t dwAddress, uint16_t *pwPage, uint16_t *pwOffset ) ;
+
+extern void EFC_ComputeAddress( Efc* efc, uint16_t wPage, uint16_t wOffset, uint32_t *pdwAddress ) ;
+
+extern void EFC_StartCommand( Efc* efc, uint32_t dwCommand, uint32_t dwArgument ) ;
+
+extern uint32_t EFC_PerformCommand( Efc* efc, uint32_t dwCommand, uint32_t dwArgument, uint32_t dwUseIAP ) ;
+
+extern uint32_t EFC_GetStatus( Efc* efc ) ;
+
+extern uint32_t EFC_GetResult( Efc* efc ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _EEFC_ */
+

firmware/atmel_softpack_libraries/libchip_sam3s/include/exceptions.h

@@ -0,0 +1,97 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ * Interface for default exception handlers.
+ */
+
+#ifndef _EXCEPTIONS_
+#define _EXCEPTIONS_
+
+/*----------------------------------------------------------------------------
+ *        Types
+ *----------------------------------------------------------------------------*/
+
+/* Function prototype for exception table items (interrupt handler). */
+typedef void( *IntFunc )( void ) ;
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/* Default empty handler */
+extern void IrqHandlerNotUsed( void ) ;
+
+/* Cortex-M3 core handlers */
+extern void NMI_Handler( void );
+extern void HardFault_Handler( void );
+extern void MemManage_Handler( void );
+extern void BusFault_Handler( void );
+extern void UsageFault_Handler( void );
+extern void SVC_Handler( void );
+extern void DebugMon_Handler( void );
+extern void PendSV_Handler( void );
+extern void SysTick_Handler( void );
+
+/* Peripherals handlers */
+extern void ACC_IrqHandler( void ) ;
+extern void ADC_IrqHandler( void ) ;
+extern void CRCCU_IrqHandler( void ) ;
+extern void DAC_IrqHandler( void ) ;
+extern void EEFC_IrqHandler( void ) ;
+extern void MCI_IrqHandler( void ) ;
+extern void PIOA_IrqHandler( void ) ;
+extern void PIOB_IrqHandler( void ) ;
+extern void PIOC_IrqHandler( void ) ;
+extern void PMC_IrqHandler( void ) ;
+extern void PWM_IrqHandler( void ) ;
+extern void RSTC_IrqHandler( void ) ;
+extern void RTC_IrqHandler( void ) ;
+extern void RTT_IrqHandler( void ) ;
+extern void SMC_IrqHandler( void ) ;
+extern void SPI_IrqHandler( void ) ;
+extern void SSC_IrqHandler( void ) ;
+extern void SUPC_IrqHandler( void ) ;
+extern void TC0_IrqHandler( void ) ;
+extern void TC1_IrqHandler( void ) ;
+extern void TC2_IrqHandler( void ) ;
+extern void TC3_IrqHandler( void ) ;
+extern void TC4_IrqHandler( void ) ;
+extern void TC5_IrqHandler( void ) ;
+extern void TWI0_IrqHandler( void ) ;
+extern void TWI1_IrqHandler( void ) ;
+extern void UART0_IrqHandler( void ) ;
+extern void UART1_IrqHandler( void ) ;
+extern void USART0_IrqHandler( void ) ;
+extern void USART1_IrqHandler( void ) ;
+extern void USBD_IrqHandler(void);
+extern void WDT_IrqHandler( void ) ;
+
+#endif /* _EXCEPTIONS_ */

firmware/atmel_softpack_libraries/libchip_sam3s/include/flashd.h

@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+*/
+
+/**
+ * \file
+ *
+ * The flash driver provides the unified interface for flash program operations.
+ *
+ */
+
+#ifndef _FLASHD_
+#define _FLASHD_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void FLASHD_Initialize( uint32_t dwMCk, uint32_t dwUseIAP ) ;
+
+extern uint32_t FLASHD_Erase( uint32_t dwAddress ) ;
+
+extern uint32_t FLASHD_Write( uint32_t dwAddress, const void *pvBuffer, uint32_t dwSize ) ;
+
+extern uint32_t FLASHD_Lock( uint32_t dwStart, uint32_t dwEnd, uint32_t *pdwActualStart, uint32_t *pdwActualEnd ) ;
+
+extern uint32_t FLASHD_Unlock( uint32_t dwStart, uint32_t dwEnd, uint32_t *pdwActualStart, uint32_t *pdwActualEnd ) ;
+
+extern uint32_t FLASHD_IsLocked( uint32_t dwStart, uint32_t dwEnd ) ;
+
+extern uint32_t FLASHD_SetGPNVM( uint8_t gpnvm ) ;
+
+extern uint32_t FLASHD_ClearGPNVM( uint8_t gpnvm ) ;
+
+extern uint32_t FLASHD_IsGPNVMSet( uint8_t gpnvm ) ;
+
+#define FLASHD_IsSecurityBitSet() FLASHD_IsGPNVMSet( 0 )
+
+#define FLASHD_SetSecurityBit()   FLASHD_SetGPNVM( 0 )
+
+extern uint32_t FLASHD_ReadUniqueID( uint32_t* pdwUniqueID ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _FLASHD_ */
+

firmware/atmel_softpack_libraries/libchip_sam3s/include/hsmci.h

@@ -0,0 +1,206 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup hsmci_module Working with HSMCI
+ * The HSMCI driver provides the interface to configure and use the HSMCI
+ * peripheral.
+ *
+ * The user needs to set the number of wait states depending on the frequency used.\n
+ * Configure number of cycles for flash read/write operations in the FWS field of HSMCI_FMR.
+ *
+ * It offers a function to send flash command to HSMCI and waits for the
+ * flash to be ready.
+ *
+ * To send flash command, the user could do in either of following way:
+ * <ul>
+ * <li>Write a correct key, command and argument in HSMCI_FCR. </li>
+ * <li>Or, Use IAP (In Application Programming) function which is executed from
+ * ROM directly, this allows flash programming to be done by code running in flash.</li>
+ * <li>Once the command is achieved, it can be detected even by polling EEFC_FSR or interrupt.
+ * </ul>
+ *
+ * The command argument could be a page number,GPNVM number or nothing, it depends on
+ * the command itself. Some useful functions in this driver could help user tranlate physical
+ * flash address into a page number and vice verse.
+ *
+ * For more accurate information, please look at the EEFC section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref hsmci_pdc.c\n
+ * \ref hsmci.h.\n
+*/
+/*@{*/
+/*@}*/
+
+/**
+ *  \file
+ */
+
+/**
+ *
+ * \section Purpose
+ *
+ * Implement MultiMediaCard(MCI) Interface Driver
+ *
+ * \section Usage
+ *
+ * -# MCI_Init(): Initializes a MCI driver instance and the underlying
+ *                peripheral.
+  * -# MCI_Handler() : Interrupt handler which is called by ISR handler.
+ * -# MCI_SetSpeed() : Configure the  MCI CLKDIV in the _MR register
+ *                     (\ref Hsmci::HSMCI_MR).
+ * -# MCI_SetBusWidth() : Configure the  MCI SDCBUS in the _SDCR register
+ *                        (\ref Hsmci::HSMCI_SDCR).
+ * -# MCI_EnableHsMode() : Configure the MCI HSMODE in the _CFG register
+ *                         (\ref Hsmci::HSMCI_CFG).
+ */
+
+#ifndef HSMCID_H
+#define HSMCID_H
+/** \addtogroup sdmmc_hal
+ *@{
+ */
+
+/*----------------------------------------------------------------------------
+ *         Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+#include <stdio.h>
+
+//#include <memories/sdmmc/sdmmc_cmd.h>
+
+/*----------------------------------------------------------------------------
+ *         Constants
+ *----------------------------------------------------------------------------*/
+
+/* Transfer type */
+
+/** MultiMedia Transfer type: no data */
+#define MCI_NO_TRANSFER     0
+/** MultiMedia Transfer type: Device to Host (read) */
+#define MCI_START_READ      1
+/** MultiMedia Transfer type: Host to Device (write) & check BUSY */
+#define MCI_START_WRITE     2
+/** Device to Host (read) without command */
+#define MCI_READ            3
+/** Host to Device (write) without command & check BUSY */
+#define MCI_WRITE           4
+/** MultiMedia Transfer type: STOP transfer */
+#define MCI_STOP_TRANSFER   5
+
+/** MCI Initialize clock 400K Hz */
+#define MCI_INITIAL_SPEED   400000
+
+/*----------------------------------------------------------------------------
+ *         Types
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ * \brief MCI Transfer Request prepared by the application upper layer.
+ *
+ * This structure is sent to the Sdmmc_SendCommand function to start the transfer.
+ * At the end of the transfer, the callback is invoked.
+ */
+typedef struct _MciCmd {
+
+    /** Command code. */
+    uint32_t cmd;
+    /** Command argument. */
+    uint32_t arg;
+    /** Data buffer, with MCI_DMA_ENABLE defined 1, the buffer can be
+     * 1, 2 or 4 bytes aligned. It has to be 4 byte aligned if no DMA.
+     */
+    uint8_t *pData;
+    /** Size of data block in bytes. */
+    uint16_t blockSize;
+    /** Number of blocks to be transfered */
+    uint16_t nbBlock;
+    /** Response buffer. */
+    uint32_t  *pResp;
+    /** Optional user-provided callback function. */
+    void (*callback)( uint8_t status, void *pArg ) ;
+    /** Optional argument to the callback function. */
+    void *pArg;
+    /** SD card command option. */
+    uint8_t resType:7,      /** Response */
+            busyCheck:1;    /** Check busy as end of command */
+    /** Indicate transfer type */
+    uint8_t tranType;
+
+    /** Indicate end of transfer status */
+    uint8_t status;
+
+    /** Command state. */
+    volatile uint8_t state;
+} MciCmd;
+
+/**
+ *  \brief MCI Driver
+ */
+typedef struct
+{
+    /** Pointer to a MCI peripheral. */
+    Hsmci *pMciHw;
+    /** Pointer to currently executing command. */
+    MciCmd *pCommand;
+    /** MCI peripheral identifier. */
+    uint8_t mciId;
+    /** Mutex. */
+    volatile uint8_t semaphore;
+} Mcid;
+
+/*----------------------------------------------------------------------------
+ *         Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void MCI_Disable(Hsmci *pMciHw);
+extern void MCI_Enable(Hsmci *pMciHw);
+extern uint8_t MCI_EnableHsMode(Mcid * pMci, uint8_t hsEnable);
+extern void MCI_Init( Mcid  *pMci, Hsmci *pMciHw, uint8_t mciId, uint32_t dwMCk ) ;
+extern uint32_t MCI_SetBusWidth(Mcid *pMci, uint32_t busWidth);
+extern uint32_t MCI_SetSpeed(Mcid *pMci, uint32_t mciSpeed, uint32_t mck);
+
+/* pdc if used */
+extern void MCI_Reset(Mcid *pMci, uint8_t keepSettings);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif //#ifndef HSMCID_H
+

firmware/atmel_softpack_libraries/libchip_sam3s/include/pio.h

@@ -0,0 +1,206 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2010, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \section Purpose
+ *
+ *  This file provides a basic API for PIO configuration and usage of
+ *  user-controlled pins. Please refer to the board.h file for a list of
+ *  available pin definitions.
+ *
+ *  \section Usage
+ *
+ *  -# Define a constant pin description array such as the following one, using
+ *     the existing definitions provided by the board.h file if possible:
+ *     \code
+ *        const Pin pPins[] = {PIN_USART0_TXD, PIN_USART0_RXD};
+ *     \endcode
+ *     Alternatively, it is possible to add new pins by provided the full Pin
+ *     structure:
+ *     \code
+ *     // Pin instance to configure PA10 & PA11 as inputs with the internal
+ *     // pull-up enabled.
+ *     const Pin pPins = {
+ *          (1 << 10) | (1 << 11),
+ *          REG_PIOA,
+ *          ID_PIOA,
+ *          PIO_INPUT,
+ *          PIO_PULLUP
+ *     };
+ *     \endcode
+ *  -# Configure a pin array by calling PIO_Configure() with a pointer to the
+ *     array and its size (which is computed using the PIO_LISTSIZE macro).
+ *  -# Change and get the value of a user-controlled pin using the PIO_Set,
+ *     PIO_Clear and PIO_Get methods.
+ *  -# Get the level being currently output by a user-controlled pin configured
+ *     as an output using PIO_GetOutputDataStatus().
+ */
+
+#ifndef _PIO_
+#define _PIO_
+
+/*
+ *         Headers
+ */
+
+#include "chip.h"
+
+#include <stdint.h>
+
+/*
+ *         Global Definitions
+ */
+
+/*  The pin is controlled by the associated signal of peripheral A. */
+#define PIO_PERIPH_A                0
+/*  The pin is controlled by the associated signal of peripheral B. */
+#define PIO_PERIPH_B                1
+/*  The pin is controlled by the associated signal of peripheral C. */
+#define PIO_PERIPH_C                2
+/*  The pin is controlled by the associated signal of peripheral D. */
+#define PIO_PERIPH_D                3
+/*  The pin is an input. */
+#define PIO_INPUT                   4
+/*  The pin is an output and has a default level of 0. */
+#define PIO_OUTPUT_0                5
+/*  The pin is an output and has a default level of 1. */
+#define PIO_OUTPUT_1                6
+
+/*  Default pin configuration (no attribute). */
+#define PIO_DEFAULT                 (0 << 0)
+/*  The internal pin pull-up is active. */
+#define PIO_PULLUP                  (1 << 0)
+/*  The internal glitch filter is active. */
+#define PIO_DEGLITCH                (1 << 1)
+/*  The pin is open-drain. */
+#define PIO_OPENDRAIN               (1 << 2)
+
+/*  The internal debouncing filter is active. */
+#define PIO_DEBOUNCE                (1 << 3)
+
+/*  Enable additional interrupt modes. */
+#define PIO_IT_AIME                 (1 << 4)
+
+/*  Interrupt High Level/Rising Edge detection is active. */
+#define PIO_IT_RE_OR_HL             (1 << 5)
+/*  Interrupt Edge detection is active. */
+#define PIO_IT_EDGE                 (1 << 6)
+
+/*  Low level interrupt is active */
+#define PIO_IT_LOW_LEVEL            (0               | 0 | PIO_IT_AIME)
+/*  High level interrupt is active */
+#define PIO_IT_HIGH_LEVEL           (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME)
+/*  Falling edge interrupt is active */
+#define PIO_IT_FALL_EDGE            (0               | PIO_IT_EDGE | PIO_IT_AIME)
+/*  Rising edge interrupt is active */
+#define PIO_IT_RISE_EDGE            (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*
+ *          Global Macros
+ */
+
+/**
+ *  Calculates the size of an array of Pin instances. The array must be defined
+ *  locally (i.e. not a pointer), otherwise the computation will not be correct.
+ *  \param pPins  Local array of Pin instances.
+ *  \return Number of elements in array.
+ */
+#define PIO_LISTSIZE(pPins)    (sizeof(pPins) / sizeof(Pin))
+
+/*
+ *         Global Types
+ */
+
+
+/*
+ *  Describes the type and attribute of one PIO pin or a group of similar pins.
+ *  The #type# field can have the following values:
+ *     - PIO_PERIPH_A
+ *     - PIO_PERIPH_B
+ *     - PIO_OUTPUT_0
+ *     - PIO_OUTPUT_1
+ *     - PIO_INPUT
+ *
+ *  The #attribute# field is a bitmask that can either be set to PIO_DEFAULt,
+ *  or combine (using bitwise OR '|') any number of the following constants:
+ *     - PIO_PULLUP
+ *     - PIO_DEGLITCH
+ *     - PIO_DEBOUNCE
+ *     - PIO_OPENDRAIN
+ *     - PIO_IT_LOW_LEVEL
+ *     - PIO_IT_HIGH_LEVEL
+ *     - PIO_IT_FALL_EDGE
+ *     - PIO_IT_RISE_EDGE
+ */
+typedef struct _Pin
+{
+    /*  Bitmask indicating which pin(s) to configure. */
+    uint32_t mask;
+    /*  Pointer to the PIO controller which has the pin(s). */
+    Pio    *pio;
+    /*  Peripheral ID of the PIO controller which has the pin(s). */
+    uint8_t id;
+    /*  Pin type. */
+    uint8_t type;
+    /*  Pin attribute. */
+    uint8_t attribute;
+} Pin ;
+
+/*
+ *         Global Access Macros
+ */
+
+/*
+ *         Global Functions
+ */
+
+extern uint8_t PIO_Configure( const Pin *list, uint32_t size ) ;
+
+extern void PIO_Set( const Pin *pin ) ;
+
+extern void PIO_Clear( const Pin *pin ) ;
+
+extern uint8_t PIO_Get( const Pin *pin ) ;
+
+extern uint8_t PIO_GetOutputDataStatus( const Pin *pin ) ;
+
+extern void PIO_SetDebounceFilter( const Pin *pin, uint32_t cuttoff );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PIO_ */
+

firmware/atmel_softpack_libraries/libchip_sam3s/include/pio_capture.h

@@ -0,0 +1,104 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2010, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \page sam3s_ppc SAM3S PIO Parallel Capture
+ *
+ *  \section Purpose
+ *
+ *  Interface for configuration the PIO Parallel Capture peripheral.
+ *
+ *  \section Usage
+ *
+ *  -# Configurate the interrupt for PIOA, can be done by PIO_InitializeInterrupts()
+ *  -# Initialize the PIO Parallel Capture API by filing the SpioCaptureInit structur.
+ *     2 options:
+ *       - alwaysSampling: for sample data with or without take in account ENABLE pins.
+ *       - halfSampling: for sample all data or only one time out of two
+ *  -# Call PIO_CaptureInit() for init and enable the PDC, init the PIO capture.
+ *  -# Call PIO_CaptureEnable() for enable the PIO Parallel Capture.
+ *  -# When an interrupt is received, the PIO_CaptureHandler() is call and the respective
+ *     callback is launch.
+ *  -# When the transfer is complete, the user need to disable interrupt with
+ *     PIO_CaptureDisableIt(). Otherway, the PDC will send an interrupt.
+ *  -# The data receive by the PIO Parallel Capture is inside the buffer passed in the
+ *     PIO_CaptureInit().
+ *
+ */
+
+#ifndef PIO_CAPTURE_H
+#define PIO_CAPTURE_H
+
+/*----------------------------------------------------------------------------
+ *        Types
+ *----------------------------------------------------------------------------*/
+
+/** \brief PIO Parallel Capture structure for initialize.
+ *
+ * At the end of the transfer, the callback is invoked by the interrupt handler.
+ */
+typedef struct _SpioCaptureInit {
+
+    /** PIO_PCRHR register is a BYTE, HALF-WORD or WORD */
+    uint8_t dsize;
+    /** PDC size, data to be received */
+    uint16_t dPDCsize;
+    /** Data to be received */
+    uint32_t *pData;
+    /** Parallel Capture Mode Always Sampling */
+    uint8_t alwaysSampling;
+    /** Parallel Capture Mode Half Sampling */
+    uint8_t halfSampling;
+    /** Parallel Capture Mode First Sample */
+    uint8_t modeFirstSample;
+    /** Callback function invoked at Mode Data Ready */
+    void (*CbkDataReady)( struct _SpioCaptureInit* );
+    /** Callback function invoked at Mode Overrun Error */
+    void (*CbkOverrun)( struct _SpioCaptureInit* );
+    /** Callback function invoked at End of Reception Transfer */
+    void (*CbkEndReception)( struct _SpioCaptureInit* );
+    /** Callback function invoked at Reception Buffer Full */
+    void (*CbkBuffFull)( struct _SpioCaptureInit* );
+    /** Callback arguments.*/
+    void *pParam;
+
+} SpioCaptureInit ;
+
+
+/*----------------------------------------------------------------------------
+ *        Global Functions
+ *----------------------------------------------------------------------------*/
+extern void PIO_CaptureDisableIt( uint32_t itToDisable ) ;
+extern void PIO_CaptureEnableIt( uint32_t itToEnable ) ;
+extern void PIO_CaptureEnable( void ) ;
+extern void PIO_CaptureDisable( void ) ;
+extern void PIO_CaptureInit( SpioCaptureInit* pInit ) ;
+
+#endif /* #ifndef PIO_CAPTURE_H */
+

firmware/atmel_softpack_libraries/libchip_sam3s/include/pio_it.h

@@ -0,0 +1,97 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \par Purpose
+ *
+ *  Configuration and handling of interrupts on PIO status changes. The API
+ *  provided here have several advantages over the traditional PIO interrupt
+ *  configuration approach:
+ *     - It is highly portable
+ *     - It automatically demultiplexes interrupts when multiples pins have been
+ *       configured on a single PIO controller
+ *     - It allows a group of pins to share the same interrupt
+ *
+ *  However, it also has several minor drawbacks that may prevent from using it
+ *  in particular applications:
+ *     - It enables the clocks of all PIO controllers
+ *     - PIO controllers all share the same interrupt handler, which does the
+ *       demultiplexing and can be slower than direct configuration
+ *     - It reserves space for a fixed number of interrupts, which can be
+ *       increased by modifying the appropriate constant in pio_it.c.
+ *
+ *  \par Usage
+ *
+ *  -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts()
+ *     with the desired priority (0 ... 7).
+ *  -# Configure a status change interrupt on one or more pin(s) with
+ *     PIO_ConfigureIt().
+ *  -# Enable & disable interrupts on pins using PIO_EnableIt() and
+ *     PIO_DisableIt().
+ */
+
+#ifndef _PIO_IT_
+#define _PIO_IT_
+
+/*
+ *         Headers
+ */
+
+#include "pio.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*
+ *         Global functions
+ */
+
+extern void PIO_InitializeInterrupts( uint32_t dwPriority ) ;
+
+extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) ) ;
+
+extern void PIO_EnableIt( const Pin *pPin ) ;
+
+extern void PIO_DisableIt( const Pin *pPin ) ;
+
+extern void PIO_IT_InterruptHandler( void ) ;
+
+extern void PioInterruptHandler( uint32_t id, Pio *pPio ) ;
+
+extern void PIO_CaptureHandler( void ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PIO_IT_ */
+

firmware/atmel_softpack_libraries/libchip_sam3s/include/pmc.h

@@ -0,0 +1,59 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _PMC_
+#define _PMC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void PMC_EnablePeripheral( uint32_t dwId ) ;
+extern void PMC_DisablePeripheral( uint32_t dwId ) ;
+
+extern void PMC_EnableAllPeripherals( void ) ;
+extern void PMC_DisableAllPeripherals( void ) ;
+
+extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PMC_ */
+

firmware/atmel_softpack_libraries/libchip_sam3s/include/spi.h

@@ -0,0 +1,115 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Interface for Serial Peripheral Interface (SPI) controller.
+ *
+ */
+
+#ifndef _SPI_
+#define _SPI_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+/*----------------------------------------------------------------------------
+ *        Macros
+ *----------------------------------------------------------------------------*/
+
+/**
+ *
+ * Here are several macros which should be used when configuring a SPI
+ * peripheral.
+ *
+ * \section spi_configuration_macros SPI Configuration Macros
+ * - \ref SPI_PCS
+ * - \ref SPI_SCBR
+ * - \ref SPI_DLYBS
+ * - \ref SPI_DLYBCT
+ */
+
+/** Calculate the PCS field value given the chip select NPCS value */
+#define SPI_PCS(npcs)       ((~(1 << npcs) & 0xF) << 16)
+
+/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */
+#define SPI_SCBR(baudrate, masterClock) ((uint32_t) (masterClock / baudrate) << 8)
+
+/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
+#define SPI_DLYBS(delay, masterClock) ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16)
+
+/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */
+#define SPI_DLYBCT(delay, masterClock) ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24)
+
+/*------------------------------------------------------------------------------ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void SPI_Enable( Spi* spi ) ;
+extern void SPI_Disable( Spi* spi ) ;
+extern void SPI_EnableIt( Spi* spi, uint32_t dwSources ) ;
+extern void SPI_DisableIt( Spi* spi, uint32_t dwSources ) ;
+
+extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration ) ;
+extern void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration ) ;
+
+extern uint32_t SPI_Read( Spi* spi ) ;
+extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData ) ;
+
+extern uint32_t SPI_GetStatus( Spi* spi ) ;
+extern uint32_t SPI_IsFinished( Spi* pSpi ) ;
+
+extern void SPI_PdcEnableTx( Spi* spi ) ;
+extern void SPI_PdcDisableTx( Spi* spi ) ;
+extern void SPI_PdcEnableRx( Spi* spi ) ;
+extern void SPI_PdcDisableRx( Spi* spi ) ;
+
+extern void SPI_PdcSetTx( Spi* spi, void* pvTxBuf, uint32_t dwTxCount, void* pvTxNextBuf, uint32_t dwTxNextCount ) ;
+extern void SPI_PdcSetRx( Spi* spi, void* pvRxBuf, uint32_t dwRxCount, void* pvRxNextBuf, uint32_t dwRxNextCount ) ;
+
+extern uint32_t SPI_WriteBuffer( Spi* spi, void* pvBuffer, uint32_t dwLength ) ;
+
+extern uint32_t SPI_ReadBuffer( Spi* spi, void* pvBuffer, uint32_t dwLength ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _SPI_ */
+

firmware/atmel_softpack_libraries/libchip_sam3s/include/tc.h

@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \section Purpose
+ *
+ *  Interface for configuring and using Timer Counter (TC) peripherals.
+ *
+ *  \section Usage
+ *  -# Optionally, use TC_FindMckDivisor() to let the program find the best
+ *     TCCLKS field value automatically.
+ *  -# Configure a Timer Counter in the desired mode using TC_Configure().
+ *  -# Start or stop the timer clock using TC_Start() and TC_Stop().
+ */
+
+#ifndef _TC_
+#define _TC_
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+
+/*------------------------------------------------------------------------------
+ *         Global functions
+ *------------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode ) ;
+
+extern void TC_Start( Tc *pTc, uint32_t dwChannel ) ;
+
+extern void TC_Stop( Tc *pTc, uint32_t dwChannel ) ;
+
+extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _TC_ */
+

firmware/atmel_softpack_libraries/libchip_sam3s/include/trace.h

@@ -0,0 +1,237 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \par Purpose
+ *
+ *  Standard output methods for reporting debug information, warnings and
+ *  errors, which can be easily be turned on/off.
+ *
+ *  \par Usage
+ *  -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually
+ *     disable ALL traces; otherwise use DBGU_Configure().
+ *  -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR()
+ *     TRACE_FATAL() macros to output traces throughout the program.
+ *  -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2
+ *     and Fatal 1. Disable a group of traces by changing the value of
+ *     TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL
+ *     are not generated. To generate no trace, use the reserved value 0.
+ *  -# Trace disabling can be static or dynamic. If dynamic disabling is selected
+ *     the trace level can be modified in runtime. If static disabling is selected
+ *     the disabled traces are not compiled.
+ *
+ *  \par traceLevels Trace level description
+ *  -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program,
+ *     and which do not produce meaningful information otherwise.
+ *  -# TRACE_INFO (4): Informational trace about the program execution. Should
+ *     enable the user to see the execution flow.
+ *  -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case
+ *     it can be discarded safely; it may even be expected.
+ *  -# TRACE_ERROR (2): Indicates an error which may not stop the program execution,
+ *     but which indicates there is a problem with the code.
+ *  -# TRACE_FATAL (1): Indicates a major error which prevents the program from going
+ *     any further.
+ */
+
+#ifndef _TRACE_
+#define _TRACE_
+
+/*
+ *         Headers
+ */
+#include "board.h"
+#include "pio.h"
+
+#include <stdio.h>
+
+/*
+ *         Global Definitions
+ */
+
+/**  Softpack Version */
+#define SOFTPACK_VERSION       "2.0"
+
+#define TRACE_LEVEL_DEBUG      5
+#define TRACE_LEVEL_INFO       4
+#define TRACE_LEVEL_WARNING    3
+#define TRACE_LEVEL_ERROR      2
+#define TRACE_LEVEL_FATAL      1
+#define TRACE_LEVEL_NO_TRACE   0
+
+/* By default, all traces are output except the debug one. */
+#if !defined(TRACE_LEVEL)
+#define TRACE_LEVEL TRACE_LEVEL_INFO
+#endif
+
+/* By default, trace level is static (not dynamic) */
+#if !defined(DYN_TRACES)
+#define DYN_TRACES 0
+#endif
+
+#if defined(NOTRACE)
+#error "Error: NOTRACE has to be not defined !"
+#endif
+
+#undef NOTRACE
+#if (DYN_TRACES==0)
+    #if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE)
+        #define NOTRACE
+    #endif
+#endif
+
+
+
+/* ------------------------------------------------------------------------------
+ *         Global Macros
+ * ------------------------------------------------------------------------------
+ */
+
+extern void TRACE_CONFIGURE( uint32_t dwBaudRate, uint32_t dwMCk ) ;
+
+/**
+ *  Initializes the DBGU for ISP project
+ *
+ *  \param mode  DBGU mode.
+ *  \param baudrate  DBGU baudrate.
+ *  \param mck  Master clock frequency.
+ */
+#ifndef DYNTRACE
+#define DYNTRACE 0
+#endif
+
+#if (TRACE_LEVEL==0) && (DYNTRACE==0)
+#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {}
+#else
+#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \
+    const Pin pinsUART0[] = {PINS_UART}; \
+    PIO_Configure(pinsUART0, PIO_LISTSIZE(pinsUART0)); \
+    UART_Configure( baudrate, mck ) ; \
+    }
+#endif
+
+/**
+ *  Outputs a formatted string using 'printf' if the log level is high
+ *  enough. Can be disabled by defining TRACE_LEVEL=0 during compilation.
+ *  \param ...  Additional parameters depending on formatted string.
+ */
+#if defined(NOTRACE)
+
+/* Empty macro */
+#define TRACE_DEBUG(...)      { }
+#define TRACE_INFO(...)       { }
+#define TRACE_WARNING(...)    { }
+#define TRACE_ERROR(...)      { }
+#define TRACE_FATAL(...)      { while(1); }
+
+#define TRACE_DEBUG_WP(...)   { }
+#define TRACE_INFO_WP(...)    { }
+#define TRACE_WARNING_WP(...) { }
+#define TRACE_ERROR_WP(...)   { }
+#define TRACE_FATAL_WP(...)   { while(1); }
+
+#elif (DYN_TRACES == 1)
+
+/* Trace output depends on dwTraceLevel value */
+#define TRACE_DEBUG(...)      { if (dwTraceLevel >= TRACE_LEVEL_DEBUG)   { printf("-D- " __VA_ARGS__); } }
+#define TRACE_INFO(...)       { if (dwTraceLevel >= TRACE_LEVEL_INFO)    { printf("-I- " __VA_ARGS__); } }
+#define TRACE_WARNING(...)    { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } }
+#define TRACE_ERROR(...)      { if (dwTraceLevel >= TRACE_LEVEL_ERROR)   { printf("-E- " __VA_ARGS__); } }
+#define TRACE_FATAL(...)      { if (dwTraceLevel >= TRACE_LEVEL_FATAL)   { printf("-F- " __VA_ARGS__); while(1); } }
+
+#define TRACE_DEBUG_WP(...)   { if (dwTraceLevel >= TRACE_LEVEL_DEBUG)   { printf(__VA_ARGS__); } }
+#define TRACE_INFO_WP(...)    { if (dwTraceLevel >= TRACE_LEVEL_INFO)    { printf(__VA_ARGS__); } }
+#define TRACE_WARNING_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } }
+#define TRACE_ERROR_WP(...)   { if (dwTraceLevel >= TRACE_LEVEL_ERROR)   { printf(__VA_ARGS__); } }
+#define TRACE_FATAL_WP(...)   { if (dwTraceLevel >= TRACE_LEVEL_FATAL)   { printf(__VA_ARGS__); while(1); } }
+
+#else
+
+/* Trace compilation depends on TRACE_LEVEL value */
+#if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG)
+#define TRACE_DEBUG(...)      { printf("-D- " __VA_ARGS__); }
+#define TRACE_DEBUG_WP(...)   { printf(__VA_ARGS__); }
+#else
+#define TRACE_DEBUG(...)      { }
+#define TRACE_DEBUG_WP(...)   { }
+#endif
+
+#if (TRACE_LEVEL >= TRACE_LEVEL_INFO)
+#define TRACE_INFO(...)       { printf("-I- " __VA_ARGS__); }
+#define TRACE_INFO_WP(...)    { printf(__VA_ARGS__); }
+#else
+#define TRACE_INFO(...)       { }
+#define TRACE_INFO_WP(...)    { }
+#endif
+
+#if (TRACE_LEVEL >= TRACE_LEVEL_WARNING)
+#define TRACE_WARNING(...)    { printf("-W- " __VA_ARGS__); }
+#define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); }
+#else
+#define TRACE_WARNING(...)    { }
+#define TRACE_WARNING_WP(...) { }
+#endif
+
+#if (TRACE_LEVEL >= TRACE_LEVEL_ERROR)
+#define TRACE_ERROR(...)      { printf("-E- " __VA_ARGS__); }
+#define TRACE_ERROR_WP(...)   { printf(__VA_ARGS__); }
+#else
+#define TRACE_ERROR(...)      { }
+#define TRACE_ERROR_WP(...)   { }
+#endif
+
+#if (TRACE_LEVEL >= TRACE_LEVEL_FATAL)
+#define TRACE_FATAL(...)      { printf("-F- " __VA_ARGS__); while(1); }
+#define TRACE_FATAL_WP(...)   { printf(__VA_ARGS__); while(1); }
+#else
+#define TRACE_FATAL(...)      { while(1); }
+#define TRACE_FATAL_WP(...)   { while(1); }
+#endif
+
+#endif
+
+#if defined(USB_NO_DEBUG)
+    #undef TRACE_DEBUG_WP
+    #define TRACE_DEBUG(...)      { }
+
+    #undef TRACE_INFO_WP
+    #define TRACE_INFO_WP(...)    { }
+#endif
+
+/**
+ *        Exported variables
+ */
+/** Depending on DYN_TRACES, dwTraceLevel is a modifable runtime variable or a define */
+#if !defined(NOTRACE) && (DYN_TRACES == 1)
+    extern uint32_t dwTraceLevel ;
+#endif
+
+#endif //#ifndef TRACE_H
+

firmware/atmel_softpack_libraries/libchip_sam3s/include/unique_id.h

@@ -0,0 +1,3 @@
+#pragma once
+
+void EEFC_ReadUniqueID(unsigned int *pdwUniqueID);

firmware/atmel_softpack_libraries/libchip_sam3s/include/usart.h

@@ -0,0 +1,139 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \par Purpose
+ *
+ * This module provides several definitions and methods for using an USART
+ * peripheral.
+ *
+ * \par Usage
+ *
+ * -# Enable the USART peripheral clock in the PMC.
+ * -# Enable the required USART PIOs (see pio.h).
+ * -# Configure the UART by calling USART_Configure.
+ * -# Enable the transmitter and/or the receiver of the USART using
+ *    USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
+ * -# Send data through the USART using the USART_Write and
+ *    USART_WriteBuffer methods.
+ * -# Receive data from the USART using the USART_Read and
+ *    USART_ReadBuffer functions; the availability of data can be polled
+ *    with USART_IsDataAvailable.
+ * -# Disable the transmitter and/or the receiver of the USART with
+ *    USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
+ */
+
+#ifndef _USART_
+#define _USART_
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+
+/*------------------------------------------------------------------------------
+ *         Definitions
+ *------------------------------------------------------------------------------*/
+
+/** \section USART_mode USART modes
+ * This section lists several common operating modes for an USART peripheral.
+ *
+ * \b Modes
+ * - USART_MODE_ASYNCHRONOUS
+ * - USART_MODE_IRDA
+ */
+
+/** Basic asynchronous mode, i.e. 8 bits no parity.*/
+#define USART_MODE_ASYNCHRONOUS        (US_MR_CHRL_8_BIT | US_MR_PAR_NO)
+
+/** IRDA mode*/
+#define USART_MODE_IRDA                (AT91C_US_USMODE_IRDA | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_FILTER)
+
+/** SPI mode*/
+#define AT91C_US_USMODE_SPIM     0xE
+#define US_SPI_CPOL_0           (0x0<<16)
+#define US_SPI_CPHA_0            (0x0<<8)
+#define US_SPI_CPOL_1            (0x1<<16)
+#define US_SPI_CPHA_1            (0x1<<8)
+#define US_SPI_BPMODE_0    (US_SPI_CPOL_0|US_SPI_CPHA_1)
+#define US_SPI_BPMODE_1    (US_SPI_CPOL_0|US_SPI_CPHA_0)
+#define US_SPI_BPMODE_2    (US_SPI_CPOL_1|US_SPI_CPHA_1)
+#define US_SPI_BPMODE_3    (US_SPI_CPOL_1|US_SPI_CPHA_0)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+typedef struct Usart_info {
+    Usart *base;
+    uint8_t state;
+    uint32_t id;
+} Usart_info;
+
+/*------------------------------------------------------------------------------*/
+/*         Exported functions                                                   */
+/*------------------------------------------------------------------------------*/
+
+extern void USART_Configure( Usart *usart, uint32_t mode, uint32_t baudrate, uint32_t masterClock ) ;
+extern uint32_t USART_GetStatus( Usart *usart ) ;
+extern void USART_EnableIt( Usart *usart,uint32_t mode ) ;
+extern void USART_DisableIt( Usart *usart,uint32_t mode ) ;
+extern void USART_SetTransmitterEnabled( Usart *usart, uint8_t enabled ) ;
+
+extern void USART_SetReceiverEnabled( Usart *usart, uint8_t enabled ) ;
+
+extern void USART_Write( Usart *usart, uint16_t data, volatile uint32_t timeOut ) ;
+
+extern uint8_t USART_WriteBuffer( Usart *usart, void *buffer, uint32_t size ) ;
+
+extern uint16_t USART_Read( Usart *usart, volatile uint32_t timeOut ) ;
+
+extern uint8_t USART_ReadBuffer( Usart *usart, void *buffer, uint32_t size ) ;
+
+extern uint8_t USART_IsDataAvailable( Usart *usart ) ;
+
+extern void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter);
+
+extern void USART_PutChar( Usart *usart, uint8_t c ) ;
+
+extern uint32_t USART_IsRxReady( Usart *usart ) ;
+
+extern uint8_t USART_GetChar( Usart *usart ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _USART_ */
+

firmware/atmel_softpack_libraries/libchip_sam3s/include/wdt.h

@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \section Purpose
+ * Interface for Watchdog Timer (WDT) controller.
+ *
+ * \section Usage
+ * -# Enable watchdog with given mode using \ref WDT_Enable().
+ * -# Disable watchdog using \ref WDT_Disable()
+ * -# Restart the watchdog using \ref WDT_Restart().
+ * -# Get watchdog status using \ref  WDT_GetStatus().
+ * -# Caculate watchdog period value using \ref WDT_GetPeriod().
+ */
+
+#ifndef _WDT_
+#define _WDT_
+
+#include "chip.h"
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode ) ;
+
+extern void WDT_Disable( Wdt* pWDT ) ;
+
+extern void WDT_Restart( Wdt* pWDT ) ;
+
+extern uint32_t WDT_GetStatus( Wdt* pWDT ) ;
+
+extern uint32_t WDT_GetPeriod( uint32_t dwMs ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _WDT_ */
+

firmware/atmel_softpack_libraries/libchip_sam3s/source/efc.c

@@ -0,0 +1,290 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup efc_module Working with EEFC
+ * The EEFC driver provides the interface to configure and use the EEFC
+ * peripheral.
+ *
+ * The user needs to set the number of wait states depending on the frequency used.\n
+ * Configure number of cycles for flash read/write operations in the FWS field of EEFC_FMR.
+ *
+ * It offers a function to send flash command to EEFC and waits for the
+ * flash to be ready.
+ *
+ * To send flash command, the user could do in either of following way:
+ * <ul>
+ * <li>Write a correct key, command and argument in EEFC_FCR. </li>
+ * <li>Or, Use IAP (In Application Programming) function which is executed from
+ * ROM directly, this allows flash programming to be done by code running in flash.</li>
+ * <li>Once the command is achieved, it can be detected even by polling EEFC_FSR or interrupt.
+ * </ul>
+ *
+ * The command argument could be a page number,GPNVM number or nothing, it depends on
+ * the command itself. Some useful functions in this driver could help user tranlate physical
+ * flash address into a page number and vice verse.
+ *
+ * For more accurate information, please look at the EEFC section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref efc.c\n
+ * \ref efc.h.\n
+*/
+/*@{*/
+/*@}*/
+
+
+/**
+ * \file
+ *
+ * Implementation of Enhanced Embedded Flash Controller (EEFC).
+ *
+ */
+
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+#include "efc.h"
+
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Enables the flash ready interrupt source on the EEFC peripheral.
+ *
+ * \param efc  Pointer to a Efc instance
+ */
+extern void EFC_EnableFrdyIt( Efc* efc )
+{
+    efc->EEFC_FMR |= EEFC_FMR_FRDY ;
+}
+
+/**
+ * \brief Disables the flash ready interrupt source on the EEFC peripheral.
+ *
+ * \param efc  Pointer to a Efc instance
+ */
+
+extern void EFC_DisableFrdyIt( Efc* efc )
+{
+    efc->EEFC_FMR &= ~((uint32_t)EEFC_FMR_FRDY) ;
+}
+
+
+/**
+ * \brief Set read/write wait state on the EEFC perpherial.
+ *
+ * \param efc  Pointer to a Efc instance
+ * \param cycles  the number of wait states in cycle.
+ */
+
+extern void EFC_SetWaitState( Efc* efc, uint8_t ucCycles )
+{
+    uint32_t dwValue ;
+
+    dwValue = efc->EEFC_FMR ;
+    dwValue &= ~((uint32_t)EEFC_FMR_FWS_Msk) ;
+    dwValue |= EEFC_FMR_FWS(ucCycles);
+    efc->EEFC_FMR = dwValue ;
+}
+
+/**
+ * \brief Returns the current status of the EEFC.
+ *
+ * \note Keep in mind that this function clears the value of some status bits (LOCKE, PROGE).
+ *
+ * \param efc  Pointer to a Efc instance
+ */
+extern uint32_t EFC_GetStatus( Efc* efc )
+{
+    return efc->EEFC_FSR ;
+}
+
+/**
+ * \brief Returns the result of the last executed command.
+ *
+ * \param efc  Pointer to a Efc instance
+ */
+extern uint32_t EFC_GetResult( Efc* efc )
+{
+    return efc->EEFC_FRR ;
+}
+
+/**
+ * \brief Translates the given address page and offset values.
+ * \note The resulting values are stored in the provided variables if they are not null.
+ *
+ * \param efc  Pointer to a Efc instance
+ * \param address  Address to translate.
+ * \param pPage  First page accessed.
+ * \param pOffset  Byte offset in first page.
+ */
+extern void EFC_TranslateAddress( Efc** ppEfc, uint32_t dwAddress, uint16_t* pwPage, uint16_t* pwOffset )
+{
+    Efc *pEfc ;
+    uint16_t wPage ;
+    uint16_t wOffset ;
+
+    assert( dwAddress >= IFLASH_ADDR ) ;
+    assert( dwAddress <= (IFLASH_ADDR + IFLASH_SIZE) ) ;
+
+    pEfc = EFC ;
+    wPage = (dwAddress - IFLASH_ADDR) / IFLASH_PAGE_SIZE;
+    wOffset = (dwAddress - IFLASH_ADDR) % IFLASH_PAGE_SIZE;
+
+    TRACE_DEBUG( "Translated 0x%08X to page=%d and offset=%d\n\r", dwAddress, wPage, wOffset ) ;
+    /* Store values */
+    if ( pEfc )
+    {
+        *ppEfc = pEfc ;
+    }
+
+    if ( pwPage )
+    {
+        *pwPage = wPage ;
+    }
+
+    if ( pwOffset )
+    {
+        *pwOffset = wOffset ;
+    }
+}
+
+/**
+ * \brief Computes the address of a flash access given the page and offset.
+ *
+ * \param efc  Pointer to a Efc instance
+ * \param page  Page number.
+ * \param offset  Byte offset inside page.
+ * \param pAddress  Computed address (optional).
+ */
+extern void EFC_ComputeAddress( Efc *efc, uint16_t wPage, uint16_t wOffset, uint32_t *pdwAddress )
+{
+    uint32_t dwAddress ;
+	
+    assert( efc ) ;
+    assert( wPage <= IFLASH_NB_OF_PAGES ) ;
+    assert( wOffset < IFLASH_PAGE_SIZE ) ;
+	
+    /* Compute address */
+    dwAddress = IFLASH_ADDR + wPage * IFLASH_PAGE_SIZE + wOffset ;
+	
+    /* Store result */
+    if ( pdwAddress != NULL )
+	{
+        *pdwAddress = dwAddress ;
+    }
+}
+
+/**
+ * \brief Starts the executing the given command on the EEFC and returns as soon as the command is started.
+ *
+ * \note It does NOT set the FMCN field automatically.
+ * \param efc  Pointer to a Efc instance
+ * \param command  Command to execute.
+ * \param argument  Command argument (should be 0 if not used).
+ */
+extern void EFC_StartCommand( Efc* efc, uint32_t dwCommand, uint32_t dwArgument )
+{
+    /* Check command & argument */
+    switch ( dwCommand )
+    {
+        case EFC_FCMD_WP:
+        case EFC_FCMD_WPL:
+        case EFC_FCMD_EWP:
+        case EFC_FCMD_EWPL:
+        case EFC_FCMD_SLB:
+        case EFC_FCMD_CLB:
+            assert( dwArgument < IFLASH_NB_OF_PAGES ) ;
+        break ;
+
+        case EFC_FCMD_SFB:
+        case EFC_FCMD_CFB:
+            assert( dwArgument < 2 ) ;
+        break;
+
+        case EFC_FCMD_GETD:
+        case EFC_FCMD_EA:
+        case EFC_FCMD_GLB:
+        case EFC_FCMD_GFB:
+        case EFC_FCMD_STUI:
+            assert( dwArgument == 0 ) ;
+        break;
+
+        default: assert( 0 ) ;
+    }
+
+    /* Start command Embedded flash */
+    assert( (efc->EEFC_FSR & EEFC_FMR_FRDY) == EEFC_FMR_FRDY ) ;
+    efc->EEFC_FCR = EEFC_FCR_FKEY(0x5A) | EEFC_FCR_FARG(dwArgument) | EEFC_FCR_FCMD(dwCommand) ;
+}
+
+/**
+ * \brief Performs the given command and wait until its completion (or an error).
+ *
+ * \param efc  Pointer to a Efc instance
+ * \param command  Command to perform.
+ * \param argument  Optional command argument.
+ *
+ * \return 0 if successful, otherwise returns an error code.
+ */
+
+extern uint32_t EFC_PerformCommand( Efc* efc, uint32_t dwCommand, uint32_t dwArgument, uint32_t dwUseIAP )
+{
+    if ( dwUseIAP != 0 )
+    {
+        /* Pointer on IAP function in ROM */
+        static uint32_t (*IAP_PerformCommand)( uint32_t, uint32_t ) ;
+
+        IAP_PerformCommand = (uint32_t (*)( uint32_t, uint32_t )) *((uint32_t*)CHIP_FLASH_IAP_ADDRESS ) ;
+        IAP_PerformCommand( 0, EEFC_FCR_FKEY(0x5A) | EEFC_FCR_FARG(dwArgument) | EEFC_FCR_FCMD(dwCommand) ) ;
+
+        return (efc->EEFC_FSR & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE)) ;
+    }
+    else
+    {
+        uint32_t dwStatus ;
+
+        efc->EEFC_FCR = EEFC_FCR_FKEY(0x5A) | EEFC_FCR_FARG(dwArgument) | EEFC_FCR_FCMD(dwCommand) ;
+        do
+        {
+            dwStatus = efc->EEFC_FSR ;
+        }
+        while ( (dwStatus & EEFC_FSR_FRDY) != EEFC_FSR_FRDY ) ;
+
+        return ( dwStatus & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE) ) ;
+    }
+}
+
+

firmware/atmel_softpack_libraries/libchip_sam3s/source/exceptions.c

@@ -0,0 +1,459 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ * This file contains the default exception handlers.
+ *
+ * \note
+ * The exception handler has weak aliases.
+ * As they are weak aliases, any function with the same name will override
+ * this definition.
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Default interrupt handler for not used irq.
+ */
+void IrqHandlerNotUsed( void )
+{
+    printf("NotUsed\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default NMI interrupt handler.
+ */
+WEAK void NMI_Handler( void )
+{
+    printf("NMI\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default HardFault interrupt handler.
+ */
+struct hardfault_args {
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r12;
+	unsigned long lr;
+	unsigned long pc;
+	unsigned long psr;
+};
+
+void hard_fault_handler_c(struct hardfault_args *args)
+{
+    printf("HardFault\r\n");
+    printf("R0=%08x, R1=%08x, R2=%08x, R3=%08x, R12=%08x\r\n",
+	   args->r0, args->r1, args->r2, args->r3, args->r12);
+    printf("LR[R14]=%08x, PC[R15]=%08x, PSR=%08x\r\n",
+	   args->lr, args->pc, args->psr);
+    printf("BFAR=%08x, CFSR=%08x, HFSR=%08x\r\n",
+	   SCB->BFAR, SCB->CFSR, SCB->HFSR);
+    printf("DFSR=%08x, AFSR=%08x, SHCSR=%08x\r\n",
+	   SCB->DFSR, SCB->CFSR, SCB->SHCSR);
+    while ( 1 ) ;
+}
+
+__attribute__((naked))
+WEAK void HardFault_Handler( void )
+{
+	__asm volatile(
+		".syntax unified	\n"
+		" tst lr, #4		\n"
+		" ite eq		\n"
+		" mrseq r0, msp		\n"
+		" mrsne r0, psp		\n"
+		//" ldr r1, [r0, #24] 	\n"
+		" b hard_fault_handler_c\n"
+		".syntax divided	\n");
+}
+
+/**
+ * \brief Default MemManage interrupt handler.
+ */
+WEAK void MemManage_Handler( void )
+{
+    printf("MemManage\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default BusFault interrupt handler.
+ */
+WEAK void BusFault_Handler( void )
+{
+    printf("BusFault\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default UsageFault interrupt handler.
+ */
+WEAK void UsageFault_Handler( void )
+{
+    printf("UsageFault\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default SVC interrupt handler.
+ */
+WEAK void SVC_Handler( void )
+{
+    printf("SVC\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default DebugMon interrupt handler.
+ */
+WEAK void DebugMon_Handler( void )
+{
+    printf("DebugMon\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default PendSV interrupt handler.
+ */
+WEAK void PendSV_Handler( void )
+{
+    printf("PendSV\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default SysTick interrupt handler.
+ */
+WEAK void SysTick_Handler( void )
+{
+    printf("SysTick\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for Supply Controller.
+ */
+WEAK void SUPC_IrqHandler( void )
+{
+    printf("SUPC\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for Reset Controller.
+ */
+WEAK void RSTC_IrqHandler( void )
+{
+    printf("RSTC\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for Real Time Clock.
+ */
+WEAK void RTC_IrqHandler( void )
+{
+    printf("RTC\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for Real Time Timer.
+ */
+WEAK void RTT_IrqHandler( void )
+{
+    printf("RTT\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for Watchdog Timer.
+ */
+WEAK void WDT_IrqHandler( void )
+{
+    printf("WDT\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for PMC.
+ */
+WEAK void PMC_IrqHandler( void )
+{
+    printf("PMC\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for EEFC.
+ */
+WEAK void EEFC_IrqHandler( void )
+{
+    printf("EEFC\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for UART0.
+ */
+WEAK void UART0_IrqHandler( void )
+{
+    printf("UART0\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for UART1.
+ */
+WEAK void UART1_IrqHandler( void )
+{
+    printf("UART1\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for SMC.
+ */
+WEAK void SMC_IrqHandler( void )
+{
+    printf("SMC\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for PIOA Controller.
+ */
+WEAK void PIOA_IrqHandler( void )
+{
+    printf("PIOA\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for PIOB Controller.
+ */
+WEAK void PIOB_IrqHandler( void )
+{
+    printf("PIOB\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for PIOC Controller.
+ */
+WEAK void PIOC_IrqHandler( void )
+{
+    printf("PIOC\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for USART0.
+ */
+WEAK void USART0_IrqHandler( void )
+{
+    printf("USART0\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for USART1.
+ */
+WEAK void USART1_IrqHandler( void )
+{
+    printf("USART1\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for MCI.
+ */
+WEAK void MCI_IrqHandler( void )
+{
+    printf("MCI\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for TWI0.
+ */
+WEAK void TWI0_IrqHandler( void )
+{
+    printf("TWI0\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for TWI1.
+ */
+WEAK void TWI1_IrqHandler( void )
+{
+    printf("TWI1\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for SPI.
+ */
+WEAK void SPI_IrqHandler( void )
+{
+    printf("SPI\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for SSC.
+ */
+WEAK void SSC_IrqHandler( void )
+{
+    printf("SSC\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for TC0.
+ */
+WEAK void TC0_IrqHandler( void )
+{
+    printf("TC0\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for TC1.
+ */
+WEAK void TC1_IrqHandler( void )
+{
+    printf("TC1\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default interrupt handler for TC2.
+ */
+WEAK void TC2_IrqHandler( void )
+{
+    printf("TC2\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default SUPC interrupt handler for TC3.
+ */
+WEAK void TC3_IrqHandler( void )
+{
+    printf("TC3\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default SUPC interrupt handler for TC4.
+ */
+WEAK void TC4_IrqHandler( void )
+{
+    printf("TC4\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default SUPC interrupt handler for TC5.
+ */
+WEAK void TC5_IrqHandler( void )
+{
+    printf("TC5\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default SUPC interrupt handler for ADC.
+ */
+WEAK void ADC_IrqHandler( void )
+{
+    printf("ADC\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default SUPC interrupt handler for DAC.
+ */
+WEAK void DAC_IrqHandler( void )
+{
+    printf("DAC\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default SUPC interrupt handler for PWM.
+ */
+WEAK void PWM_IrqHandler( void )
+{
+    printf("PWM\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default SUPC interrupt handler for CRCCU.
+ */
+WEAK void CRCCU_IrqHandler( void )
+{
+    printf("CRCCU\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default SUPC interrupt handler for ACC.
+ */
+WEAK void ACC_IrqHandler( void )
+{
+    printf("ACC\r\n");
+    while ( 1 ) ;
+}
+
+/**
+ * \brief Default SUPC interrupt handler for USBD.
+ */
+WEAK void USBD_IrqHandler( void )
+{
+    printf("USBD\r\n");
+    while ( 1 ) ;
+}

firmware/atmel_softpack_libraries/libchip_sam3s/source/flashd.c

@@ -0,0 +1,514 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup flashd_module Flash Memory Interface
+ * The flash driver manages the programming, erasing, locking and unlocking sequences
+ * with dedicated commands.
+ *
+ * To implement flash programing operation, the user has to follow these few steps :
+ * <ul>
+ * <li>Configue flash wait states to initializes the flash. </li>
+ * <li>Checks whether a region to be programmed is locked. </li>
+ * <li>Unlocks the user region to be programmed if the region have locked before.</li>
+ * <li>Erases the user page before program (optional).</li>
+ * <li>Writes the user page from the page buffer.</li>
+ * <li>Locks the region of programmed area if any.</li>
+ * </ul>
+ *
+ * Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
+ * A check of this validity and padding for 32-bit alignment should be done in write algorithm.
+
+ * Lock/unlock range associated with the user address range is automatically translated.
+ *
+ * This security bit can be enabled through the command "Set General Purpose NVM Bit 0".
+ *
+ * A 128-bit factory programmed unique ID could be read to serve several purposes.
+ *
+ * The driver accesses the flash memory by calling the lowlevel module provided in \ref efc_module.
+ * For more accurate information, please look at the EEFC section of the Datasheet.
+ *
+ * Related files :\n
+ * \ref flashd.c\n
+ * \ref flashd.h.\n
+ * \ref efc.c\n
+ * \ref efc.h.\n
+*/
+/*@{*/
+/*@}*/
+
+
+/**
+ * \file
+ *
+ * The flash driver provides the unified interface for flash program operations.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+#include "flashd.h"
+#include "efc.h"
+
+#include <string.h>
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *        Local variables
+ *----------------------------------------------------------------------------*/
+
+//static NO_INIT uint8_t _aucPageBuffer[IFLASH_PAGE_SIZE] ;
+static NO_INIT uint32_t _adwPageBuffer[IFLASH_PAGE_SIZE/4] ;
+static uint8_t* _aucPageBuffer = (uint8_t*)_adwPageBuffer;
+static NO_INIT uint32_t _dwUseIAP ;
+
+/*----------------------------------------------------------------------------
+ *        Local macros
+ *----------------------------------------------------------------------------*/
+
+#define min( a, b ) (((a) < (b)) ? (a) : (b))
+
+/*----------------------------------------------------------------------------
+ *        Local functions
+ *----------------------------------------------------------------------------*/
+
+
+/**
+ * \brief Computes the lock range associated with the given address range.
+ *
+ * \param dwStart  Start address of lock range.
+ * \param dwEnd  End address of lock range.
+ * \param pdwActualStart  Actual start address of lock range.
+ * \param pdwActualEnd  Actual end address of lock range.
+ */
+static void ComputeLockRange( uint32_t dwStart, uint32_t dwEnd, uint32_t *pdwActualStart, uint32_t *pdwActualEnd )
+{
+    Efc* pStartEfc ;
+    Efc* pEndEfc ;
+    uint16_t wStartPage ;
+    uint16_t wEndPage ;
+    uint16_t wNumPagesInRegion ;
+    uint16_t wActualStartPage ;
+    uint16_t wActualEndPage ;
+
+    // Convert start and end address in page numbers
+    EFC_TranslateAddress( &pStartEfc, dwStart, &wStartPage, 0 ) ;
+    EFC_TranslateAddress( &pEndEfc, dwEnd, &wEndPage, 0 ) ;
+
+    // Find out the first page of the first region to lock
+    wNumPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE ;
+    wActualStartPage = wStartPage - (wStartPage % wNumPagesInRegion) ;
+    wActualEndPage = wEndPage ;
+
+    if ( (wEndPage % wNumPagesInRegion) != 0 )
+    {
+        wActualEndPage += wNumPagesInRegion - (wEndPage % wNumPagesInRegion) ;
+    }
+    // Store actual page numbers
+    EFC_ComputeAddress( pStartEfc, wActualStartPage, 0, pdwActualStart ) ;
+    EFC_ComputeAddress( pEndEfc, wActualEndPage, 0, pdwActualEnd ) ;
+    TRACE_DEBUG( "Actual lock range is 0x%06X - 0x%06X\n\r", *pdwActualStart, *pdwActualEnd ) ;
+}
+
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Initializes the flash driver.
+ *
+ * \param mck  Master clock frequency in Hz.
+ */
+
+extern void FLASHD_Initialize( uint32_t dwMCk, uint32_t dwUseIAP )
+{
+    EFC_DisableFrdyIt( EFC ) ;
+	
+    if ( (dwMCk/1000000) >= 64 )
+	{
+        EFC_SetWaitState( EFC, 2 ) ;
+    }
+    else
+	{
+	    if ( (dwMCk/1000000) >= 50 )
+	    {
+            EFC_SetWaitState( EFC, 1 ) ;
+        }
+        else
+	    {
+            EFC_SetWaitState( EFC, 0 ) ;
+        }
+	}
+
+    _dwUseIAP=dwUseIAP ;
+}
+
+/**
+ * \brief Erases the entire flash.
+ *
+ * \param address  Flash start address.
+ * \return 0 if successful; otherwise returns an error code.
+ */
+extern uint32_t FLASHD_Erase( uint32_t dwAddress )
+{
+    Efc* pEfc ;
+    uint16_t wPage ;
+    uint16_t wOffset ;
+    uint32_t dwError ;
+
+    assert( (dwAddress >=IFLASH_ADDR) || (dwAddress <= (IFLASH_ADDR + IFLASH_SIZE)) ) ;
+
+    // Translate write address
+    EFC_TranslateAddress( &pEfc, dwAddress, &wPage, &wOffset ) ;
+    dwError = EFC_PerformCommand( pEfc, EFC_FCMD_EA, 0, _dwUseIAP ) ;
+	
+    return dwError ;
+}
+
+/**
+ * \brief Writes a data buffer in the internal flash
+ *
+ * \note This function works in polling mode, and thus only returns when the
+ * data has been effectively written.
+ * \param address  Write address.
+ * \param pBuffer  Data buffer.
+ * \param size  Size of data buffer in bytes.
+ * \return 0 if successful, otherwise returns an error code.
+ */
+extern uint32_t FLASHD_Write( uint32_t dwAddress, const void *pvBuffer, uint32_t dwSize )
+{
+    Efc* pEfc ;
+    uint16_t page ;
+    uint16_t offset ;
+    uint32_t writeSize ;
+    uint32_t pageAddress ;
+    uint16_t padding ;
+    uint32_t dwError ;
+    uint32_t sizeTmp ;
+    uint32_t *pAlignedDestination ;
+    uint32_t *pAlignedSource ;
+
+    assert( pvBuffer ) ;
+    assert( dwAddress >=IFLASH_ADDR ) ;
+    assert( (dwAddress + dwSize) <= (IFLASH_ADDR + IFLASH_SIZE) ) ;
+
+    /* Translate write address */
+    EFC_TranslateAddress( &pEfc, dwAddress, &page, &offset ) ;
+
+    /* Write all pages */
+    while ( dwSize > 0 )
+    {
+        /* Copy data in temporary buffer to avoid alignment problems */
+        writeSize = min((uint32_t)IFLASH_PAGE_SIZE - offset, dwSize ) ;
+        EFC_ComputeAddress(pEfc, page, 0, &pageAddress ) ;
+        padding = IFLASH_PAGE_SIZE - offset - writeSize ;
+
+        /* Pre-buffer data */
+        memcpy( _aucPageBuffer, (void *) pageAddress, offset);
+
+        /* Buffer data */
+        memcpy( _aucPageBuffer + offset, pvBuffer, writeSize);
+
+        /* Post-buffer data */
+        memcpy( _aucPageBuffer + offset + writeSize, (void *) (pageAddress + offset + writeSize), padding);
+
+        /* Write page
+         * Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption
+         */
+        pAlignedDestination = (uint32_t*)pageAddress ;
+        pAlignedSource = (uint32_t*)_adwPageBuffer ;
+        sizeTmp = IFLASH_PAGE_SIZE ;
+
+        while ( sizeTmp >= 4 )
+        {
+            *pAlignedDestination++ = *pAlignedSource++;
+            sizeTmp -= 4;
+        }
+
+        /* Send writing command */
+        dwError = EFC_PerformCommand( pEfc, EFC_FCMD_EWP, page, _dwUseIAP ) ;
+        if ( dwError )
+        {
+            return dwError ;
+        }
+
+        /* Progression */
+        dwAddress += IFLASH_PAGE_SIZE ;
+        pvBuffer = (void *)((uint32_t) pvBuffer + writeSize) ;
+        dwSize -= writeSize ;
+        page++;
+        offset = 0;
+    }
+
+    return 0 ;
+}
+/**
+ * \brief Locks all the regions in the given address range. The actual lock range is
+ * reported through two output parameters.
+ *
+ * \param start  Start address of lock range.
+ * \param end    End address of lock range.
+ * \param pActualStart  Start address of the actual lock range (optional).
+ * \param pActualEnd  End address of the actual lock range (optional).
+ * \return 0 if successful, otherwise returns an error code.
+ */
+extern uint32_t FLASHD_Lock( uint32_t start, uint32_t end, uint32_t *pActualStart, uint32_t *pActualEnd )
+{
+    Efc *pEfc ;
+    uint32_t actualStart, actualEnd ;
+    uint16_t startPage, endPage ;
+    uint32_t dwError ;
+    uint16_t numPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE;
+
+    /* Compute actual lock range and store it */
+    ComputeLockRange( start, end, &actualStart, &actualEnd ) ;
+    if ( pActualStart != NULL )
+    {
+        *pActualStart = actualStart ;
+    }
+    if ( pActualEnd != NULL )
+    {
+        *pActualEnd = actualEnd;
+    }
+
+    /* Compute page numbers */
+    EFC_TranslateAddress( &pEfc, actualStart, &startPage, 0 ) ;
+    EFC_TranslateAddress( 0, actualEnd, &endPage, 0 ) ;
+
+    /* Lock all pages */
+    while ( startPage < endPage )
+    {
+        dwError = EFC_PerformCommand( pEfc, EFC_FCMD_SLB, startPage, _dwUseIAP ) ;
+        if ( dwError )
+        {
+            return dwError ;
+        }
+        startPage += numPagesInRegion;
+    }
+
+    return 0 ;
+}
+
+/**
+ * \brief Unlocks all the regions in the given address range. The actual unlock range is
+ * reported through two output parameters.
+ * \param start  Start address of unlock range.
+ * \param end  End address of unlock range.
+ * \param pActualStart  Start address of the actual unlock range (optional).
+ * \param pActualEnd  End address of the actual unlock range (optional).
+ * \return 0 if successful, otherwise returns an error code.
+ */
+extern uint32_t FLASHD_Unlock( uint32_t start, uint32_t end, uint32_t *pActualStart, uint32_t *pActualEnd )
+{
+    Efc* pEfc ;
+    uint32_t actualStart, actualEnd ;
+    uint16_t startPage, endPage ;
+    uint32_t dwError ;
+    uint16_t numPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE;
+
+    // Compute actual unlock range and store it
+    ComputeLockRange(start, end, &actualStart, &actualEnd);
+    if ( pActualStart != NULL )
+    {
+        *pActualStart = actualStart ;
+    }
+    if ( pActualEnd != NULL )
+    {
+        *pActualEnd = actualEnd ;
+    }
+
+    // Compute page numbers
+    EFC_TranslateAddress( &pEfc, actualStart, &startPage, 0 ) ;
+    EFC_TranslateAddress( 0, actualEnd, &endPage, 0 ) ;
+
+    // Unlock all pages
+    while ( startPage < endPage )
+    {
+        dwError = EFC_PerformCommand( pEfc, EFC_FCMD_CLB, startPage, _dwUseIAP ) ;
+        if ( dwError )
+        {
+            return dwError ;
+        }
+        startPage += numPagesInRegion ;
+    }
+    return 0 ;
+}
+
+/**
+ * \brief Returns the number of locked regions inside the given address range.
+ *
+ * \param start  Start address of range
+ * \param end    End address of range.
+ */
+extern uint32_t FLASHD_IsLocked( uint32_t start, uint32_t end )
+{
+    Efc *pEfc ;
+    uint16_t startPage, endPage ;
+    uint8_t startRegion, endRegion ;
+    uint32_t numPagesInRegion ;
+    uint32_t status ;
+    uint32_t dwError ;
+    uint32_t numLockedRegions = 0 ;
+
+    assert( end >= start ) ;
+    assert( (start >=IFLASH_ADDR) && (end <= IFLASH_ADDR + IFLASH_SIZE) ) ;
+
+    // Compute page numbers
+    EFC_TranslateAddress( &pEfc, start, &startPage, 0 ) ;
+    EFC_TranslateAddress( 0, end, &endPage, 0 ) ;
+
+    // Compute region numbers
+    numPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE ;
+    startRegion = startPage / numPagesInRegion ;
+    endRegion = endPage / numPagesInRegion ;
+    if ((endPage % numPagesInRegion) != 0)
+    {
+        endRegion++ ;
+    }
+
+    // Retrieve lock status
+    dwError = EFC_PerformCommand( pEfc, EFC_FCMD_GLB, 0, _dwUseIAP ) ;
+    assert( !dwError ) ;
+    status = EFC_GetResult( pEfc ) ;
+
+    // Check status of each involved region
+    while ( startRegion < endRegion )
+    {
+        if ( (status & (1 << startRegion)) != 0 )
+        {
+            numLockedRegions++ ;
+        }
+        startRegion++ ;
+    }
+
+    return numLockedRegions ;
+}
+
+/**
+ * \brief Check if the given GPNVM bit is set or not.
+ *
+ * \param gpnvm  GPNVM bit index.
+ * \returns 1 if the given GPNVM bit is currently set; otherwise returns 0.
+ */
+extern uint32_t FLASHD_IsGPNVMSet( uint8_t ucGPNVM )
+{
+    uint32_t dwError ;
+    uint32_t dwStatus ;
+
+    assert( ucGPNVM < 2 ) ;
+
+    /* Get GPNVMs status */
+    dwError = EFC_PerformCommand( EFC, EFC_FCMD_GFB, 0, _dwUseIAP ) ;
+    assert( !dwError ) ;
+    dwStatus = EFC_GetResult( EFC ) ;
+
+    /* Check if GPNVM is set */
+    if ( (dwStatus & (1 << ucGPNVM)) != 0 )
+    {
+        return 1 ;
+    }
+    else
+    {
+        return 0 ;
+    }
+}
+
+/**
+ * \brief Sets the selected GPNVM bit.
+ *
+ * \param gpnvm  GPNVM bit index.
+ * \returns 0 if successful; otherwise returns an error code.
+ */
+extern uint32_t FLASHD_SetGPNVM( uint8_t ucGPNVM )
+{
+    assert( ucGPNVM < 2 ) ;
+
+    if ( !FLASHD_IsGPNVMSet( ucGPNVM ) )
+    {
+        return EFC_PerformCommand( EFC, EFC_FCMD_SFB, ucGPNVM, _dwUseIAP ) ;
+    }
+    else
+    {
+        return 0 ;
+    }
+}
+
+/**
+ * \brief Clears the selected GPNVM bit.
+ *
+ * \param gpnvm  GPNVM bit index.
+ * \returns 0 if successful; otherwise returns an error code.
+ */
+extern uint32_t FLASHD_ClearGPNVM( uint8_t ucGPNVM )
+{
+    assert( ucGPNVM < 2 ) ;
+
+    if ( FLASHD_IsGPNVMSet( ucGPNVM ) )
+    {
+        return EFC_PerformCommand( EFC, EFC_FCMD_CFB, ucGPNVM, _dwUseIAP ) ;
+    }
+    else
+    {
+        return 0 ;
+    }
+}
+/**
+ * \brief Read the unique ID.
+ *
+ * \param uniqueID pointer on a 4bytes char containing the unique ID value.
+ * \returns 0 if successful; otherwise returns an error code.
+ */
+extern uint32_t FLASHD_ReadUniqueID( uint32_t* pdwUniqueID )
+{
+    uint32_t dwError ;
+
+    assert( pdwUniqueID != NULL ) ;
+
+    pdwUniqueID[0] = 0 ;
+    pdwUniqueID[1] = 0 ;
+    pdwUniqueID[2] = 0 ;
+    pdwUniqueID[3] = 0 ;
+
+    EFC_StartCommand( EFC, EFC_FCMD_STUI, 0 ) ;
+
+    pdwUniqueID[0] = *(uint32_t*) IFLASH_ADDR;
+    pdwUniqueID[1] = *(uint32_t*)(IFLASH_ADDR + 4) ;
+    pdwUniqueID[2] = *(uint32_t*)(IFLASH_ADDR + 8) ;
+    pdwUniqueID[3] = *(uint32_t*)(IFLASH_ADDR + 12) ;
+
+    dwError = EFC_PerformCommand( EFC, EFC_FCMD_SPUI, 0, _dwUseIAP ) ;
+    if ( dwError )
+    {
+        return dwError ;
+    }
+
+    return 0 ;
+}

firmware/atmel_softpack_libraries/libchip_sam3s/source/pio.c

@@ -0,0 +1,453 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2010, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \file */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+#include "pio.h"
+#include "pmc.h"
+
+/*----------------------------------------------------------------------------
+ *        Local functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures one or more pin(s) of a PIO controller as being controlled by
+ * peripheral A. Optionally, the corresponding internal pull-up(s) can be enabled.
+ *
+ * \param pio  Pointer to a PIO controller.
+ * \param mask  Bitmask of one or more pin(s) to configure.
+ * \param enablePullUp  Indicates if the pin(s) internal pull-up shall be
+ *                      configured.
+ */
+static void PIO_SetPeripheralA(
+    Pio *pio,
+    unsigned int mask,
+    unsigned char enablePullUp)
+{
+    unsigned int abcdsr;
+    /* Disable interrupts on the pin(s) */
+    pio->PIO_IDR = mask;
+
+    /* Enable the pull-up(s) if necessary */
+    if (enablePullUp) {
+        pio->PIO_PUER = mask;
+    }
+    else {
+
+        pio->PIO_PUDR = mask;
+    }
+
+    abcdsr = pio->PIO_ABCDSR[0];
+    pio->PIO_ABCDSR[0] &= (~mask & abcdsr);
+    abcdsr = pio->PIO_ABCDSR[1];
+    pio->PIO_ABCDSR[1] &= (~mask & abcdsr);
+    pio->PIO_PDR = mask;
+}
+
+/**
+ * \brief Configures one or more pin(s) of a PIO controller as being controlled by
+ * peripheral B. Optionally, the corresponding internal pull-up(s) can be enabled.
+ *
+ * \param pio  Pointer to a PIO controller.
+ * \param mask  Bitmask of one or more pin(s) to configure.
+ * \param enablePullUp  Indicates if the pin(s) internal pull-up shall be
+ *                      configured.
+ */
+static void PIO_SetPeripheralB(
+    Pio *pio,
+    unsigned int mask,
+    unsigned char enablePullUp)
+{
+    unsigned int abcdsr;
+    /* Disable interrupts on the pin(s) */
+    pio->PIO_IDR = mask;
+
+    /* Enable the pull-up(s) if necessary */
+    if (enablePullUp) {
+
+        pio->PIO_PUER = mask;
+    }
+    else {
+
+        pio->PIO_PUDR = mask;
+    }
+
+    abcdsr = pio->PIO_ABCDSR[0];
+    pio->PIO_ABCDSR[0] = (mask | abcdsr);
+    abcdsr = pio->PIO_ABCDSR[1];
+    pio->PIO_ABCDSR[1] &= (~mask & abcdsr);
+
+    pio->PIO_PDR = mask;
+}
+
+/**
+ * \brief Configures one or more pin(s) of a PIO controller as being controlled by
+ * peripheral C. Optionally, the corresponding internal pull-up(s) can be enabled.
+ *
+ * \param pio  Pointer to a PIO controller.
+ * \param mask  Bitmask of one or more pin(s) to configure.
+ * \param enablePullUp  Indicates if the pin(s) internal pull-up shall be
+ *                      configured.
+ */
+static void PIO_SetPeripheralC(
+    Pio *pio,
+    unsigned int mask,
+    unsigned char enablePullUp)
+{
+    unsigned int abcdsr;
+    /* Disable interrupts on the pin(s) */
+    pio->PIO_IDR = mask;
+
+    /* Enable the pull-up(s) if necessary */
+    if (enablePullUp) {
+
+        pio->PIO_PUER = mask;
+    }
+    else {
+
+        pio->PIO_PUDR = mask;
+    }
+
+    abcdsr = pio->PIO_ABCDSR[0];
+    pio->PIO_ABCDSR[0] &= (~mask & abcdsr);
+    abcdsr = pio->PIO_ABCDSR[1];
+    pio->PIO_ABCDSR[1] = (mask | abcdsr);
+
+    pio->PIO_PDR = mask;
+}
+
+/**
+ * \brief Configures one or more pin(s) of a PIO controller as being controlled by
+ * peripheral D. Optionally, the corresponding internal pull-up(s) can be enabled.
+ *
+ * \param pio  Pointer to a PIO controller.
+ * \param mask  Bitmask of one or more pin(s) to configure.
+ * \param enablePullUp  Indicates if the pin(s) internal pull-up shall be
+ *                      configured.
+ */
+static void PIO_SetPeripheralD(
+    Pio *pio,
+    unsigned int mask,
+    unsigned char enablePullUp)
+{
+    unsigned int abcdsr;
+    /* Disable interrupts on the pin(s) */
+    pio->PIO_IDR = mask;
+
+    /* Enable the pull-up(s) if necessary */
+    if (enablePullUp) {
+
+        pio->PIO_PUER = mask;
+    }
+    else {
+
+        pio->PIO_PUDR = mask;
+    }
+
+    abcdsr = pio->PIO_ABCDSR[0];
+    pio->PIO_ABCDSR[0] = (mask | abcdsr);
+    abcdsr = pio->PIO_ABCDSR[1];
+    pio->PIO_ABCDSR[1] = (mask | abcdsr);
+
+    pio->PIO_PDR = mask;
+}
+
+/**
+ * \brief Configures one or more pin(s) or a PIO controller as inputs. Optionally,
+ * the corresponding internal pull-up(s) and glitch filter(s) can be enabled.
+ *
+ * \param pio  Pointer to a PIO controller.
+ * \param mask  Bitmask indicating which pin(s) to configure as input(s).
+ * \param enablePullUp  Indicates if the internal pull-up(s) must be enabled.
+ * \param enableFilter  Indicates if the glitch filter(s) must be enabled.
+ */
+static void PIO_SetInput(
+    Pio *pio,
+    unsigned int mask,
+    unsigned char attribute)
+{
+    /* Disable interrupts */
+    pio->PIO_IDR = mask;
+
+    /* Enable pull-up(s) if necessary */
+    if (attribute & PIO_PULLUP)
+        pio->PIO_PUER = mask;
+    else
+        pio->PIO_PUDR = mask;
+
+    /* Enable Input Filter if necessary */
+    if (attribute & (PIO_DEGLITCH | PIO_DEBOUNCE))
+        pio->PIO_IFER = mask;
+    else
+        pio->PIO_IFDR = mask;
+
+    /* Enable de-glitch or de-bounce if necessary */
+    if (attribute & PIO_DEGLITCH)
+    {
+        pio->PIO_IFSCDR = mask;
+    }
+    else
+    {
+        if (attribute & PIO_DEBOUNCE)
+        {
+            pio->PIO_IFSCER = mask;
+        }
+    }
+
+    /* Configure pin as input */
+    pio->PIO_ODR = mask;
+    pio->PIO_PER = mask;
+}
+
+/**
+ * \brief Configures one or more pin(s) of a PIO controller as outputs, with the
+ * given default value. Optionally, the multi-drive feature can be enabled
+ * on the pin(s).
+ *
+ * \param pio  Pointer to a PIO controller.
+ * \param mask  Bitmask indicating which pin(s) to configure.
+ * \param defaultValue  Default level on the pin(s).
+ * \param enableMultiDrive  Indicates if the pin(s) shall be configured as
+ *                          open-drain.
+ * \param enablePullUp  Indicates if the pin shall have its pull-up activated.
+ */
+static void PIO_SetOutput(
+    Pio *pio,
+    unsigned int mask,
+    unsigned char defaultValue,
+    unsigned char enableMultiDrive,
+    unsigned char enablePullUp)
+{
+    /* Disable interrupts */
+    pio->PIO_IDR = mask;
+
+    /* Enable pull-up(s) if necessary */
+    if (enablePullUp) {
+
+        pio->PIO_PUER = mask;
+    }
+    else {
+
+        pio->PIO_PUDR = mask;
+    }
+
+    /* Enable multi-drive if necessary */
+    if (enableMultiDrive) {
+
+        pio->PIO_MDER = mask;
+    }
+    else {
+
+        pio->PIO_MDDR = mask;
+    }
+
+    /* Set default value */
+    if (defaultValue) {
+
+        pio->PIO_SODR = mask;
+    }
+    else {
+
+        pio->PIO_CODR = mask;
+    }
+
+    /* Configure pin(s) as output(s) */
+    pio->PIO_OER = mask;
+    pio->PIO_PER = mask;
+}
+
+/*----------------------------------------------------------------------------
+ *         Global functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures a list of Pin instances, each of which can either hold a single
+ * pin or a group of pins, depending on the mask value; all pins are configured
+ * by this function. The size of the array must also be provided and is easily
+ * computed using PIO_LISTSIZE whenever its length is not known in advance.
+ *
+ * \param list  Pointer to a list of Pin instances.
+ * \param size  Size of the Pin list (calculated using PIO_LISTSIZE).
+ *
+ * \return 1 if the pins have been configured properly; otherwise 0.
+ */
+uint8_t PIO_Configure( const Pin *list, uint32_t size )
+{
+    /* Configure pins */
+    while ( size > 0 )
+    {
+        switch ( list->type )
+        {
+
+            case PIO_PERIPH_A:
+                PIO_SetPeripheralA(list->pio,
+                                   list->mask,
+                                   (list->attribute & PIO_PULLUP) ? 1 : 0);
+            break;
+
+            case PIO_PERIPH_B:
+                PIO_SetPeripheralB(list->pio,
+                                   list->mask,
+                                   (list->attribute & PIO_PULLUP) ? 1 : 0);
+            break;
+
+            case PIO_PERIPH_C:
+                PIO_SetPeripheralC(list->pio,
+                                   list->mask,
+                                   (list->attribute & PIO_PULLUP) ? 1 : 0);
+            break;
+
+            case PIO_PERIPH_D:
+                PIO_SetPeripheralD(list->pio,
+                                   list->mask,
+                                   (list->attribute & PIO_PULLUP) ? 1 : 0);
+            break;
+            case PIO_INPUT:
+                PMC_EnablePeripheral(list->id);
+                PIO_SetInput(list->pio,
+                             list->mask,
+                             list->attribute);
+                break;
+
+            case PIO_OUTPUT_0:
+            case PIO_OUTPUT_1:
+                PIO_SetOutput(list->pio,
+                              list->mask,
+                              (list->type == PIO_OUTPUT_1),
+                              (list->attribute & PIO_OPENDRAIN) ? 1 : 0,
+                              (list->attribute & PIO_PULLUP) ? 1 : 0);
+                break;
+
+            default: return 0;
+        }
+
+        list++;
+        size--;
+    }
+
+    return 1;
+}
+
+/**
+ * \brief Sets a high output level on all the PIOs defined in the given Pin instance.
+ * This has no immediate effects on PIOs that are not output, but the PIO
+ * controller will memorize the value they are changed to outputs.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ */
+void PIO_Set(const Pin *pin)
+{
+    pin->pio->PIO_SODR = pin->mask;
+}
+
+/**
+ * \brief Sets a low output level on all the PIOs defined in the given Pin instance.
+ * This has no immediate effects on PIOs that are not output, but the PIO
+ * controller will memorize the value they are changed to outputs.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ */
+void PIO_Clear(const Pin *pin)
+{
+    pin->pio->PIO_CODR = pin->mask;
+}
+
+/**
+ * \brief Returns 1 if one or more PIO of the given Pin instance currently have
+ * a high level; otherwise returns 0. This method returns the actual value that
+ * is being read on the pin. To return the supposed output value of a pin, use
+ * PIO_GetOutputDataStatus() instead.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ *
+ * \return 1 if the Pin instance contains at least one PIO that currently has
+ * a high level; otherwise 0.
+ */
+unsigned char PIO_Get( const Pin *pin )
+{
+    unsigned int reg ;
+
+    if ( (pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1) )
+    {
+        reg = pin->pio->PIO_ODSR ;
+    }
+    else
+    {
+        reg = pin->pio->PIO_PDSR ;
+    }
+
+    if ( (reg & pin->mask) == 0 )
+    {
+        return 0 ;
+    }
+    else
+    {
+        return 1 ;
+    }
+}
+
+/**
+ * \brief Returns 1 if one or more PIO of the given Pin are configured to output a
+ * high level (even if they are not output).
+ * To get the actual value of the pin, use PIO_Get() instead.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ *
+ * \return 1 if the Pin instance contains at least one PIO that is configured
+ * to output a high level; otherwise 0.
+ */
+unsigned char PIO_GetOutputDataStatus(const Pin *pin)
+{
+    if ((pin->pio->PIO_ODSR & pin->mask) == 0) {
+
+        return 0;
+    }
+    else {
+
+        return 1;
+    }
+}
+
+/*
+ * \brief Configures Glitch or Debouncing filter for input.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ * \param cuttoff  Cutt off frequency for debounce filter.
+ */
+void PIO_SetDebounceFilter( const Pin *pin, uint32_t cuttoff )
+{
+    Pio *pio = pin->pio;
+
+    pio->PIO_IFSCER = pin->mask; /* set Debouncing, 0 bit field no effect */
+    pio->PIO_SCDR = ((32678/(2*(cuttoff))) - 1) & 0x3FFF; /* the lowest 14 bits work */
+}

firmware/atmel_softpack_libraries/libchip_sam3s/source/pio_capture.c

@@ -0,0 +1,283 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2010, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup pio_capture_module Working with PIO Parallel Capture Mode
+ * The PIO Parallel Capture Mode driver provides the interface to configure and use the
+ * PIO Parallel Capture Mode peripheral.\n
+ *
+ * The PIO Controller integrates an interface able to read data from a CMOS digital
+ * image sensor, a high-speed parallel ADC, a DSP synchronous port in synchronous
+ * mode, etc.... For better understanding and to ease reading, the following
+ * description uses an example with a CMOS digital image sensor
+ *
+ * To use the PIO Parallel Capture, the user has to follow these few steps:
+ * <ul>
+ *   <li> Enable PIOA peripheral clock </li>
+ *   <li> Configure the PDC </li>
+ *   <li> Configure the PIO Capture interrupt </li>
+ *   <li> Enable the PDC </li>
+ *   <li> Enable the PIO Capture </li>
+ *   <li> Wait for interrupt </li>
+ *   <li> Disable the interrupt </li>
+ *   <li> Read the DATA </li>
+ * </ul>
+ *
+ * For more accurate information, please look at the PIO Parallel Capture Mode section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref pio_capture.c\n
+ * \ref pio_capture.h\n
+ */
+/*@{*/
+/*@}*/
+/**
+ * \file
+ *
+ * Implementation of PIO Parallel Capture.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *        Local Functions
+ *----------------------------------------------------------------------------*/
+/** Copy the API structure for interrupt handler */
+static SpioCaptureInit* _PioCaptureCopy;
+
+/*----------------------------------------------------------------------------
+ *        Global Functions
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief The PIO_CaptureHandler must be called by the PIO Capture Interrupt
+ * Service Routine with the corresponding PIO Capture instance.
+ */
+/*----------------------------------------------------------------------------*/
+extern void PIO_CaptureHandler( void )
+{
+    volatile uint32_t pio_captureSr;
+
+    /* Read the status register*/
+    pio_captureSr = PIOA->PIO_PCISR ;
+    pio_captureSr &= PIOA->PIO_PCIMR ;
+
+    if (pio_captureSr & PIO_PCISR_DRDY)
+    {
+        /* Parallel Capture Mode Data Ready */
+        if ( _PioCaptureCopy->CbkDataReady != NULL )
+        {
+            _PioCaptureCopy->CbkDataReady( _PioCaptureCopy );
+        }
+        else
+        {
+            TRACE_DEBUG("IT PIO Capture Data Ready received (no callback)\n\r");
+        }
+    }
+
+    if (pio_captureSr & PIO_PCISR_OVRE)
+    {
+        /* Parallel Capture Mode Overrun Error */
+        if ( _PioCaptureCopy->CbkOverrun != NULL )
+        {
+            _PioCaptureCopy->CbkOverrun( _PioCaptureCopy );
+        }
+        else
+        {
+            TRACE_DEBUG("IT PIO Capture Overrun Error received (no callback)\n\r");
+        }
+    }
+
+    if (pio_captureSr & PIO_PCISR_RXBUFF)
+    {
+        /* Reception Buffer Full */
+        if ( _PioCaptureCopy->CbkBuffFull != NULL )
+        {
+            _PioCaptureCopy->CbkBuffFull( _PioCaptureCopy );
+        }
+        else
+        {
+            TRACE_DEBUG("IT PIO Capture Reception Buffer Full received (no callback)\n\r");
+        }
+    }
+
+    if (pio_captureSr & PIO_PCISR_ENDRX)
+    {
+        /* End of Reception Transfer */
+        if ( _PioCaptureCopy->CbkEndReception != NULL )
+        {
+            _PioCaptureCopy->CbkEndReception( _PioCaptureCopy );
+        }
+        else
+        {
+            TRACE_DEBUG("IT PIO Capture End of Reception Transfer received (no callback)\n\r");
+        }
+    }
+}
+
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief Disable Interupt of the PIO Capture
+ * \param itToDisable : Interrupt to disable
+ */
+/*----------------------------------------------------------------------------*/
+void PIO_CaptureDisableIt( uint32_t itToDisable )
+{
+    /* Parallel capture mode is enabled */
+    PIOA->PIO_PCIDR = itToDisable;
+}
+
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief Enable Interupt of the PIO Capture
+ * \param itToEnable : Interrupt to enable
+ */
+/*----------------------------------------------------------------------------*/
+void PIO_CaptureEnableIt( uint32_t itToEnable )
+{
+    /* Parallel capture mode is enabled */
+    PIOA->PIO_PCIER = itToEnable;
+}
+
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief Enable the PIO Capture
+ */
+/*----------------------------------------------------------------------------*/
+void PIO_CaptureEnable( void )
+{
+    /* PDC: Receive Pointer Register */
+    PIOA->PIO_RPR = (uint32_t)_PioCaptureCopy->pData ;
+    /* PDC: Receive Counter Register */
+    /* Starts peripheral data transfer if corresponding channel is active */
+    PIOA->PIO_RCR = PIO_RCR_RXCTR(_PioCaptureCopy->dPDCsize) ;
+
+    /* Parallel capture mode is enabled */
+    PIOA->PIO_PCMR |= PIO_PCMR_PCEN ;
+}
+
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief Disable the PIO Capture
+ */
+/*----------------------------------------------------------------------------*/
+void PIO_CaptureDisable( void )
+{
+    /* Parallel capture mode is disabled */
+    PIOA->PIO_PCMR &= (uint32_t)(~PIO_PCMR_PCEN) ;
+}
+
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief Initialize the PIO Capture
+ * Be careful to configure the PDC before enable interrupt on pio capture.
+ * Otherway, the pdc will go in interrupt handler continuously.
+ * \param dsize :
+ *  0 = The reception data in the PIO_PCRHR register is a BYTE (8-bit).
+ *  1 = The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit).
+ * 2/3 = The reception data in the PIO_PCRHR register is a WORD (32-bit).
+ * \param alwaysSampling: ALWYS: Parallel Capture Mode Always Sampling
+ * 0 = The parallel capture mode samples the data when both data enables are active.
+ * 1 = The parallel capture mode samples the data whatever the data enables are.
+ * \param halfSampling: HALFS: Parallel Capture Mode Half Sampling
+ * 0 = The parallel capture mode samples all the data.
+ * 1 = The parallel capture mode samples the data only one time out of two.
+ * \param modeFirstSample: FRSTS: Parallel Capture Mode First Sample
+ * This bit is useful only if the HALFS bit is set to 1. If data are numbered
+ * in the order that they are received with an index from 0 to n:
+ * 0 = Only data with an even index are sampled.
+ * 1 = Only data with an odd index are sampled.
+ */
+/*----------------------------------------------------------------------------*/
+void PIO_CaptureInit( SpioCaptureInit *pInit )
+{
+    PMC_EnablePeripheral( ID_PIOA );
+
+    assert( (pInit->dsize < 0x4) ) ;
+    assert( (pInit->dPDCsize <= PIO_RPR_RXPTR_Msk) ) ;
+    assert( (pInit->alwaysSampling < 2)  );
+    assert( (pInit->halfSampling < 2) );
+    assert( (pInit->modeFirstSample < 2) );
+
+    /* PDC: Transfer Control Register */
+    /* Disables the PDC transmitter channel requests */
+    PIOA->PIO_PTCR = PIO_PTCR_RXTDIS;
+    /* PDC: Receive Pointer Register */
+    PIOA->PIO_RPR = (uint32_t)pInit->pData;
+    /* PDC: Receive Counter Register */
+    /* Starts peripheral data transfer if corresponding channel is active */
+    PIOA->PIO_RCR = PIO_RCR_RXCTR(pInit->dPDCsize);
+
+    /* PDC: Transfer Control Register */
+    /* Enables PDC receiver channel requests if RXTDIS is not set */
+    PIOA->PIO_PTCR = PIO_PTCR_RXTEN ;
+
+
+    /* Copy the API structure for interrupt handler */
+    _PioCaptureCopy = pInit;
+    /* PIO Parallel Capture Mode */
+    PIOA->PIO_PCMR =  PIO_PCMR_DSIZE(pInit->dsize)
+                    | ((pInit->alwaysSampling<<9) & PIO_PCMR_ALWYS)
+                    | ((pInit->halfSampling<<10) & PIO_PCMR_HALFS)
+                    | ((pInit->modeFirstSample<<11) & PIO_PCMR_FRSTS);
+
+    if ( pInit->CbkDataReady != NULL )
+    {
+        PIOA->PIO_PCIER = PIO_PCISR_DRDY;
+    }
+
+    if ( pInit->CbkOverrun != NULL )
+    {
+        PIOA->PIO_PCIER = PIO_PCISR_OVRE;
+    }
+
+    if ( pInit->CbkEndReception != NULL )
+    {
+        PIOA->PIO_PCIER = PIO_PCISR_ENDRX;
+    }
+
+    if ( pInit->CbkBuffFull != NULL )
+    {
+        PIOA->PIO_PCIER = PIO_PCISR_RXBUFF;
+    }
+//    else
+//    {
+//        TRACE_INFO("No interruption, no callback\n\r");
+//    }
+
+}
+

firmware/atmel_softpack_libraries/libchip_sam3s/source/pio_it.c

@@ -0,0 +1,315 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*
+ * \file
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *        Local definitions
+ *----------------------------------------------------------------------------*/
+
+/* Maximum number of interrupt sources that can be defined. This
+ * constant can be increased, but the current value is the smallest possible
+ * that will be compatible with all existing projects. */
+#define MAX_INTERRUPT_SOURCES       7
+
+/*----------------------------------------------------------------------------
+ *        Local types
+ *----------------------------------------------------------------------------*/
+
+/**
+ * Describes a PIO interrupt source, including the PIO instance triggering the
+ * interrupt and the associated interrupt handler.
+ */
+typedef struct _InterruptSource
+{
+    /* Pointer to the source pin instance. */
+    const Pin *pPin;
+
+    /* Interrupt handler. */
+    void (*handler)( const Pin* ) ;
+} InterruptSource ;
+
+/*----------------------------------------------------------------------------
+ *        Local variables
+ *----------------------------------------------------------------------------*/
+
+/* List of interrupt sources. */
+static InterruptSource _aIntSources[MAX_INTERRUPT_SOURCES] ;
+
+/* Number of currently defined interrupt sources. */
+static uint32_t _dwNumSources = 0;
+
+/*----------------------------------------------------------------------------
+ *        Local Functions
+ *----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief Stub, to handling all PIO Capture interrupts, if not defined.
+ */
+/*----------------------------------------------------------------------------*/
+//extern WEAK void PIO_CaptureHandler( void )
+//{
+//}
+
+/**
+ * \brief Handles all interrupts on the given PIO controller.
+ * \param id  PIO controller ID.
+ * \param pPio  PIO controller base address.
+ */
+extern void PioInterruptHandler( uint32_t id, Pio *pPio )
+{
+    uint32_t status;
+    uint32_t i;
+
+    /* Read PIO controller status */
+    status = pPio->PIO_ISR;
+    status &= pPio->PIO_IMR;
+
+    /* Check pending events */
+    if ( status != 0 )
+    {
+        TRACE_DEBUG( "PIO interrupt on PIO controller #%" PRIu32 "\n\r", id ) ;
+
+        /* Find triggering source */
+        i = 0;
+        while ( status != 0 )
+        {
+            /* There cannot be an unconfigured source enabled. */
+            assert(i < _dwNumSources);
+
+            /* Source is configured on the same controller */
+            if (_aIntSources[i].pPin->id == id)
+            {
+                /* Source has PIOs whose statuses have changed */
+                if ( (status & _aIntSources[i].pPin->mask) != 0 )
+                {
+                    TRACE_DEBUG( "Interrupt source #%" PRIu32 " triggered\n\r", i ) ;
+
+                    _aIntSources[i].handler(_aIntSources[i].pPin);
+                    status &= ~(_aIntSources[i].pPin->mask);
+                }
+            }
+            i++;
+        }
+    }
+}
+
+/*----------------------------------------------------------------------------
+ *        Global Functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Parallel IO Controller A interrupt handler
+ * \Redefined PIOA interrupt handler for NVIC interrupt table.
+ */
+extern void PIOA_IrqHandler( void )
+{
+    if ( PIOA->PIO_PCISR != 0 )
+    {
+        PIO_CaptureHandler() ;
+    }
+
+    PioInterruptHandler( ID_PIOA, PIOA ) ;
+}
+
+/**
+ * \brief Parallel IO Controller B interrupt handler
+ * \Redefined PIOB interrupt handler for NVIC interrupt table.
+ */
+extern void PIOB_IrqHandler( void )
+{
+    PioInterruptHandler( ID_PIOB, PIOB ) ;
+}
+
+/**
+ * \brief Parallel IO Controller C interrupt handler
+ * \Redefined PIOC interrupt handler for NVIC interrupt table.
+ */
+extern void PIOC_IrqHandler( void )
+{
+    PioInterruptHandler( ID_PIOC, PIOC ) ;
+}
+
+/**
+ * \brief Initializes the PIO interrupt management logic
+ *
+ * The desired priority of PIO interrupts must be provided.
+ * Calling this function multiple times result in the reset of currently
+ * configured interrupts.
+ *
+ * \param priority  PIO controller interrupts priority.
+ */
+extern void PIO_InitializeInterrupts( uint32_t dwPriority )
+{
+    TRACE_DEBUG( "PIO_Initialize()\n\r" ) ;
+
+    /* Reset sources */
+    _dwNumSources = 0 ;
+
+    /* Configure PIO interrupt sources */
+    TRACE_DEBUG( "PIO_Initialize: Configuring PIOA\n\r" ) ;
+    PMC_EnablePeripheral( ID_PIOA ) ;
+    PIOA->PIO_ISR ;
+    PIOA->PIO_IDR = 0xFFFFFFFF ;
+    NVIC_DisableIRQ( PIOA_IRQn ) ;
+    NVIC_ClearPendingIRQ( PIOA_IRQn ) ;
+    NVIC_SetPriority( PIOA_IRQn, dwPriority ) ;
+    NVIC_EnableIRQ( PIOA_IRQn ) ;
+
+    TRACE_DEBUG( "PIO_Initialize: Configuring PIOB\n\r" ) ;
+    PMC_EnablePeripheral( ID_PIOB ) ;
+    PIOB->PIO_ISR ;
+    PIOB->PIO_IDR = 0xFFFFFFFF ;
+    NVIC_DisableIRQ( PIOB_IRQn ) ;
+    NVIC_ClearPendingIRQ( PIOB_IRQn ) ;
+    NVIC_SetPriority( PIOB_IRQn, dwPriority ) ;
+    NVIC_EnableIRQ( PIOB_IRQn ) ;
+
+    TRACE_DEBUG( "PIO_Initialize: Configuring PIOC\n\r" ) ;
+    PMC_EnablePeripheral( ID_PIOC ) ;
+    PIOC->PIO_ISR ;
+    PIOC->PIO_IDR = 0xFFFFFFFF ;
+    NVIC_DisableIRQ( PIOC_IRQn ) ;
+    NVIC_ClearPendingIRQ( PIOC_IRQn ) ;
+    NVIC_SetPriority( PIOC_IRQn, dwPriority ) ;
+    NVIC_EnableIRQ( PIOC_IRQn ) ;
+}
+
+/**
+ * Configures a PIO or a group of PIO to generate an interrupt on status
+ * change. The provided interrupt handler will be called with the triggering
+ * pin as its parameter (enabling different pin instances to share the same
+ * handler).
+ * \param pPin  Pointer to a Pin instance.
+ * \param handler  Interrupt handler function pointer.
+ */
+extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) )
+{
+    Pio* pio ;
+    InterruptSource* pSource ;
+
+    TRACE_DEBUG( "PIO_ConfigureIt()\n\r" ) ;
+
+    assert( pPin ) ;
+    pio = pPin->pio ;
+    assert( _dwNumSources < MAX_INTERRUPT_SOURCES ) ;
+
+    /* Define new source */
+    TRACE_DEBUG( "PIO_ConfigureIt: Defining new source #%" PRIu32 ".\n\r",  _dwNumSources ) ;
+
+    pSource = &(_aIntSources[_dwNumSources]) ;
+    pSource->pPin = pPin ;
+    pSource->handler = handler ;
+    _dwNumSources++ ;
+
+    /* PIO3 with additional interrupt support
+     * Configure additional interrupt mode registers */
+    if ( pPin->attribute & PIO_IT_AIME )
+    {
+        // enable additional interrupt mode
+        pio->PIO_AIMER       = pPin->mask ;
+
+        // if bit field of selected pin is 1, set as Rising Edge/High level detection event
+        if ( pPin->attribute & PIO_IT_RE_OR_HL )
+        {
+            pio->PIO_REHLSR    = pPin->mask ;
+        }
+        else
+        {
+            pio->PIO_FELLSR     = pPin->mask;
+        }
+
+        /* if bit field of selected pin is 1, set as edge detection source */
+        if (pPin->attribute & PIO_IT_EDGE)
+            pio->PIO_ESR     = pPin->mask;
+        else
+            pio->PIO_LSR     = pPin->mask;
+    }
+    else
+    {
+        /* disable additional interrupt mode */
+        pio->PIO_AIMDR       = pPin->mask;
+    }
+}
+
+/**
+ * Enables the given interrupt source if it has been configured. The status
+ * register of the corresponding PIO controller is cleared prior to enabling
+ * the interrupt.
+ * \param pPin  Interrupt source to enable.
+ */
+extern void PIO_EnableIt( const Pin *pPin )
+{
+    TRACE_DEBUG( "PIO_EnableIt()\n\r" ) ;
+
+    assert( pPin != NULL ) ;
+
+#ifndef NOASSERT
+    uint32_t i = 0;
+    uint32_t dwFound = 0;
+
+    while ( (i < _dwNumSources) && !dwFound )
+    {
+        if ( _aIntSources[i].pPin == pPin )
+        {
+            dwFound = 1 ;
+        }
+        i++ ;
+    }
+    assert( dwFound != 0 ) ;
+#endif
+
+    pPin->pio->PIO_ISR;
+    pPin->pio->PIO_IER = pPin->mask ;
+}
+
+/**
+ * Disables a given interrupt source, with no added side effects.
+ *
+ * \param pPin  Interrupt source to disable.
+ */
+extern void PIO_DisableIt( const Pin *pPin )
+{
+    assert( pPin != NULL ) ;
+
+    TRACE_DEBUG( "PIO_DisableIt()\n\r" ) ;
+
+    pPin->pio->PIO_IDR = pPin->mask;
+}
+

firmware/atmel_softpack_libraries/libchip_sam3s/source/pmc.c

@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+#include "trace.h"
+
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *        Local definitions
+ *----------------------------------------------------------------------------*/
+
+#define MASK_STATUS0 0xFFFFFFFC
+#define MASK_STATUS1 0xFFFFFFFF
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Enables the clock of a peripheral. The peripheral ID is used
+ * to identify which peripheral is targetted.
+ *
+ * \note The ID must NOT be shifted (i.e. 1 << ID_xxx).
+ *
+ * \param id  Peripheral ID (ID_xxx).
+ */
+extern void PMC_EnablePeripheral( uint32_t dwId )
+{
+    assert( dwId < 35 ) ;
+
+    if ( dwId < 32 )
+    {
+        if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) )
+        {
+            TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral"  " %" PRIu32 " is already enabled\n\r", dwId ) ;
+        }
+        else
+        {
+            PMC->PMC_PCER0 = 1 << dwId ;
+        }
+    }
+    else
+    {
+        dwId -= 32;
+        if ((PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId))
+        {
+            TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral"  " %" PRIu32 " is already enabled\n\r", dwId + 32 ) ;
+        }
+        else
+        {
+            PMC->PMC_PCER1 = 1 << dwId ;
+        }
+    }
+}
+
+/**
+ * \brief Disables the clock of a peripheral. The peripheral ID is used
+ * to identify which peripheral is targetted.
+ *
+ * \note The ID must NOT be shifted (i.e. 1 << ID_xxx).
+ *
+ * \param id  Peripheral ID (ID_xxx).
+ */
+extern void PMC_DisablePeripheral( uint32_t dwId )
+{
+    assert( dwId < 35 ) ;
+
+    if ( dwId < 32 )
+    {
+        if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) )
+        {
+            TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %" PRIu32 " is not enabled\n\r", dwId ) ;
+        }
+        else
+        {
+            PMC->PMC_PCDR0 = 1 << dwId ;
+        }
+    }
+    else
+    {
+        dwId -= 32 ;
+        if ( (PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) )
+        {
+            TRACE_DEBUG( "PMC_DisablePeripheral: clock of peripheral" " %" PRIu32 " is not enabled\n\r", dwId + 32 ) ;
+        }
+        else
+        {
+            PMC->PMC_PCDR1 = 1 << dwId ;
+        }
+    }
+}
+
+/**
+ * \brief Enable all the periph clock via PMC.
+ */
+extern void PMC_EnableAllPeripherals( void )
+{
+    PMC->PMC_PCER0 = MASK_STATUS0 ;
+    while ( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0 ) ;
+
+    PMC->PMC_PCER1 = MASK_STATUS1 ;
+    while ( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1 ) ;
+
+    TRACE_DEBUG( "Enable all periph clocks\n\r" ) ;
+}
+
+/**
+ * \brief Disable all the periph clock via PMC.
+ */
+extern void PMC_DisableAllPeripherals( void )
+{
+    PMC->PMC_PCDR0 = MASK_STATUS0 ;
+    while ( (PMC->PMC_PCSR0 & MASK_STATUS0) != 0 ) ;
+
+    PMC->PMC_PCDR1 = MASK_STATUS1 ;
+    while ( (PMC->PMC_PCSR1 & MASK_STATUS1) != 0 ) ;
+
+    TRACE_DEBUG( "Disable all periph clocks\n\r" ) ;
+}
+
+/**
+ * \brief Get Periph Status for the given peripheral ID.
+ *
+ * \param id  Peripheral ID (ID_xxx).
+ */
+extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId )
+{
+    assert( dwId < 35 ) ;
+
+    if ( dwId < 32 )
+    {
+        return ( PMC->PMC_PCSR0 & (1 << dwId) ) ;
+    }
+    else {
+        return ( PMC->PMC_PCSR1 & (1 << (dwId - 32)) ) ;
+    }
+}

firmware/atmel_softpack_libraries/libchip_sam3s/source/spi.c

@@ -0,0 +1,352 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup spi_module Working with SPI
+ * The SPI driver provides the interface to configure and use the SPI
+ * peripheral.
+ *
+ * The Serial Peripheral Interface (SPI) circuit is a synchronous serial
+ * data link that provides communication with external devices in Master
+ * or Slave Mode.
+ *
+ * To use the SPI, the user has to follow these few steps:
+ * -# Enable the SPI pins required by the application (see pio.h).
+ * -# Configure the SPI using the \ref SPI_Configure(). This enables the
+ *    peripheral clock. The mode register is loaded with the given value.
+ * -# Configure all the necessary chip selects with \ref SPI_ConfigureNPCS().
+ * -# Enable the SPI by calling \ref SPI_Enable().
+ * -# Send/receive data using \ref SPI_Write() and \ref SPI_Read(). Note that \ref SPI_Read()
+ *    must be called after \ref SPI_Write() to retrieve the last value read.
+ * -# Send/receive data using the PDC with the \ref SPI_WriteBuffer() and
+ *    \ref SPI_ReadBuffer() functions.
+ * -# Disable the SPI by calling \ref SPI_Disable().
+ *
+ * For more accurate information, please look at the SPI section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref spi.c\n
+ * \ref spi.h.\n
+*/
+/*@{*/
+/*@}*/
+
+/**
+ * \file
+ *
+ * Implementation of Serial Peripheral Interface (SPI) controller.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+#include "pmc.h"
+#include "spi.h"
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Enables a SPI peripheral.
+ *
+ * \param spi  Pointer to an Spi instance.
+ */
+extern void SPI_Enable( Spi* spi )
+{
+    spi->SPI_CR = SPI_CR_SPIEN ;
+}
+
+/**
+ * \brief Disables a SPI peripheral.
+ *
+ * \param spi  Pointer to an Spi instance.
+ */
+extern void SPI_Disable( Spi* spi )
+{
+    spi->SPI_CR = SPI_CR_SPIDIS ;
+}
+
+/**
+ * \brief Enables one or more interrupt sources of a SPI peripheral.
+ *
+ * \param spi  Pointer to an Spi instance.
+ * \param sources Bitwise OR of selected interrupt sources.
+ */
+extern void SPI_EnableIt( Spi* spi, uint32_t dwSources )
+{
+    spi->SPI_IER = dwSources ;
+}
+
+/**
+ * \brief Disables one or more interrupt sources of a SPI peripheral.
+ *
+ * \param spi  Pointer to an Spi instance.
+ * \param sources Bitwise OR of selected interrupt sources.
+ */
+extern void SPI_DisableIt( Spi* spi, uint32_t dwSources )
+{
+    spi->SPI_IDR = dwSources ;
+}
+
+/**
+ * \brief Configures a SPI peripheral as specified. The configuration can be computed
+ * using several macros (see \ref spi_configuration_macros).
+ *
+ * \param spi  Pointer to an Spi instance.
+ * \param id   Peripheral ID of the SPI.
+ * \param configuration  Value of the SPI configuration register.
+ */
+extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration )
+{
+    PMC_EnablePeripheral( dwId ) ;
+    spi->SPI_CR = SPI_CR_SPIDIS ;
+
+    /* Execute a software reset of the SPI twice */
+    spi->SPI_CR = SPI_CR_SWRST ;
+    spi->SPI_CR = SPI_CR_SWRST ;
+    spi->SPI_MR = dwConfiguration ;
+}
+
+
+/**
+ * \brief Configures a chip select of a SPI peripheral. The chip select configuration
+ * is computed using several macros (see \ref spi_configuration_macros).
+ *
+ * \param spi   Pointer to an Spi instance.
+ * \param npcs  Chip select to configure (0, 1, 2 or 3).
+ * \param configuration  Desired chip select configuration.
+ */
+void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration )
+{
+    spi->SPI_CSR[dwNpcs] = dwConfiguration ;
+}
+
+/**
+ * \brief Get the current status register of the given SPI peripheral.
+ * \note This resets the internal value of the status register, so further
+ * read may yield different values.
+ * \param spi   Pointer to a Spi instance.
+ * \return  SPI status register.
+ */
+extern uint32_t SPI_GetStatus( Spi* spi )
+{
+    return spi->SPI_SR ;
+}
+
+/**
+ * \brief Reads and returns the last word of data received by a SPI peripheral. This
+ * method must be called after a successful SPI_Write call.
+ *
+ * \param spi  Pointer to an Spi instance.
+ *
+ * \return readed data.
+ */
+extern uint32_t SPI_Read( Spi* spi )
+{
+    while ( (spi->SPI_SR & SPI_SR_RDRF) == 0 ) ;
+
+    return spi->SPI_RDR & 0xFFFF ;
+}
+
+/**
+ * \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed
+ * peripheral select, the npcs value is meaningless. Otherwise, it identifies
+ * the component which shall be addressed.
+ *
+ * \param spi   Pointer to an Spi instance.
+ * \param npcs  Chip select of the component to address (0, 1, 2 or 3).
+ * \param data  Word of data to send.
+ */
+extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData )
+{
+    /* Send data */
+    while ( (spi->SPI_SR & SPI_SR_TXEMPTY) == 0 ) ;
+    spi->SPI_TDR = wData | SPI_PCS( dwNpcs ) ;
+    while ( (spi->SPI_SR & SPI_SR_TDRE) == 0 ) ;
+}
+
+/**
+ * \brief Check if SPI transfer finish.
+ *
+ * \param spi  Pointer to an Spi instance.
+ *
+ * \return Returns 1 if there is no pending write operation on the SPI; otherwise
+ * returns 0.
+ */
+extern uint32_t SPI_IsFinished( Spi* spi )
+{
+    return ((spi->SPI_SR & SPI_SR_TXEMPTY) != 0) ;
+}
+
+/**
+ * \brief Enable Spi PDC transmit
+ * \param spi  Pointer to an Spi instance.
+*/
+extern void SPI_PdcEnableTx( Spi* spi )
+{
+    spi->SPI_PTCR = SPI_PTCR_TXTEN ;
+}
+
+/**
+ * \brief Disable Spi PDC transmit
+ * \param spi  Pointer to an Spi instance.
+*/
+extern void SPI_PdcDisableTx( Spi* spi )
+{
+    spi->SPI_PTCR = SPI_PTCR_TXTDIS ;
+}
+
+/**
+ * \brief Enable Spi PDC receive
+ * \param spi  Pointer to an Spi instance.
+*/
+extern void SPI_PdcEnableRx( Spi* spi )
+{
+    spi->SPI_PTCR = SPI_PTCR_RXTEN ;
+}
+
+/**
+ * \brief Disable Spi PDC receive
+ * \param spi  Pointer to an Spi instance.
+*/
+extern void SPI_PdcDisableRx( Spi* spi )
+{
+    spi->SPI_PTCR = SPI_PTCR_RXTDIS ;
+}
+
+/**
+ * \brief Set PDC transmit and next transmit buffer address and size.
+ *
+ * \param spi    Pointer to an Spi instance.
+ * \param txBuf  PDC transmit buffer address.
+ * \param txCount  Length in bytes of the transmit buffer.
+ * \param txNextBuf  PDC next transmit buffer address.
+ * \param txNextCount  Length in bytes of the next transmit buffer.
+ */
+extern void SPI_PdcSetTx( Spi* spi, void* pvTxBuf, uint32_t dwTxCount, void* pvTxNextBuf, uint32_t dwTxNextCount )
+{
+    spi->SPI_TPR = (uint32_t)pvTxBuf ;
+    spi->SPI_TCR = dwTxCount ;
+    spi->SPI_TNPR = (uint32_t)pvTxNextBuf ;
+    spi->SPI_TNCR = dwTxNextCount ;
+}
+
+/**
+ * \brief Set PDC receive and next receive buffer address and size.
+ *
+ * \param spi    Pointer to an Spi instance.
+ * \param rxBuf  PDC receive buffer address.
+ * \param rxCount  Length in bytes of the receive buffer.
+ * \param rxNextBuf  PDC next receive buffer address.
+ * \param rxNextCount  Length in bytes of the next receive buffer.
+ */
+extern void SPI_PdcSetRx( Spi* spi, void* pvRxBuf, uint32_t dwRxCount, void* pvRxNextBuf, uint32_t dwRxNextCount )
+{
+    spi->SPI_RPR = (uint32_t)pvRxBuf ;
+    spi->SPI_RCR = dwRxCount ;
+    spi->SPI_RNPR = (uint32_t)pvRxNextBuf ;
+    spi->SPI_RNCR = dwRxNextCount ;
+}
+
+/**
+ * \brief Sends the contents of buffer through a SPI peripheral, using the PDC to
+ * take care of the transfer.
+ *
+ * \param spi     Pointer to an Spi instance.
+ * \param buffer  Data buffer to send.
+ * \param length  Length of the data buffer.
+ */
+extern uint32_t SPI_WriteBuffer( Spi* spi, void* pvBuffer, uint32_t dwLength )
+{
+    /* Check if first bank is free */
+    if ( spi->SPI_TCR == 0 )
+    {
+        spi->SPI_TPR = (uint32_t)pvBuffer ;
+        spi->SPI_TCR = dwLength ;
+        spi->SPI_PTCR = PERIPH_PTCR_TXTEN ;
+
+        return 1 ;
+    }
+    /* Check if second bank is free */
+    else
+    {
+        if ( spi->SPI_TNCR == 0 )
+        {
+            spi->SPI_TNPR = (uint32_t)pvBuffer ;
+            spi->SPI_TNCR = dwLength ;
+
+            return 1 ;
+        }
+    }
+
+    /* No free banks */
+    return 0 ;
+}
+
+/**
+ * \brief Reads data from a SPI peripheral until the provided buffer is filled. This
+ * method does NOT need to be called after SPI_Write or SPI_WriteBuffer.
+ *
+ * \param spi     Pointer to an Spi instance.
+ * \param buffer  Data buffer to store incoming bytes.
+ * \param length  Length in bytes of the data buffer.
+ */
+extern uint32_t SPI_ReadBuffer( Spi* spi, void *pvBuffer, uint32_t dwLength )
+{
+    /* Check if the first bank is free */
+    if ( spi->SPI_RCR == 0 )
+    {
+        spi->SPI_RPR = (uint32_t)pvBuffer ;
+        spi->SPI_RCR = dwLength ;
+        spi->SPI_PTCR = PERIPH_PTCR_RXTEN ;
+
+        return 1 ;
+    }
+    /* Check if second bank is free */
+    else
+    {
+        if ( spi->SPI_RNCR == 0 )
+        {
+            spi->SPI_RNPR = (uint32_t)pvBuffer ;
+            spi->SPI_RNCR = dwLength ;
+            return 1 ;
+        }
+    }
+
+    /* No free bank */
+    return 0 ;
+}
+
+

firmware/atmel_softpack_libraries/libchip_sam3s/source/tc.c

@@ -0,0 +1,175 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Implementation of Timer Counter (TC).
+ *
+ */
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <assert.h>
+
+/*------------------------------------------------------------------------------
+ *         Global functions
+ *------------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures a Timer Counter Channel
+ *
+ * Configures a Timer Counter to operate in the given mode. Timer is stopped
+ * after configuration and must be restarted with TC_Start(). All the
+ * interrupts of the timer are also disabled.
+ *
+ * \param pTc  Pointer to a Tc instance.
+ * \param channel Channel number.
+ * \param mode  Operating mode (TC_CMR value).
+ */
+extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode )
+{
+    TcChannel* pTcCh ;
+
+    assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;
+    pTcCh = pTc->TC_CHANNEL+dwChannel ;
+
+    /*  Disable TC clock */
+    pTcCh->TC_CCR = TC_CCR_CLKDIS ;
+
+    /*  Disable interrupts */
+    pTcCh->TC_IDR = 0xFFFFFFFF ;
+
+    /*  Clear status register */
+    pTcCh->TC_SR ;
+
+    /*  Set mode */
+    pTcCh->TC_CMR = dwMode ;
+}
+
+/**
+ * \brief Reset and Start the TC Channel
+ *
+ * Enables the timer clock and performs a software reset to start the counting.
+ *
+ * \param pTc  Pointer to a Tc instance.
+ * \param dwChannel Channel number.
+ */
+extern void TC_Start( Tc *pTc, uint32_t dwChannel )
+{
+    TcChannel* pTcCh ;
+
+    assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;
+
+    pTcCh = pTc->TC_CHANNEL+dwChannel ;
+    pTcCh->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG ;
+}
+
+/**
+ * \brief Stop TC Channel
+ *
+ * Disables the timer clock, stopping the counting.
+ *
+ * \param pTc     Pointer to a Tc instance.
+ * \param dwChannel Channel number.
+ */
+extern void TC_Stop(Tc *pTc, uint32_t dwChannel )
+{
+    TcChannel* pTcCh ;
+
+    assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;
+
+    pTcCh = pTc->TC_CHANNEL+dwChannel ;
+    pTcCh->TC_CCR = TC_CCR_CLKDIS ;
+}
+
+/**
+ * \brief Find best MCK divisor
+ *
+ * Finds the best MCK divisor given the timer frequency and MCK. The result
+ * is guaranteed to satisfy the following equation:
+ * \code
+ *   (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)
+ * \endcode
+ * with DIV being the highest possible value.
+ *
+ * \param dwFreq  Desired timer frequency.
+ * \param dwMCk  Master clock frequency.
+ * \param dwDiv  Divisor value.
+ * \param dwTcClks  TCCLKS field value for divisor.
+ * \param dwBoardMCK  Board clock frequency.
+ *
+ * \return 1 if a proper divisor has been found, otherwise 0.
+ */
+extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK )
+{
+    const uint32_t adwDivisors[5] = { 2, 8, 32, 128, dwBoardMCK / 32768 } ;
+
+    uint32_t dwIndex = 0 ;
+
+    /*  Satisfy lower bound */
+    while ( dwFreq < ((dwMCk / adwDivisors[dwIndex]) / 65536) )
+    {
+        dwIndex++ ;
+
+        /*  If no divisor can be found, return 0 */
+        if ( dwIndex == (sizeof( adwDivisors )/sizeof( adwDivisors[0] ))  )
+        {
+            return 0 ;
+        }
+    }
+
+    /*  Try to maximize DIV while satisfying upper bound */
+    while ( dwIndex < 4 )
+    {
+
+        if ( dwFreq > (dwMCk / adwDivisors[dwIndex + 1]) )
+        {
+            break ;
+        }
+        dwIndex++ ;
+    }
+
+    /*  Store results */
+    if ( dwDiv )
+    {
+        *dwDiv = adwDivisors[dwIndex] ;
+    }
+    if ( dwTcClks )
+    {
+        *dwTcClks = dwIndex ;
+    }
+
+    return 1 ;
+}
+

firmware/atmel_softpack_libraries/libchip_sam3s/source/unique_id.c

@@ -0,0 +1,43 @@
+#include "chip.h"
+
+#define EFC_FCMD_STUI	0x0E
+#define EFC_FCMD_SPUI	0x0F
+
+__attribute__ ((section(".ramfunc")))
+void EEFC_ReadUniqueID(unsigned int *pdwUniqueID)
+{
+	unsigned int status;
+
+	/* Errata / Workaround: Set bit 16 of EEFC Flash Mode Register
+	 * to 1 */
+	EFC->EEFC_FMR |= (1 << 16);
+
+	/* Send the Start Read unique Identifier command (STUI) by
+	 * writing the Flash Command Register with the STUI command. */
+	EFC->EEFC_FCR = (0x5A << 24) | EFC_FCMD_STUI;
+
+	/* Wait for the FRDY bit to fall */
+	do {
+		status = EFC->EEFC_FSR;
+	} while ((status & EEFC_FSR_FRDY) == EEFC_FSR_FRDY);
+
+	/* The Unique Identifier is located in the first 128 bits of the
+	 * Flash memory mapping. So, at the address 0x400000-0x400003.
+	 * */
+	pdwUniqueID[0] = *(uint32_t *) IFLASH_ADDR;
+	pdwUniqueID[1] = *(uint32_t *) (IFLASH_ADDR + 4);
+	pdwUniqueID[2] = *(uint32_t *) (IFLASH_ADDR + 8);
+	pdwUniqueID[3] = *(uint32_t *) (IFLASH_ADDR + 12);
+
+	/* To stop the Unique Identifier mode, the user needs to send
+	 * the Stop Read unique Identifier command (SPUI) by writing the
+	 * Flash Command Register with the SPUI command. */
+	EFC->EEFC_FCR = (0x5A << 24) | EFC_FCMD_SPUI;
+
+	/* When the Stop read Unique Unique Identifier command (SPUI)
+	 * has been performed, the FRDY bit in the Flash Programming
+	 * Status Register (EEFC_FSR) rises. */
+	do {
+		status = EFC->EEFC_FSR;
+	} while ((status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY);
+}

firmware/atmel_softpack_libraries/libchip_sam3s/source/usart.c

@@ -0,0 +1,410 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup usart_module Working with USART
+ * The USART driver provides the interface to configure and use the USART peripheral.\n
+ *
+ * The USART supports several kinds of comminication modes such as full-duplex asynchronous/
+ * synchronous serial commnunication,RS485 with driver control signal,ISO7816,SPI and Test modes.
+ *
+ * To start a USART transfer with \ref AT91SAM3S_PDC "PDC" support, the user could follow these steps:
+ * <ul>
+ * <li> Configure USART with expected mode and baudrate(see \ref USART_Configure), which could be done by:
+ * -# Resetting and disabling transmitter and receiver by setting US_CR(Control Register). </li>
+ * -# Conifguring the USART in a specific mode by setting USART_MODE bits in US_MR(Mode Register) </li>
+ * -# Setting baudrate which is different from mode to mode.
+   </li>
+ * <li> Enable transmitter or receiver respectively by set US_CR_TXEN or US_CR_RXEN in US_CR.</li>
+ * <li> Read from or write to the peripheral with  \ref USART_ReadBuffer or \ref USART_WriteBuffer.
+        These operations could be done by polling or interruption. </li>
+ * <li> For polling, check the status bit US_CSR_ENDRX/US_CSR_RXBUFF (READ) or US_CSR_ENDTX/
+        US_CSR_TXBUFE (WRITE).  </li>
+ * <li> For interruption,"enable" the status bit through US_IER and
+        realize the hanler with USARTx_IrqHandler according to IRQ vector
+        table which is defined in board_cstartup_<toolchain>.c
+        To enable the interruption of USART,it should be configured with priority and enabled first through
+        NVIC .</li>
+ * </ul>
+ *
+ * For more accurate information, please look at the USART section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref usart.c\n
+ * \ref usart.h\n
+*/
+
+
+
+/**
+ * \file
+ *
+ * Implementation of USART (Universal Synchronous Asynchronous Receiver Transmitter)
+ * controller.
+ *
+ */
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+#include "chip.h"
+#include "trace.h"
+
+#include <assert.h>
+#include <string.h>
+
+/*----------------------------------------------------------------------------
+ *        Local definitions
+ *----------------------------------------------------------------------------*/
+
+
+/*------------------------------------------------------------------------------
+ *         Exported functions
+ *------------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures an USART peripheral with the specified parameters.
+ *
+ *
+ *  \param usart  Pointer to the USART peripheral to configure.
+ *  \param mode  Desired value for the USART mode register (see the datasheet).
+ *  \param baudrate  Baudrate at which the USART should operate (in Hz).
+ *  \param masterClock  Frequency of the system master clock (in Hz).
+ */
+void USART_Configure(Usart *usart,
+                            uint32_t mode,
+                            uint32_t baudrate,
+                            uint32_t masterClock)
+{
+    /* Reset and disable receiver & transmitter*/
+    usart->US_CR = US_CR_RSTRX | US_CR_RSTTX
+                   | US_CR_RXDIS | US_CR_TXDIS;
+
+    /* Configure mode*/
+    usart->US_MR = mode;
+
+    /* Configure baudrate*/
+    /* Asynchronous, no oversampling*/
+    if ( ((mode & US_MR_SYNC) == 0) && ((mode & US_MR_OVER) == 0) )
+    {
+        usart->US_BRGR = (masterClock / baudrate) / 16;
+    }
+
+    if( ((mode & US_MR_USART_MODE_SPI_MASTER) == US_MR_USART_MODE_SPI_MASTER)
+     || ((mode & US_MR_SYNC) == US_MR_SYNC))
+    {
+        if( (mode & US_MR_USCLKS_Msk) == US_MR_USCLKS_MCK)
+        {
+            usart->US_BRGR = masterClock / baudrate;
+        }
+        else
+        {
+            if ( (mode & US_MR_USCLKS_DIV) == US_MR_USCLKS_DIV)
+            {
+                usart->US_BRGR = masterClock / baudrate / 8;
+            }
+        }
+    }
+    /* TODO other modes*/
+}
+/**
+ * \brief Enables or disables the transmitter of an USART peripheral.
+ *
+ *
+ * \param usart  Pointer to an USART peripheral
+ * \param enabled  If true, the transmitter is enabled; otherwise it is
+ *                disabled.
+ */
+void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled)
+{
+    if (enabled) {
+
+        usart->US_CR = US_CR_TXEN;
+    }
+    else {
+
+        usart->US_CR = US_CR_TXDIS;
+    }
+}
+
+/**
+ * \brief Enables or disables the receiver of an USART peripheral
+ *
+ *
+ * \param usart  Pointer to an USART peripheral
+ * \param enabled  If true, the receiver is enabled; otherwise it is disabled.
+ */
+void USART_SetReceiverEnabled(Usart *usart,
+                                     uint8_t enabled)
+{
+    if (enabled) {
+
+        usart->US_CR = US_CR_RXEN;
+    }
+    else {
+
+        usart->US_CR = US_CR_RXDIS;
+    }
+}
+
+/**
+ * \brief Sends one packet of data through the specified USART peripheral. This
+ * function operates synchronously, so it only returns when the data has been
+ * actually sent.
+ *
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param data  Data to send including 9nth bit and sync field if necessary (in
+ *        the same format as the US_THR register in the datasheet).
+ * \param timeOut  Time out value (0 = no timeout).
+ */
+void USART_Write(
+    Usart *usart,
+    uint16_t data,
+    volatile uint32_t timeOut)
+{
+    if (timeOut == 0) {
+
+        while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
+    }
+    else {
+
+        while ((usart->US_CSR & US_CSR_TXEMPTY) == 0) {
+
+            if (timeOut == 0) {
+
+                TRACE_ERROR("USART_Write: Timed out.\n\r");
+                return;
+            }
+            timeOut--;
+        }
+    }
+
+    usart->US_THR = data;
+}
+
+/**
+ * \brief Sends the contents of a data buffer through the specified USART peripheral.
+ * This function returns immediately (1 if the buffer has been queued, 0
+ * otherwise); poll the ENDTX and TXBUFE bits of the USART status register
+ * to check for the transfer completion.
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param buffer  Pointer to the data buffer to send.
+ * \param size  Size of the data buffer (in bytes).
+ */
+uint8_t USART_WriteBuffer(
+    Usart *usart,
+    void *buffer,
+    uint32_t size)
+{
+    /* Check if the first PDC bank is free*/
+    if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) {
+
+        usart->US_TPR = (uint32_t) buffer;
+        usart->US_TCR = size;
+        usart->US_PTCR = US_PTCR_TXTEN;
+
+        return 1;
+    }
+    /* Check if the second PDC bank is free*/
+    else if (usart->US_TNCR == 0) {
+
+        usart->US_TNPR = (uint32_t) buffer;
+        usart->US_TNCR = size;
+
+        return 1;
+    }
+    else {
+
+        return 0;
+    }
+}
+
+
+/**
+ * \brief  Reads and return a packet of data on the specified USART peripheral. This
+ * function operates asynchronously, so it waits until some data has been
+ * received.
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param timeOut  Time out value (0 -> no timeout).
+ */
+uint16_t USART_Read(
+    Usart *usart,
+    volatile uint32_t timeOut)
+{
+    if (timeOut == 0) {
+
+        while ((usart->US_CSR & US_CSR_RXRDY) == 0);
+    }
+    else {
+
+        while ((usart->US_CSR & US_CSR_RXRDY) == 0) {
+
+            if (timeOut == 0) {
+
+                TRACE_ERROR( "USART_Read: Timed out.\n\r" ) ;
+                return 0;
+            }
+            timeOut--;
+        }
+    }
+
+    return usart->US_RHR;
+}
+
+/**
+ * \brief  Reads data from an USART peripheral, filling the provided buffer until it
+ * becomes full. This function returns immediately with 1 if the buffer has
+ * been queued for transmission; otherwise 0.
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param buffer  Pointer to the buffer where the received data will be stored.
+ * \param size  Size of the data buffer (in bytes).
+ */
+uint8_t USART_ReadBuffer(Usart *usart,
+                                      void *buffer,
+                                      uint32_t size)
+{
+    /* Check if the first PDC bank is free*/
+    if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) {
+
+        usart->US_RPR = (uint32_t) buffer;
+        usart->US_RCR = size;
+        usart->US_PTCR = US_PTCR_RXTEN;
+
+        return 1;
+    }
+    /* Check if the second PDC bank is free*/
+    else if (usart->US_RNCR == 0) {
+
+        usart->US_RNPR = (uint32_t) buffer;
+        usart->US_RNCR = size;
+
+        return 1;
+    }
+    else {
+
+        return 0;
+    }
+}
+
+/**
+ * \brief  Returns 1 if some data has been received and can be read from an USART;
+ * otherwise returns 0.
+ *
+ * \param usart  Pointer to an Usart instance.
+ */
+uint8_t USART_IsDataAvailable(Usart *usart)
+{
+    if ((usart->US_CSR & US_CSR_RXRDY) != 0) {
+
+        return 1;
+    }
+    else {
+
+        return 0;
+    }
+}
+
+/**
+ * \brief  Sets the filter value for the IRDA demodulator.
+ *
+ * \param pUsart  Pointer to an Usart instance.
+ * \param filter  Filter value.
+ */
+void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter)
+{
+    assert( pUsart != NULL ) ;
+
+    pUsart->US_IF = filter;
+}
+
+/**
+ * \brief  Sends one packet of data through the specified USART peripheral. This
+ * function operates synchronously, so it only returns when the data has been
+ * actually sent.
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param c  Character to send
+ */
+void USART_PutChar(
+    Usart *usart,
+    uint8_t c)
+{
+    /* Wait for the transmitter to be ready*/
+    while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
+
+    /* Send character*/
+    usart->US_THR = c;
+
+    /* Wait for the transfer to complete*/
+    while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
+}
+
+/**
+ * \brief   Return 1 if a character can be read in USART
+ */
+uint32_t USART_IsRxReady(Usart *usart)
+{
+    return (usart->US_CSR & US_CSR_RXRDY);
+}
+/**
+ * \brief   Get present status
+ */
+uint32_t USART_GetStatus(Usart *usart)
+{
+    return usart->US_CSR;
+}
+/**
+ * \brief   Enable interrupt
+ */
+void USART_EnableIt(Usart *usart,uint32_t mode)
+{
+    usart->US_IER = mode;
+}
+/**
+ * \brief   Disable interrupt
+ */
+void USART_DisableIt(Usart *usart,uint32_t mode)
+{
+    usart->US_IDR = mode;
+}
+/**
+ * \brief  Reads and returns a character from the USART.
+ *
+ * \note This function is synchronous (i.e. uses polling).
+ * \param usart  Pointer to an USART peripheral.
+ * \return Character received.
+ */
+uint8_t USART_GetChar(Usart *usart)
+{
+    while ((usart->US_CSR & US_CSR_RXRDY) == 0);
+    return usart->US_RHR;
+}

firmware/atmel_softpack_libraries/libchip_sam3s/source/wdt.c

@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Implementation of Watchdog Timer (WDT) controller.
+ *
+ */
+
+/** \addtogroup wdt_module Working with WDT
+ * The WDT driver provides the interface to configure and use the WDT
+ * peripheral.
+ *
+ * The WDT can be used to prevent system lock-up if the software becomes
+ * trapped in a deadlock. It can generate a general reset or a processor
+ * reset only. It is clocked by slow clock divided by 128.
+ *
+ * The WDT is running at reset with 16 seconds watchdog period (slow clock at 32.768 kHz)
+ * and external reset generation enabled. The user must either disable it or
+ * reprogram it to meet the application requires.
+ *
+ * To use the WDT, the user could follow these few steps:
+ * <ul>
+ * <li>Enable watchdog with given mode using \ref WDT_Enable().
+ * <li>Restart the watchdog using \ref WDT_Restart() within the watchdog period.
+ * </ul>
+ *
+ * For more accurate information, please look at the WDT section of the
+ * Datasheet.
+ *
+ * \note
+ * The Watchdog Mode Register (WDT_MR) can be written only once.\n
+ *
+ * Related files :\n
+ * \ref wdt.c\n
+ * \ref wdt.h.\n
+ */
+/*@{*/
+/*@}*/
+
+/*---------------------------------------------------------------------------
+ *        Headers
+ *---------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Enable watchdog with given mode.
+ *
+ * \note The Watchdog Mode Register (WDT_MR) can be written only once.
+ * Only a processor reset resets it.
+ *
+ * \param dwMode   WDT mode to be set
+ */
+extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode )
+{
+    pWDT->WDT_MR = dwMode ;
+}
+
+/**
+ * \brief Disable watchdog.
+ *
+ * \note The Watchdog Mode Register (WDT_MR) can be written only once.
+ * Only a processor reset resets it.
+ */
+extern void WDT_Disable( Wdt* pWDT )
+{
+    pWDT->WDT_MR = WDT_MR_WDDIS;
+}
+
+/**
+ * \brief Watchdog restart.
+ */
+extern void WDT_Restart( Wdt* pWDT )
+{
+    pWDT->WDT_CR = 0xA5000001;
+}
+
+/**
+ * \brief Watchdog get status.
+ */
+extern uint32_t WDT_GetStatus( Wdt* pWDT )
+{
+    return (pWDT->WDT_SR & 0x3) ;
+}
+
+/**
+ * \brief Watchdog get period.
+ *
+ * \param dwMs   desired watchdog period in millisecond.
+ */
+extern uint32_t WDT_GetPeriod( uint32_t dwMs )
+{
+    if ( (dwMs < 4) || (dwMs > 16000) )
+    {
+        return 0 ;
+    }
+    return ((dwMs << 8) / 1000) ;
+}