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this is just to better understand the flow

Change-Id: I045286836176da729cc8c863866d6f6aa3836592
This commit is contained in:
Kévin Redon
2019-05-14 23:32:48 +02:00
parent 7a060da30f
commit 7fd7674577
1 changed files with 27 additions and 22 deletions
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49
firmware/libcommon/source/mode_cardemu.c
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@@ -1,7 +1,7 @@
/* card emulation mode
*
* (C) 2015-2017 by Harald Welte <laforge@gnumonks.org>
* (C) 2018 by sysmocom -s.f.m.c. GmbH, Author: Kevin Redon <kredon@sysmocom.de>
* (C) 2018-2019 by sysmocom -s.f.m.c. GmbH, Author: Kevin Redon <kredon@sysmocom.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -188,41 +188,42 @@ int card_emu_uart_tx(uint8_t uart_chan, uint8_t byte)
return 1;
}
/* FIXME: integrate this with actual irq handler */
static void usart_irq_rx(uint8_t inst_num)
{
OSMO_ASSERT(inst_num < ARRAY_SIZE(cardem_inst));
Usart *usart = get_usart_by_chan(inst_num);
struct cardem_inst *ci = &cardem_inst[inst_num];
uint32_t csr;
uint8_t byte = 0;
csr = usart->US_CSR & usart->US_IMR;
csr = usart->US_CSR & usart->US_IMR; // save state/flags before they get changed
if (csr & US_CSR_RXRDY) {
byte = (usart->US_RHR) & 0xFF;
if (rbuf_write(&ci->rb, byte) < 0)
TRACE_ERROR("rbuf overrun\r\n");
if (csr & US_CSR_RXRDY) { // bytes has been received
byte = (usart->US_RHR) & 0xFF; // ready out byte
if (rbuf_write(&ci->rb, byte) < 0) // store byte in buffer
TRACE_ERROR("rbuf overrun\r\n"); // error if could not store in buffer
}
if (csr & US_CSR_TXRDY) {
if (card_emu_tx_byte(ci->ch) == 0)
USART_DisableIt(usart, US_IER_TXRDY);
if (csr & US_CSR_TXRDY) { // ready to transmit the next byte
if (card_emu_tx_byte(ci->ch) == 0) // transmit next byte, and check if a byte is being transmitted
USART_DisableIt(usart, US_IER_TXRDY); // stop the TX ready signal if not byte has been transmitted
}
if (csr & (US_CSR_OVRE|US_CSR_FRAME|US_CSR_PARE|
US_CSR_TIMEOUT|US_CSR_NACK|(1<<10))) {
usart->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;
TRACE_ERROR("%u e 0x%x st: 0x%lx\n", ci->num, byte, csr);
if (csr & (US_CSR_OVRE|US_CSR_FRAME|US_CSR_PARE|US_CSR_TIMEOUT|US_CSR_NACK|(1<<10))) { // error flag set
usart->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK; // reset UART state to clear flag
TRACE_ERROR("%u USART error on 0x%x status: 0x%lx\n", ci->num, byte, csr); // warn user about error
}
}
/*! ISR called for USART0 */
void mode_cardemu_usart0_irq(void)
{
/* USART0 == Instance 1 == USIM 2 */
usart_irq_rx(1);
}
/*! ISR called for USART1 */
void mode_cardemu_usart1_irq(void)
{
/* USART1 == Instance 0 == USIM 1 */
@@ -366,7 +367,7 @@ static void usim1_vcc_irqhandler(const Pin *pPin)
{
int active = PIO_Get(&pin_usim1_vcc) ? 1 : 0;
card_emu_io_statechg(cardem_inst[0].ch, CARD_IO_VCC, active);
/* FIXME do this for real */
/* FIXME readers enable clock after providing power and before releasing reset, but we should check it */
card_emu_io_statechg(cardem_inst[0].ch, CARD_IO_CLK, active);
}
#endif /* !DETECT_VCC_BY_ADC */
@@ -383,7 +384,7 @@ static void usim2_vcc_irqhandler(const Pin *pPin)
{
int active = PIO_Get(&pin_usim2_vcc) ? 1 : 0;
card_emu_io_statechg(cardem_inst[1].ch, CARD_IO_VCC, active);
/* FIXME do this for real */
/* FIXME readers enable clock after providing power and before releasing reset, but we should check it */
card_emu_io_statechg(cardem_inst[1].ch, CARD_IO_CLK, active);
}
#endif /* !DETECT_VCC_BY_ADC */
@@ -412,13 +413,15 @@ void mode_cardemu_init(void)
INIT_LLIST_HEAD(&cardem_inst[0].usb_out_queue);
rbuf_reset(&cardem_inst[0].rb);
PIO_Configure(pins_usim1, PIO_LISTSIZE(pins_usim1));
ISO7816_Init(&cardem_inst[0].usart_info, CLK_SLAVE);
NVIC_EnableIRQ(USART1_IRQn);
PIO_ConfigureIt(&pin_usim1_rst, usim1_rst_irqhandler);
PIO_EnableIt(&pin_usim1_rst);
ISO7816_Init(&cardem_inst[0].usart_info, CLK_SLAVE); // configure USART as ISO-7816 slave (e.g. card)
cardem_inst[0].usart_info.base->US_RTOR = 0; // don't use receive timeout timer for now
USART_EnableIt(cardem_inst[0].usart_info.base, US_IER_RXRDY | US_IER_TIMEOUT); // enable interrupts to indicate when data has been received or timeout occurred
NVIC_EnableIRQ(USART1_IRQn); // enable interrupt requests for the USART peripheral
PIO_ConfigureIt(&pin_usim1_rst, usim1_rst_irqhandler); // register ISR to handle reset signal change
PIO_EnableIt(&pin_usim1_rst); // enable interrupt for reset pin change
#ifndef DETECT_VCC_BY_ADC
PIO_ConfigureIt(&pin_usim1_vcc, usim1_vcc_irqhandler);
PIO_EnableIt(&pin_usim1_vcc);
PIO_ConfigureIt(&pin_usim1_vcc, usim1_vcc_irqhandler); // register ISR to handle VCC signal change
PIO_EnableIt(&pin_usim1_vcc); // enable interrupt for VCC pin change
#endif /* DETECT_VCC_BY_ADC */
cardem_inst[0].ch = card_emu_init(0, 2, 0, SIMTRACE_CARDEM_USB_EP_USIM1_DATAIN, SIMTRACE_CARDEM_USB_EP_USIM1_INT);
sim_switch_use_physical(0, 1);
@@ -428,6 +431,7 @@ void mode_cardemu_init(void)
rbuf_reset(&cardem_inst[1].rb);
PIO_Configure(pins_usim2, PIO_LISTSIZE(pins_usim2));
ISO7816_Init(&cardem_inst[1].usart_info, CLK_SLAVE);
// TODO enable timeout
NVIC_EnableIRQ(USART0_IRQn);
PIO_ConfigureIt(&pin_usim2_rst, usim2_rst_irqhandler);
PIO_EnableIt(&pin_usim2_rst);
@@ -437,6 +441,7 @@ void mode_cardemu_init(void)
#endif /* DETECT_VCC_BY_ADC */
cardem_inst[1].ch = card_emu_init(1, 0, 1, SIMTRACE_CARDEM_USB_EP_USIM2_DATAIN, SIMTRACE_CARDEM_USB_EP_USIM2_INT);
sim_switch_use_physical(1, 1);
// TODO check rst and vcc
#endif /* CARDEMU_SECOND_UART */
}