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clk calculation: updated max mul val

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Christina Quast
2015-02-20 14:40:07 +01:00
parent 49ba6bc1ba
commit b440c62140
1 changed files with 11 additions and 5 deletions
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16
clk_calc.py
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@@ -1,6 +1,9 @@
# frequ in MHz
f=18.432
ftarg=64.0
# Master clock:
#ftarg=64.0
# USB Clock:
ftarg=48.0
# PLL range: 60 MHz <= PLL <= 130 MHz
# MUL range: 4 <= MUL <= 7
@@ -8,10 +11,13 @@ ftarg=64.0
min_err_val=[1.0, 0.0]
min_err=f
for mul in range(1, 8):
for div in range(1, 0x20):
err=abs((f*mul/(1.0*div)) - ftarg)
print(mul, div, err)
#for mul in range(1, 8):
for mul in range(1, 36):
#for div in range(1, 0x20):
for div in range(1, 255):
freq=(f*mul/(1.0*div))
err=abs(freq - ftarg)
print(mul, div, freq, err)
if(err < min_err):
min_err_val=[mul, div]
print("last minerr: %f, new minerr: %f, mul: %d, div: %d" % (min_err, err, mul, div))