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iso7816_uart: starting point for pts parsing
This commit is contained in:
Christina Quast
641
firmware/src_simtrace/iso7816_uart.c
Normal file
641
firmware/src_simtrace/iso7816_uart.c
Normal file
@@ -0,0 +1,641 @@
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/* Driver for AT91SAM7 USART0 in ISO7816-3 mode for passive sniffing
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* (C) 2010 by Harald Welte <hwelte@hmw-consulting.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <errno.h>
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#include <string.h>
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#include <sys/types.h>
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#include <AT91SAM7.h>
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#include <lib_AT91SAM7.h>
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#include <openpcd.h>
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#include <simtrace_usb.h>
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#include <os/usb_handler.h>
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#include <os/dbgu.h>
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#include <os/pio_irq.h>
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#include "../simtrace.h"
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#include "../openpcd.h"
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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static const AT91PS_USART usart = AT91C_BASE_US0;
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enum iso7816_3_state {
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ISO7816_S_RESET, /* in Reset */
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ISO7816_S_WAIT_ATR, /* waiting for ATR to start */
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ISO7816_S_IN_ATR, /* while we are receiving the ATR */
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ISO7816_S_WAIT_APDU, /* waiting for start of new APDU */
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ISO7816_S_IN_APDU, /* inside a single APDU */
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ISO7816_S_IN_PTS, /* while we are inside the PTS / PSS */
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};
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/* detailed sub-states of ISO7816_S_IN_ATR */
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enum atr_state {
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ATR_S_WAIT_TS,
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ATR_S_WAIT_T0,
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ATR_S_WAIT_TA,
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ATR_S_WAIT_TB,
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ATR_S_WAIT_TC,
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ATR_S_WAIT_TD,
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ATR_S_WAIT_HIST,
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ATR_S_WAIT_TCK,
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ATR_S_DONE,
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};
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/* detailed sub-states of ISO7816_S_IN_PTS */
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enum pts_state {
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PTS_S_WAIT_REQ_PTSS,
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PTS_S_WAIT_REQ_PTS0,
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PTS_S_WAIT_REQ_PTS1,
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PTS_S_WAIT_REQ_PTS2,
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PTS_S_WAIT_REQ_PTS3,
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PTS_S_WAIT_REQ_PCK,
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PTS_S_WAIT_RESP_PTSS = PTS_S_WAIT_REQ_PTSS | 0x10,
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PTS_S_WAIT_RESP_PTS0 = PTS_S_WAIT_REQ_PTS0 | 0x10,
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PTS_S_WAIT_RESP_PTS1 = PTS_S_WAIT_REQ_PTS1 | 0x10,
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PTS_S_WAIT_RESP_PTS2 = PTS_S_WAIT_REQ_PTS2 | 0x10,
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PTS_S_WAIT_RESP_PTS3 = PTS_S_WAIT_REQ_PTS3 | 0x10,
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PTS_S_WAIT_RESP_PCK = PTS_S_WAIT_REQ_PCK | 0x10,
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};
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#define _PTSS 0
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#define _PTS0 1
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#define _PTS1 2
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#define _PTS2 3
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#define _PTS3 4
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#define _PCK 5
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struct iso7816_3_handle {
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enum iso7816_3_state state;
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u_int8_t fi;
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u_int8_t di;
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u_int8_t wi;
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u_int32_t waiting_time;
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enum atr_state atr_state;
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u_int8_t atr_idx;
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u_int8_t atr_hist_len;
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u_int8_t atr_last_td;
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u_int8_t atr[64];
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enum pts_state pts_state;
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u_int8_t pts_req[6];
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u_int8_t pts_resp[6];
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struct simtrace_hdr sh;
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int rctx_must_be_sent;
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struct req_ctx *rctx;
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};
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struct iso7816_3_handle isoh;
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/* Table 6 from ISO 7816-3 */
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static const u_int16_t fi_table[] = {
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0, 372, 558, 744, 1116, 1488, 1860, 0,
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0, 512, 768, 1024, 1536, 2048, 0, 0
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};
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/* Table 7 from ISO 7816-3 */
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static const u_int8_t di_table[] = {
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0, 1, 2, 4, 8, 16, 0, 0,
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0, 0, 2, 4, 8, 16, 32, 64,
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};
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/* compute the F/D ratio based on Fi and Di values */
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static int compute_fidi_ratio(u_int8_t fi, u_int8_t di)
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{
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u_int16_t f, d;
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int ret;
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if (fi >= ARRAY_SIZE(fi_table) ||
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di >= ARRAY_SIZE(di_table))
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return -EINVAL;
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f = fi_table[fi];
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if (f == 0)
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return -EINVAL;
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d = di_table[di];
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if (d == 0)
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return -EINVAL;
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if (di < 8)
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ret = f / d;
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else
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ret = f * d;
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return ret;
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}
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static void refill_rctx(struct iso7816_3_handle *ih)
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{
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struct req_ctx *rctx;
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rctx = req_ctx_find_get(0, RCTX_STATE_FREE,
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RCTX_STATE_LIBRFID_BUSY);
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if (!rctx) {
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ih->rctx = NULL;
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return;
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}
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ih->sh.cmd = SIMTRACE_MSGT_DATA;
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/* reserve spece at start of rctx */
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rctx->tot_len = sizeof(struct simtrace_hdr);
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ih->rctx = rctx;
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}
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static void send_rctx(struct iso7816_3_handle *ih)
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{
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struct req_ctx *rctx = ih->rctx;
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if (!rctx)
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return;
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/* copy the simtrace header */
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memcpy(rctx->data, &ih->sh, sizeof(ih->sh));
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req_ctx_set_state(rctx, RCTX_STATE_UDP_EP2_PENDING);
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memset(&ih->sh, 0, sizeof(ih->sh));
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ih->rctx = NULL;
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}
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/* Update the ATR sub-state */
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static void set_atr_state(struct iso7816_3_handle *ih, enum atr_state new_atrs)
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{
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if (new_atrs == ATR_S_WAIT_TS) {
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ih->atr_idx = 0;
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ih->atr_hist_len = 0;
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ih->atr_last_td = 0;
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memset(ih->atr, 0, sizeof(ih->atr));
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} else if (ih->atr_state == new_atrs)
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return;
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//DEBUGPCR("ATR state %u -> %u", ih->atr_state, new_atrs);
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ih->atr_state = new_atrs;
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}
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#define ISO7816_3_INIT_WTIME 9600
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#define ISO7816_3_DEFAULT_WI 10
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static void update_fidi(struct iso7816_3_handle *ih)
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{
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int rc;
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rc = compute_fidi_ratio(ih->fi, ih->di);
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if (rc > 0 && rc < 0x400) {
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DEBUGPCR("computed Fi(%u) Di(%u) ratio: %d", ih->fi, ih->di, rc);
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/* make sure UART uses new F/D ratio */
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usart->US_CR |= AT91C_US_RXDIS | AT91C_US_RSTRX;
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usart->US_FIDI = rc & 0x3ff;
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usart->US_CR |= AT91C_US_RXEN | AT91C_US_STTTO;
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/* notify ETU timer about this */
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tc_etu_set_etu(rc);
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} else
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DEBUGPCRF("computed FiDi ratio %d unsupported", rc);
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}
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/* Update the ISO 7816-3 APDU receiver state */
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static void set_state(struct iso7816_3_handle *ih, enum iso7816_3_state new_state)
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{
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if (new_state == ISO7816_S_RESET) {
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usart->US_CR |= AT91C_US_RXDIS | AT91C_US_RSTRX;
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} else if (new_state == ISO7816_S_WAIT_ATR) {
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/* Reset to initial Fi / Di ratio */
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ih->fi = 1;
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ih->di = 1;
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update_fidi(ih);
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/* initialize todefault WI, this will be overwritten if we
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* receive TC2, and it will be programmed into hardware after
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* ATR is finished */
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ih->wi = ISO7816_3_DEFAULT_WI;
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/* update waiting time to initial waiting time */
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ih->waiting_time = ISO7816_3_INIT_WTIME;
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tc_etu_set_wtime(ih->waiting_time);
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/* Set ATR sub-state to initial state */
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set_atr_state(ih, ATR_S_WAIT_TS);
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/* Notice that we are just coming out of reset */
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ih->sh.flags |= SIMTRACE_FLAG_ATR;
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}
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if (ih->state == new_state)
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return;
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//DEBUGPCR("7816 state %u -> %u", ih->state, new_state);
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ih->state = new_state;
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}
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/* determine the next ATR state based on received interface byte */
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static enum atr_state next_intb_state(struct iso7816_3_handle *ih, u_int8_t ch)
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{
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switch (ih->atr_state) {
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case ATR_S_WAIT_TD:
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case ATR_S_WAIT_T0:
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ih->atr_last_td = ch;
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goto from_td;
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case ATR_S_WAIT_TC:
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if ((ih->atr_last_td & 0x0f) == 0x02) {
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/* TC2 contains WI */
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ih->wi = ch;
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}
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goto from_tc;
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case ATR_S_WAIT_TB:
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goto from_tb;
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case ATR_S_WAIT_TA:
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goto from_ta;
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default:
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DEBUGPCR("something wrong, old_state != TA");
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return ATR_S_WAIT_TCK;
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}
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from_td:
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if (ih->atr_last_td & 0x10)
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return ATR_S_WAIT_TA;
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from_ta:
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if (ih->atr_last_td & 0x20)
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return ATR_S_WAIT_TB;
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from_tb:
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if (ih->atr_last_td & 0x40)
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return ATR_S_WAIT_TC;
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from_tc:
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if (ih->atr_last_td & 0x80)
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return ATR_S_WAIT_TD;
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return ATR_S_WAIT_HIST;
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}
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/* process an incomng ATR byte */
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static enum iso7816_3_state
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process_byte_atr(struct iso7816_3_handle *ih, u_int8_t byte)
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{
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/* add byte to ATR buffer */
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ih->atr[ih->atr_idx] = byte;
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ih->atr_idx++;
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switch (ih->atr_state) {
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case ATR_S_WAIT_TS:
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/* FIXME: if we don't have the RST line we might get this */
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if (byte == 0) {
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ih->atr_idx--;
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break;
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}
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/* FIXME: check inverted logic */
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set_atr_state(ih, ATR_S_WAIT_T0);
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break;
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case ATR_S_WAIT_T0:
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/* obtain the number of historical bytes */
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ih->atr_hist_len = byte & 0xf;
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/* Mask out the hist-byte-length to indiicate T=0 */
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set_atr_state(ih, next_intb_state(ih, byte & 0xf0));
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break;
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case ATR_S_WAIT_TA:
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case ATR_S_WAIT_TB:
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case ATR_S_WAIT_TC:
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case ATR_S_WAIT_TD:
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set_atr_state(ih, next_intb_state(ih, byte));
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break;
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case ATR_S_WAIT_HIST:
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ih->atr_hist_len--;
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/* after all historical bytes are recieved, go to TCK */
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if (ih->atr_hist_len == 0)
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set_atr_state(ih, ATR_S_WAIT_TCK);
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break;
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case ATR_S_WAIT_TCK:
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/* FIXME: process and verify the TCK */
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set_atr_state(ih, ATR_S_DONE);
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/* send off the USB context */
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ih->rctx_must_be_sent = 1;
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/* update the waiting time */
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ih->waiting_time = 960 * di_table[ih->di] * ih->wi;
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tc_etu_set_wtime(ih->waiting_time);
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return ISO7816_S_WAIT_APDU;
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}
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return ISO7816_S_IN_ATR;
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}
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/* Update the ATR sub-state */
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static void set_pts_state(struct iso7816_3_handle *ih, enum pts_state new_ptss)
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{
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//DEBUGPCR("PTS state %u -> %u", ih->pts_state, new_ptss);
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ih->pts_state = new_ptss;
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}
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/* Determine the next PTS state */
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static enum pts_state next_pts_state(struct iso7816_3_handle *ih)
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{
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u_int8_t is_resp = ih->pts_state & 0x10;
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u_int8_t sstate = ih->pts_state & 0x0f;
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u_int8_t *pts_ptr;
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if (!is_resp)
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pts_ptr = ih->pts_req;
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else
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pts_ptr = ih->pts_resp;
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switch (sstate) {
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case PTS_S_WAIT_REQ_PTSS:
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goto from_ptss;
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case PTS_S_WAIT_REQ_PTS0:
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goto from_pts0;
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case PTS_S_WAIT_REQ_PTS1:
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goto from_pts1;
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case PTS_S_WAIT_REQ_PTS2:
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goto from_pts2;
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case PTS_S_WAIT_REQ_PTS3:
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goto from_pts3;
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}
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if (ih->pts_state == PTS_S_WAIT_REQ_PCK)
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return PTS_S_WAIT_RESP_PTSS;
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from_ptss:
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return PTS_S_WAIT_REQ_PTS0 | is_resp;
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from_pts0:
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if (pts_ptr[_PTS0] & (1 << 4))
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return PTS_S_WAIT_REQ_PTS1 | is_resp;
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from_pts1:
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if (pts_ptr[_PTS0] & (1 << 5))
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return PTS_S_WAIT_REQ_PTS2 | is_resp;
|
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from_pts2:
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if (pts_ptr[_PTS0] & (1 << 6))
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return PTS_S_WAIT_REQ_PTS3 | is_resp;
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from_pts3:
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return PTS_S_WAIT_REQ_PCK | is_resp;
|
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}
|
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|
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static enum iso7816_3_state
|
||||
process_byte_pts(struct iso7816_3_handle *ih, u_int8_t byte)
|
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{
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switch (ih->pts_state) {
|
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case PTS_S_WAIT_REQ_PTSS:
|
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ih->pts_req[_PTSS] = byte;
|
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break;
|
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case PTS_S_WAIT_REQ_PTS0:
|
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ih->pts_req[_PTS0] = byte;
|
||||
break;
|
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case PTS_S_WAIT_REQ_PTS1:
|
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ih->pts_req[_PTS1] = byte;
|
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break;
|
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case PTS_S_WAIT_REQ_PTS2:
|
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ih->pts_req[_PTS2] = byte;
|
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break;
|
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case PTS_S_WAIT_REQ_PTS3:
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ih->pts_req[_PTS3] = byte;
|
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break;
|
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case PTS_S_WAIT_REQ_PCK:
|
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/* FIXME: check PCK */
|
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ih->pts_req[_PCK] = byte;
|
||||
break;
|
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case PTS_S_WAIT_RESP_PTSS:
|
||||
ih->pts_resp[_PTSS] = byte;
|
||||
break;
|
||||
case PTS_S_WAIT_RESP_PTS0:
|
||||
ih->pts_resp[_PTS0] = byte;
|
||||
break;
|
||||
case PTS_S_WAIT_RESP_PTS1:
|
||||
/* This must be TA1 */
|
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ih->fi = byte >> 4;
|
||||
ih->di = byte & 0xf;
|
||||
DEBUGPCR("found Fi=%u Di=%u", ih->fi, ih->di);
|
||||
ih->pts_resp[_PTS1] = byte;
|
||||
break;
|
||||
case PTS_S_WAIT_RESP_PTS2:
|
||||
ih->pts_resp[_PTS2] = byte;
|
||||
break;
|
||||
case PTS_S_WAIT_RESP_PTS3:
|
||||
ih->pts_resp[_PTS3] = byte;
|
||||
break;
|
||||
case PTS_S_WAIT_RESP_PCK:
|
||||
ih->pts_resp[_PCK] = byte;
|
||||
/* FIXME: check PCK */
|
||||
set_pts_state(ih, PTS_S_WAIT_REQ_PTSS);
|
||||
/* update baud rate generator with Fi/Di */
|
||||
update_fidi(ih);
|
||||
/* Wait for the next APDU */
|
||||
return ISO7816_S_WAIT_APDU;
|
||||
}
|
||||
/* calculate the next state and set it */
|
||||
set_pts_state(ih, next_pts_state(ih));
|
||||
|
||||
return ISO7816_S_IN_PTS;
|
||||
}
|
||||
|
||||
static void process_byte(struct iso7816_3_handle *ih, u_int8_t byte)
|
||||
{
|
||||
int new_state = -1;
|
||||
struct req_ctx *rctx;
|
||||
|
||||
if (!ih->rctx)
|
||||
refill_rctx(ih);
|
||||
|
||||
switch (ih->state) {
|
||||
case ISO7816_S_RESET:
|
||||
break;
|
||||
case ISO7816_S_WAIT_ATR:
|
||||
case ISO7816_S_IN_ATR:
|
||||
new_state = process_byte_atr(ih, byte);
|
||||
break;
|
||||
case ISO7816_S_WAIT_APDU:
|
||||
if (byte == 0xff) {
|
||||
new_state = process_byte_pts(ih, byte);
|
||||
goto out_silent;
|
||||
}
|
||||
case ISO7816_S_IN_APDU:
|
||||
new_state = ISO7816_S_IN_APDU;
|
||||
break;
|
||||
case ISO7816_S_IN_PTS:
|
||||
new_state = process_byte_pts(ih, byte);
|
||||
goto out_silent;
|
||||
}
|
||||
|
||||
/* The USB buffer could be gone in case the timer expired or code above
|
||||
* this line explicitly sent it off */
|
||||
if (!ih->rctx)
|
||||
refill_rctx(ih);
|
||||
|
||||
rctx = ih->rctx;
|
||||
if (!rctx) {
|
||||
DEBUGPCR("==> Lost byte, missing rctx");
|
||||
return;
|
||||
}
|
||||
|
||||
/* store the byte in the USB request context */
|
||||
rctx->data[rctx->tot_len] = byte;
|
||||
rctx->tot_len++;
|
||||
|
||||
if (rctx->tot_len >= rctx->size || ih->rctx_must_be_sent) {
|
||||
ih->rctx_must_be_sent = 0;
|
||||
send_rctx(ih);
|
||||
}
|
||||
|
||||
out_silent:
|
||||
if (new_state != -1)
|
||||
set_state(ih, new_state);
|
||||
}
|
||||
|
||||
/* timeout of work waiting time during receive */
|
||||
void iso7816_wtime_expired(void)
|
||||
{
|
||||
/* Always flush the URB at Rx timeout as this indicates end of APDU */
|
||||
if (isoh.rctx) {
|
||||
isoh.sh.flags |= SIMTRACE_FLAG_WTIME_EXP;
|
||||
send_rctx(&isoh);
|
||||
}
|
||||
if (isoh.state == ISO7816_S_IN_PTS) {
|
||||
/* Timout during PTS: Card does not support PTS */
|
||||
}
|
||||
set_state(&isoh, ISO7816_S_WAIT_APDU);
|
||||
}
|
||||
|
||||
static __ramfunc void usart_irq(void)
|
||||
{
|
||||
u_int32_t csr = usart->US_CSR;
|
||||
u_int8_t octet;
|
||||
|
||||
//DEBUGP("USART IRQ, CSR=0x%08x\n", csr);
|
||||
|
||||
if (csr & AT91C_US_RXRDY) {
|
||||
/* at least one character received */
|
||||
octet = usart->US_RHR & 0xff;
|
||||
//DEBUGP("%02x ", octet);
|
||||
process_byte(&isoh, octet);
|
||||
}
|
||||
|
||||
if (csr & AT91C_US_TXRDY) {
|
||||
/* nothing to transmit anymore */
|
||||
}
|
||||
|
||||
if (csr & (AT91C_US_PARE|AT91C_US_FRAME|AT91C_US_OVRE)) {
|
||||
/* FIXME: some error has occurrerd */
|
||||
}
|
||||
}
|
||||
|
||||
/* handler for the RST input pin state change */
|
||||
static void reset_pin_irq(u_int32_t pio)
|
||||
{
|
||||
if (!AT91F_PIO_IsInputSet(AT91C_BASE_PIOA, pio)) {
|
||||
DEBUGPCR("nRST");
|
||||
set_state(&isoh, ISO7816_S_RESET);
|
||||
} else {
|
||||
DEBUGPCR("RST");
|
||||
set_state(&isoh, ISO7816_S_WAIT_ATR);
|
||||
}
|
||||
}
|
||||
|
||||
void iso_uart_dump(void)
|
||||
{
|
||||
u_int32_t csr = usart->US_CSR;
|
||||
|
||||
DEBUGPCR("USART CSR=0x%08x", csr);
|
||||
}
|
||||
|
||||
void iso_uart_rst(unsigned int state)
|
||||
{
|
||||
DEBUGPCR("USART set nRST set state=%u", state);
|
||||
switch (state) {
|
||||
case 0:
|
||||
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, SIMTRACE_PIO_nRST);
|
||||
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, SIMTRACE_PIO_nRST);
|
||||
break;
|
||||
case 1:
|
||||
AT91F_PIO_SetOutput(AT91C_BASE_PIOA, SIMTRACE_PIO_nRST);
|
||||
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, SIMTRACE_PIO_nRST);
|
||||
break;
|
||||
default:
|
||||
AT91F_PIO_CfgInput(AT91C_BASE_PIOA, SIMTRACE_PIO_nRST);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void iso_uart_rx_mode(void)
|
||||
{
|
||||
DEBUGPCR("USART Entering Rx Mode");
|
||||
/* Enable receive interrupts */
|
||||
usart->US_IER = AT91C_US_RXRDY | AT91C_US_OVRE | AT91C_US_FRAME |
|
||||
AT91C_US_PARE | AT91C_US_NACK | AT91C_US_ITERATION;
|
||||
|
||||
/* call interrupt handler once to set initial state RESET / ATR */
|
||||
reset_pin_irq(SIMTRACE_PIO_nRST);
|
||||
}
|
||||
|
||||
void iso_uart_clk_master(unsigned int master)
|
||||
{
|
||||
DEBUGPCR("USART Clock Master %u", master);
|
||||
if (master) {
|
||||
usart->US_MR = AT91C_US_USMODE_ISO7816_0 | AT91C_US_CLKS_CLOCK |
|
||||
AT91C_US_CHRL_8_BITS | AT91C_US_NBSTOP_1_BIT |
|
||||
AT91C_US_CKLO;
|
||||
usart->US_BRGR = (0x0000 << 16) | 16;
|
||||
} else {
|
||||
usart->US_MR = AT91C_US_USMODE_ISO7816_0 | AT91C_US_CLKS_EXT |
|
||||
AT91C_US_CHRL_8_BITS | AT91C_US_NBSTOP_1_BIT |
|
||||
AT91C_US_CKLO;
|
||||
usart->US_BRGR = (0x0000 << 16) | 0x0001;
|
||||
}
|
||||
}
|
||||
|
||||
void iso_uart_init(void)
|
||||
{
|
||||
DEBUGPCR("USART Initializing");
|
||||
|
||||
refill_rctx(&isoh);
|
||||
|
||||
/* make sure we get clock from the power management controller */
|
||||
AT91F_US0_CfgPMC();
|
||||
|
||||
/* configure all 3 signals as input */
|
||||
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, SIMTRACE_PIO_IO, SIMTRACE_PIO_CLK);
|
||||
AT91F_PIO_CfgInput(AT91C_BASE_PIOA, SIMTRACE_PIO_nRST);
|
||||
|
||||
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_US0,
|
||||
OPENPCD_IRQ_PRIO_USART,
|
||||
AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &usart_irq);
|
||||
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_US0);
|
||||
|
||||
usart->US_CR = AT91C_US_RXDIS | AT91C_US_TXDIS |
|
||||
(AT91C_US_RSTRX | AT91C_US_RSTTX);
|
||||
/* FIXME: wait for some time */
|
||||
usart->US_CR = AT91C_US_RXDIS | AT91C_US_TXDIS;
|
||||
|
||||
/* ISO7816 T=0 mode with external clock input */
|
||||
usart->US_MR = AT91C_US_USMODE_ISO7816_0 | AT91C_US_CLKS_EXT |
|
||||
AT91C_US_CHRL_8_BITS | AT91C_US_NBSTOP_1_BIT |
|
||||
AT91C_US_CKLO;
|
||||
|
||||
/* Disable all interrupts */
|
||||
usart->US_IDR = 0xff;
|
||||
/* Clock Divider = 1, i.e. no division of SCLK */
|
||||
usart->US_BRGR = (0x0000 << 16) | 0x0001;
|
||||
/* Disable Receiver Time-out */
|
||||
usart->US_RTOR = 0;
|
||||
/* Disable Transmitter Timeguard */
|
||||
usart->US_TTGR = 0;
|
||||
|
||||
pio_irq_register(SIMTRACE_PIO_nRST, &reset_pin_irq);
|
||||
AT91F_PIO_CfgInputFilter(AT91C_BASE_PIOA, SIMTRACE_PIO_nRST);
|
||||
pio_irq_enable(SIMTRACE_PIO_nRST);
|
||||
}
|
||||
6
firmware/src_simtrace/iso7816_uart.h
Normal file
6
firmware/src_simtrace/iso7816_uart.h
Normal file
@@ -0,0 +1,6 @@
|
||||
|
||||
void iso_uart_dump(void);
|
||||
void iso_uart_rst(unsigned int state);
|
||||
void iso_uart_rx_mode(void);
|
||||
void iso_uart_clk_master(unsigned int master);
|
||||
void iso_uart_init(void);
|
||||
Reference in New Issue
Block a user