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https://gitea.osmocom.org/sim-card/simtrace2.git
synced 2026-03-16 21:28:33 +03:00
set main clock for using UART at 921600 bps
UART baud rate is main clock (MCK) divided by CR*16. The MCK values are chosen >= 48 MHz and <= 64 MHz to have a near integer value CR for a baud rate of 921600 bps. The end MCK frequency between simtrace and qmod differ slightly but are close to 58 MHz. Change-Id: Iaa4a97fc68494c93b9d128503515d88049de506c
This commit is contained in:
@@ -53,8 +53,6 @@
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/** Core definition */
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#define cortexm3
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#define BOARD_MCK 48000000
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#define PIO_LED_RED PIO_PA17
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#define PIO_LED_GREEN PIO_PA18
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@@ -46,39 +46,39 @@
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#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
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#define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
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#if (BOARD_MCK == 48000000)
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#if (BOARD_MAINOSC == 18432000)
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/* Clock settings at 48MHz for 18 MHz crystal */
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(13-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(5))
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#elif (BOARD_MAINOSC == 12000000)
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/* QMod has 12 MHz clock, so multply by 8 (96 MHz) and divide by 2 */
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/** configure PLL to generate main clock based on main oscillator frequency */
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#if (BOARD_MAINOSC == 12000000) && (BOARD_MCK == 48000000)
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(8-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(2))
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#else
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#error "Please define PLLA config for your MAINOSC frequency"
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#endif /* MAINOSC */
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#elif (BOARD_MCK == 64000000)
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#if (BOARD_MAINOSC == 18432000)
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/* Clock settings at 64MHz for 18 MHz crystal: 64.512 MHz */
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#elif (BOARD_MAINOSC == 12000000) && (BOARD_MCK == 58000000)
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(7-1) \
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| CKGR_PLLAR_MULA(29-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(2))
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#elif (BOARD_MAINOSC == 12000000)
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/* QMod has 12 MHz clock, so multply by 10 / div by 2: 60 MHz */
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| CKGR_PLLAR_DIVA(6))
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#elif (BOARD_MAINOSC == 12000000) && (BOARD_MCK == 60000000)
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(10-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(2))
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#error "Please define PLLA config for your MAINOSC frequency"
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#endif /* MAINOSC */
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#elif (BOARD_MAINOSC == 18432000) && (BOARD_MCK == 47923200)
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(13-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(5))
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#elif (BOARD_MAINOSC == 18432000) && (BOARD_MCK == 58982400)
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(16-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(5))
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#elif (BOARD_MAINOSC == 18432000) && (BOARD_MCK == 64512000)
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#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
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| CKGR_PLLAR_MULA(7-1) \
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| CKGR_PLLAR_PLLACOUNT(0x1) \
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| CKGR_PLLAR_DIVA(2))
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#else
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#error "No PLL settings for current BOARD_MCK."
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#error "Please define PLLA config for your BOARD_MCK/MAINOSC frequency"
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#endif
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#if (BOARD_MAINOSC == 12000000)
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@@ -25,7 +25,10 @@
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/** Board definition */
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#define owhw
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/** oscillator used as main clock source (in Hz) */
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#define BOARD_MAINOSC 18432000
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/** desired main clock frequency (in Hz, based on BOARD_MAINOSC) */
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#define BOARD_MCK 58982400 // 18.432 * 16 / 5
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/* USIM 2 interface (USART) */
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#define PIN_USIM2_CLK {PIO_PA2, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
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@@ -28,7 +28,10 @@
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/** Board definition */
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#define qmod
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/** oscillator used as main clock source (in Hz) */
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#define BOARD_MAINOSC 12000000
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/** desired main clock frequency (in Hz, based on BOARD_MAINOSC) */
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#define BOARD_MCK 58000000 // 18.432 * 29 / 6
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/* USIM 2 interface (USART) */
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#define PIN_USIM2_CLK {PIO_PA2, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
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@@ -26,8 +26,10 @@
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/* Board definition */
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#define simtrace
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/* Board main oscillator frequency (in Hz) */
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/** oscillator used as main clock source (in Hz) */
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#define BOARD_MAINOSC 18432000
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/** desired main clock frequency (in Hz, based on BOARD_MAINOSC) */
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#define BOARD_MCK 58982400 // 18.432 * 16 / 5
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/** Pin configuration **/
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/* Button to force bootloader start (shorted to ground when pressed */
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