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mirror of https://github.com/gillham/logic_analyzer.git synced 2026-05-01 23:53:02 +03:00
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739144d57e8f53c0b3f668f2183ce0026a43c964
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2 Commits

Author SHA1 Message Date
Andrew Gillham
739144d57e Fix off by one on the capture buffer due to earlier debugging. I finally realized I was checking if an unsigned int was less than zero. Thanks Szilárd for the correct indexes in the issue comments. 2023-10-03 23:48:07 -05:00
Andrew Gillham
0b2651864e Add a sketch with Sigrok support. Basically returning the capture buffer in the opposite order. 2023-10-03 23:00:05 -05:00
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