Andrew Gillham 739144d57e Fix off by one on the capture buffer due to earlier debugging. I finally realized I was checking if an unsigned int was less than zero. Thanks Szilárd for the correct indexes in the issue comments.

2023-10-03 23:48:07 -05:00

..

LICENSE

Add a sketch with Sigrok support. Basically returning the capture buffer in the opposite order.

2023-10-03 23:00:05 -05:00

logic_analyzer_inline_2mhz.ino

Fix off by one on the capture buffer due to earlier debugging. I finally realized I was checking if an unsigned int was less than zero. Thanks Szilárd for the correct indexes in the issue comments.

2023-10-03 23:48:07 -05:00

logic_analyzer_inline_4mhz.ino

Fix off by one on the capture buffer due to earlier debugging. I finally realized I was checking if an unsigned int was less than zero. Thanks Szilárd for the correct indexes in the issue comments.

2023-10-03 23:48:07 -05:00

logic_analyzer_sigrok.ino

Fix off by one on the capture buffer due to earlier debugging. I finally realized I was checking if an unsigned int was less than zero. Thanks Szilárd for the correct indexes in the issue comments.

2023-10-03 23:48:07 -05:00