180 Commits

Author SHA1 Message Date
Oliver Smith
2bbb7cd7f8 contrib/jenkins.sh: add new script
Prepare to replace the legacy SIMTRACE jenkins job with a new
master-simtrace job that works like other master build jobs. Move the
build commands from the old job into this contrib/jenkins.sh file.
2023-08-29 11:59:59 +02:00
Harald Welte
122531949d smartcard-fpc: add BOM attributes 2023-01-25 22:00:24 +01:00
Harald Welte
7dfb319dc0 smartcard-fpc: update gerber export 2023-01-25 21:59:41 +01:00
Harald Welte
c1338a1186 smartcard-fpc: Add company logo / marketing + version indication 2023-01-25 20:56:38 +01:00
Harald Welte
72b0040cee smartcard-fpc: Move labels / WEEE bin to different location 2023-01-25 20:55:33 +01:00
Harald Welte
cda1ef7f75 smartcard-fpc: Update to use with JUSHUO-AFA07 FPC connector 2023-01-25 20:55:33 +01:00
Kévin Redon
dfc1c4fc72 expert 4FF-FFC gerbers 2022-11-20 20:34:36 +01:00
Kévin Redon
ac4f87a06b add 4FF-FFC design in 4 directions
only 2 directions were present
2022-11-20 20:33:20 +01:00
Harald Welte
8e3eccd270 update git URLs (git -> https; gitea) 2022-06-17 23:02:39 +02:00
Harald Welte
22f87eb4e5 smartcard-fpc: Don't put solder cream on smartcard contacts 2021-01-14 15:33:37 +01:00
Harald Welte
b161f50e72 add full-size smartcard to FPC adapter design files 2020-12-29 17:30:02 +01:00
Kévin Redon
6dc3393177 add v1.5 release file
Change-Id: I1185e30cb241b08b87ea3131c6a582fc96fe8fa5
2019-10-01 15:27:32 +02:00
Kévin Redon
01fb365d32 add README wit hardwar eproject details
Change-Id: Ie5f2ac7d15d28e44abb60fdbc16f3e9f97544b03
2019-10-01 15:24:59 +02:00
Kévin Redon
3d2234cf66 update BOM with DNP parts
Change-Id: If650fa0a806e77d72c432a83388c0a7e414333cc
2019-10-01 15:23:12 +02:00
Kévin Redon
518fb3f40a add parts related datasheets
Change-Id: Ic61f1311d688f5a515385ca992a60f7f0fc75e82
2019-10-01 15:02:49 +02:00
Kévin Redon
6202db5089 Merge branch 'v1.5'
Change-Id: I19221ac1e88ee4ba6b74705f898c145fe76724a2
2019-10-01 15:00:28 +02:00
Kévin Redon
8958907a57 add v1.4 release files
Change-Id: I788d3b970fe8ec277bd77e0fe61bd795d554e94c
2019-10-01 14:58:35 +02:00
Kévin Redon
2714c8d357 Merge branch 'v1.4'
Change-Id: Ie406e2d62adbd2e9914b04b9d874d2bd520026a9
2019-10-01 14:57:42 +02:00
Kévin Redon
f9895d703d add v1.3 release files
Change-Id: I32d82402a8c56ae2b27345bbff20c3214c1ed017
2019-10-01 14:47:45 +02:00
Kévin Redon
83d28736a3 Merge branch 'v1.3'
Change-Id: I8ecde4dd1b6ff749e762bb2c42f99df04723c753
2019-10-01 14:44:15 +02:00
Kévin Redon
eb020e6071 add v1.2p release files
Change-Id: I21c9a9a0b96cdc68aea454b3c72091e02efdc01a
2019-10-01 14:37:39 +02:00
Kévin Redon
02405c014b Merge branch 'v1.2_production'
Change-Id: Ib4cba75e8e3cb795b38db588f6ad452e1ff26faa
2019-10-01 14:34:07 +02:00
Kévin Redon
18ed2c1ed8 add v1.1p release files
Change-Id: Ie0f05b912df1f1c44157be2cea24c12d75627374
2019-10-01 14:30:46 +02:00
Kévin Redon
dc4cb0a9ac Merge branch 'v1.1_production'
Change-Id: Ie064c379c9625b3cf6910912fd859e8e4dd0326e
2019-10-01 14:28:01 +02:00
Kévin Redon
74eb7fad6d add v1.0p release files
Change-Id: Id4b69f1b6deac0a7d0f3725f2d96d75c5b6c6ca8
2019-10-01 14:25:31 +02:00
Kévin Redon
8c202c012b Merge branch 'v1.0_production'
Change-Id: I481a6b1802993ceb6d02e7edcbd3b6d853f1e487
2019-10-01 14:21:04 +02:00
Kévin Redon
ceeb2b1ad8 add v1.0 release files
Change-Id: I879d35bca5bbaf2bc9616d181b085b4af7196fdc
2019-10-01 14:17:35 +02:00
Kévin Redon
28eff3dced schematic: add DNP note on JTAG and UART debug connectors
Change-Id: Id1c03418af021ce8febd666946bed3d8c01ceb77
2019-10-01 13:09:04 +02:00
Kévin Redon
06b45f17b6 schematic: mark P1 and P2 as dot no place
P1 (JTAG) and P2 (FTDI UART) are onlz needed to be placed on
boards meant for development.
this can by done by hand separately.

Change-Id: I039ecff7d910f3de549bf2cec264a860c8ea1d34
2019-09-03 21:26:05 +02:00
Kévin Redon
bea9406bb1 schematic: mark USB reset circuit as dot no place
the additional circuit to reset USB (by pulling D+ low) is not
required anymore since the USB controller in the SAM3S integrates
this capability.
the SAM3S-EK Development Board also demonstrates only the inline
27 Ohm termination resistors are required.

this change has been tested (behind 2 USB HUBs).
the RESET button still works.
resetting using DFU into the bootloader and starting the
application from the bootloader still works.

Change-Id: I648a041f6d3cf456f1783249546078961f85e662
2019-09-03 21:13:44 +02:00
Kévin Redon
614ce7a7d8 schematic: mark R19 as dot no place
R19 pulls VCC_PHONE low for better power on detection.
but the voltage divider R20 + R21 also pull this line low using
a stronger pull down resistor ok 20 kOhm.
thus R19 is unnecessary-

this change has been tested with a real simtrace device.
trace and card emulation worked with a Nokia 3310.

Change-Id: I0dd2025a8634f0ec38060cfbaae68618a4198fca
2019-09-03 20:33:57 +02:00
Kévin Redon
af693b2ee0 schematic: rename NP to DNP for clarity
Change-Id: I06c38e353f2b804faa0dcbf4a9405d5d5042af3e
2019-09-03 17:52:24 +02:00
Kévin Redon
31f31e24eb schematic: mark JP1 and JP2 as dot no place
the protruding through hole pins of the header for the jumper
might get shorted when the board lies on a conductive surface,
leading to unwanted flash erase (JP2) or false TST signal (JP1)

Change-Id: I7fc6176d8c63ab8274b641e7bcd990093af3c4ca
2019-09-03 17:47:55 +02:00
Kévin Redon
2ad8ff8100 schematic: mark R22 as dot no place
R22 is use to pull the FLAGB output of the FPF2109 high since this
is an open-drain output.
but we actually don't read FLAGB do get the error conditions, thus
thus pull-up resistor is not required.

this change has been tested with a real simtrace device.
trace and card emulation worked with a Nokia 3310.

Change-Id: I3dd82864708f1ecb30ddbaa4c60aa600325455e2
2019-09-03 17:40:31 +02:00
Kévin Redon
3df5a7f274 schematic: mark R24 as no place
R24 is pulling the voltage regulator output for VCC_SIM down.
it has probably been added at the same time as R15.
since we don't read VCC_SIM it is not important to have it in a
defined state.
also the card, phone, or simtrace will provide power to the card
when required (else the card load is high enough to immediately
pull it down).

this change has been tested with a real simtrace device.
trace and card emulation worked with a Nokia 3310.

Change-Id: Iaae0959b62bc9348279bc5d840addbeb28fdf98f
2019-09-03 17:20:50 +02:00
Kévin Redon
9cb8f504cb schematic: mark R15 as no place
R15 is pulling VCC_SIM down.
it has probably been added because a load resistor is present in
the FPF2109 datasheet example application, or to not have VCC_SIM
in tri-state.
since we don't read VCC_SIM it is not important to have it in a
defined state.
also the card, phone, or simtrace will provide power to the card
when required (else the card load is high enough to immediately
pull it down).
current flowing from the other card pins back to VCC should not
happen, and if it happens this high value resistor will not have
any effect.

this change has been tested with a real device.
trace and card emulation worked with a Nokia 3310.

Change-Id: I002b1fcf1039c8910d902e476a47183172d70761
2019-09-03 17:08:46 +02:00
Kévin Redon
7fc392aabf schematic: make it more readable
- VCC is up
- GND is down
- group the parts by functionality and use net name
- separate decoupling capacitors
- arrange groups from left input to right output

Change-Id: I2d894dd10b8b619ccbce1ae8b7e25316963157c8
2019-09-03 14:48:23 +02:00
Kévin Redon
9bf63354e7 updated libraries to KiCad 5
the library system changed from KiCad 4 to KiCad 5.
the custom libraries have been re-added to the project, and all
symbol names have been updated.
some symbols are a bit smaller, requiring to add some wires.

Change-Id: Id8e61aab6f05c633f455ef0d338c1658a62a2c4a
2019-08-27 17:31:37 +02:00
Kévin Redon
2bdf944c11 remove unused cable project
the layout for the FPC cable was not existing, and the schematic
is not an actual part of SIMtrace.
the FPC cables are designed separately.

Change-Id: I9138476c96404e18161b58b7b3a7a450ce633e81
2019-08-27 17:28:21 +02:00
Harald Welte
6fde8e1c26 update README with current information + convert to Markdown 2017-03-17 22:49:14 +01:00
Harald Welte
197ed82a32 add 'sysmocom' name to mini-UICC and nano-UICC adapters
As sysmocom is the only company manufacturing them for now, we add this
branding to the design files.
2016-04-01 13:13:53 +02:00
Harald Welte
46aceb222a remove second copy of mini-UICC FPC adapter 2016-04-01 10:06:09 +02:00
Harald Welte
0a530496b5 Add 4FF (nanoSIM) adapter 2015-08-19 15:02:51 +02:00
King Kévin
6279da6fe0 change microcontroller to SAM3S 2015-07-05 09:58:19 +02:00
Harald Welte
3fc0e7da79 Update BOM for v1.4
* AT91SAM128D, not C, as old is EOL
* New ferrite bead / filter, as old is EOL.
* Flash S25FL032P0XMFI011, was already populated in v1.3
2014-06-26 11:34:44 +02:00
Kevin Redon
2a63d76a74 export schematic, and pcb (with minor esthetic corrections) 2014-06-23 00:23:40 -07:00
Harald Welte
21f7718e2f v1.4: Connect PA0 to 3V3; pull-up for PA1/PA2 (R25,R26)
PA0, PA1 and PA2 must be high during reset to enter SAM-BA mode.
2014-06-20 15:39:02 +02:00
Harald Welte
e24db8d2b4 Schematic: Make sure PA0 to PA2 are high on power-up
any other level is interfering with SAM-BA operation.  This fixes
the PA0=GND bug in the previous v1.3 version.
2014-06-20 09:44:09 +02:00
Harald Welte
b8d4927137 mini-UICC-reverse: re-generate gerber and add outline GBR 2014-04-30 20:27:36 +02:00
Harald Welte
e179a32048 add PCB design of mini-UICC (original and reverse) adapters 2014-04-26 09:37:22 +02:00
Harald Welte
bea975a05d add datasheet of SPI flash component mounted on recent boards
At some point during v1.2p production, we switched from the S25FL016
to the S25FL032P SPI flash model.  v1.3 all have that flash (so far).
2013-11-16 10:41:48 +01:00
Harald Welte
2aed3f177b simtrace 1.3: move point of origin to lower left corner of PCB 2013-11-11 15:30:59 +01:00
Kevin Redon
e9e54e8d80 merge 2013-10-28 11:15:44 +01:00
Kevin Redon
976b0a0a9f BOM corrected (sorted by value) and reformated 2013-10-28 11:00:33 +01:00
Harald Welte
c5b69fb194 re-add BOM spreadsheet with updated v1.3 components 2013-10-27 18:54:45 +01:00
Kevin Redon
ab6f2d1a19 MCU pin 48 used to identify v1.3 by putting it to ground (with internal pull-up) 2013-10-27 17:11:29 +01:00
Kevin Redon
b8671cab1f exported fabrication files 2013-10-27 12:49:58 +01:00
Kevin Redon
99b90117ab new components placed and routed 2013-10-27 12:19:55 +01:00
Kevin Redon
f03312679e MBR0530 pin numbers corrected 2013-10-27 12:17:14 +01:00
Kevin Redon
276f58ba54 new KiCAD layout format, silkscreen refdes 0.5mm, text 0.75mm, new components loaded 2013-10-27 11:43:33 +01:00
Kevin Redon
d62ac311d2 set footprints to symbols 2013-10-27 11:41:41 +01:00
Kevin Redon
b12dd78254 exported v1.3 netlist 2013-10-27 11:40:21 +01:00
Kevin Redon
ee65e36d5c v1.3 modifications: replaced IC switch with FPF2109, added schottky and pull-down resistors 2013-10-27 11:39:42 +01:00
Kevin Redon
1b9c77bfd9 added FPF210X symbol to library 2013-10-27 11:37:38 +01:00
Harald Welte
eee3243dda add GEDA and gerber data for microSIM (3FF) adapter cable
Original by Kevin Redon, layout improvements by myself.
2013-06-12 18:41:21 +02:00
Holger Hans Peter Freyther
68ae3e3d0f usermanual: Document the serial console settings 2012-11-10 08:58:36 +01:00
Harald Welte
067dad1ae3 import v1.2p release schematics (pdf) and gerber 2012-05-20 01:31:11 +02:00
Harald Welte
4f0bebb1f9 Mark IC5 as "do not place" (VCC_Forward) as it doesn't work anyway
If the LDO is switched off, then even if we try to forward power from
the phone to the SIM, the current will sink inside the LDO (no reverse
current protection).
2012-05-19 22:02:35 +02:00
Kevin Redon
6dcf692dfa RST_PHONE pulldown added on PCB 2012-05-18 19:30:06 +02:00
Harald Welte
2590ed2f5b Add R23 (pull-up for !SIM_RST signal)
While the SAM7 has an internal pull-up, this is of no use if the bus
switch input is left open and collects noise resulting in bogus nRST
interrupts.
2012-05-17 16:15:10 +02:00
Kevin Redon
1c82a64101 v1.2p fabrication exported 2012-05-16 19:52:14 +02:00
Kevin Redon
f0bf11b541 C14 change to 4.7uF 0805, silkscreen improved, more space for JTAG 2012-05-16 13:09:38 +02:00
Kevin Redon
436872bb86 DRC rules violations corrected 2012-05-15 20:30:52 +02:00
Harald Welte
2ebce55aa4 SIMtrace: Improve PCB routing of GND, 3V3 and VCC traces
We have to make sure the impedance of the supply lanes is not too high.
Particularly bad was passing GND in 0.2mm under several resistors before
even reaching the LDO from the USB socket.

This attempts to address the major issues.  Also, the input capacitor is
moved closer to the LDO once again
2012-05-15 11:20:41 +02:00
Holger Hans Peter Freyther
203312eb41 issues: Add a new issue and reword the old one 2012-04-07 13:12:15 +02:00
Holger Hans Peter Freyther
cc4fa2571c wireshark: Mention that our patch has been upstreamed
Starting with Wireshark 1.7.1 we will not need to patch wireshark
anymore.
2012-04-07 13:01:33 +02:00
Holger Hans Peter Freyther
fe56d0df14 firmware: Point to the wiki for links about toolchains. 2012-04-07 12:37:19 +02:00
Holger Hans Peter Freyther
adf48db1b3 usermanual: Obey the docbook schema for xmlto
dblatex was more forgiving, add missing tags to make xmlto happy
2012-04-07 11:39:07 +02:00
Harald Welte
7e2c289d2e production version of SIM-SAM adapter 2012-03-16 08:52:00 +01:00
Harald Welte
ea3e3d70b8 the wireshark patch for SIM dissection has been merged mainline 2012-02-29 23:30:29 +01:00
Harald Welte
96923e77f1 simadapter: proper naming of components 2012-02-18 16:48:47 +01:00
Harald Welte
5708ca8304 add SAM-to-FPC-adapter 2012-02-18 16:48:06 +01:00
Harald Welte
b14d0ad279 simtrace: Add print-out of PPS (Fi/Di change).
simtrace firmware 4f7ca20bf40b911c035264d86ef0359d20e7ac88 and later
includes an indication of PPS-induced Fi/Di changes.  We now print
the such indications to the user.
2012-02-12 15:37:14 +01:00
Martin Paljak
e1bed6d14b apdu_split: correctly handle Le=00 which means 256. 2012-01-25 18:44:38 +01:00
Holger Hans Peter Freyther
4885038690 usermanual: Update with new packages, v1.1p and v0.4 firmware 2012-01-11 11:48:56 +01:00
Holger Hans Peter Freyther
a83492aac6 manual: Update installation for more recent distributions 2012-01-11 11:48:56 +01:00
Kevin Redon
bf8fda49c8 hw: sheet reorganized 2011-12-29 08:22:08 +01:00
Kevin Redon
4aca2c0ac4 hw: power sources path corrected 2011-12-29 08:11:06 +01:00
Kevin Redon
6db07c8a66 hw: +1.8V output corrected, as it does not exist 2011-12-26 13:45:14 +01:00
Kevin Redon
6a28f23265 hw: input voltage attached to ADC, so to measure max SIM voltage output 2011-12-26 13:39:45 +01:00
Kevin Redon
678029c527 hw: only 2 adjustable LDOs are used. 1x3.3v for CPU, 1 for the SIM 2011-12-26 13:01:44 +01:00
Kevin Redon
c20a5599dc hw: power selector for phone removed. only VCC_PHONE is needed 2011-12-26 12:24:30 +01:00
Kevin Redon
4edfab2e1d hw: Rakefile tries to guess gEDA scheme directory 2011-12-22 09:55:01 +01:00
Kevin Redon
9ab3079cbb Merge branch 'master' of git.osmocom.org:simtrace 2011-12-21 15:54:55 +01:00
Harald Welte
4bd25ce274 FFC: add edges of stiffener to Eco1 layer 2011-12-15 12:02:23 +01:00
Holger Hans Peter Freyther
5f9f38378b main: Move code around to let the SIMtrace keep running...
Re-open the USB device, reset the state... handle reconnects of
the device.
2011-12-14 15:23:27 +01:00
Holger Hans Peter Freyther
54683c7b8f main: Re-initialize the APDU split method when we enter the main_loop
Make sure we forget the current state of the APDU splitter when we
re-enter the mainloop of the application.
2011-12-14 15:23:26 +01:00
Holger Hans Peter Freyther
943d7d28dc main: Move the mainloop into a separate function
Prepare to have the application wait for the USB device to come
back. This will be done by moving the code around and then having
a simple for loop.
2011-12-14 15:23:26 +01:00
Harald Welte
56b8045e67 add nicely rendered schematics for v1.0p and v1.1p 2011-12-14 15:19:41 +01:00
Harald Welte
395633e367 FFC: add "sysmocom" text on copper layer of all four adapters 2011-12-14 15:12:09 +01:00
Kevin Redon
092bc344a5 hw: LDO documented 2011-12-08 14:40:29 +01:00
Kevin Redon
1da28c2c5d hw: pdf removed. use the rakefile to generate it 2011-12-08 14:32:41 +01:00
Kevin Redon
6b07b4c16b hw: 3variables LDOs TC1071 used for 1.8V,3.0V,3.3V 2011-12-07 16:46:55 +01:00
Kevin Redon
cd9c804f1a hw: SIM card is smaller (14.9mm instead of 15mm) to better fit in the slot 2011-12-07 14:40:51 +01:00
Kevin Redon
2b9d0c26a1 hw: fabrication output generated 2011-12-06 00:39:30 +01:00
Kevin Redon
9fb2dd51e8 hw: LDO changed(now using multiple TP1071), PWR lines remaned according to classes 2011-12-01 18:07:00 +01:00
Kevin Redon
945f0daa51 hw: SIM FFC cables gerber exported. only ppa/paxer kicad could open pcb \!\!\! 2011-11-29 09:47:11 +01:00
Kevin Redon
228f825efc hw: part information added 2011-11-22 11:58:16 +01:00
Kevin Redon
941945837f hw: Rakefile can check component properties 2011-11-21 10:38:06 +01:00
Kevin Redon
730ae7b46c hw: components have now part description 2011-11-21 10:14:13 +01:00
Kevin Redon
b1c38515fc hw: kicad schema remove, geda rakefile builds the schema. version set to v1.5 (to go up to v2.0) 2011-11-17 12:18:18 +01:00
Kevin Redon
664c813540 datasheet folder removed: too many new datasheets used for SIMtrace v2, takes to much space in git, is under copyright 2011-11-14 20:52:01 +01:00
Kevin Redon
3d41a14f66 hw: translator added 2011-11-14 11:37:28 +01:00
Kevin Redon
4ce08fe4a9 hw: power selector implemented (demultiplexer + inverer + power switch) 2011-11-13 22:06:01 +01:00
Kevin Redon
923265e4f9 hw: inverted pin name corrected 2011-11-13 17:51:55 +01:00
Kevin Redon
2226f5aaeb hw: power switch replaced: FPF2005 to FPF2300 2011-11-13 17:50:54 +01:00
Kevin Redon
894f957bb0 hw: LDO LP2966 replaces AP7332, +1.8V from LDO is used for AT91SAM3S VDDCORE/VDDPLL instead of VDDOUT 2011-11-13 15:30:14 +01:00
Kevin Redon
1d448c7687 hw: CB3Q3244.sym renamed 2011-11-13 15:09:16 +01:00
Kevin Redon
4434a44e2c hw: VPP connected throug bus switch 2011-11-06 00:18:01 +01:00
Kevin Redon
9eeaa8a507 schema boxes, cb3q3244 redraw more schematic, uSD slot added, rakefile support adding version 2011-11-06 00:14:26 +01:00
Kevin Redon
14fe95fb9d Merge branch 'master' of git.osmocom.org:simtrace 2011-11-05 21:55:17 +01:00
Kevin Redon
88a018b3e2 hw: sysmocom added to copper, gerber rendered 2011-11-05 21:30:26 +01:00
Kevin Redon
e2ae9ddbde hw: solder mask between at91sam7s added 2011-11-05 19:06:28 +01:00
Kevin Redon
e3e4d3a783 VPP connected through bus switch 2011-11-05 18:47:04 +01:00
Kevin Redon
776b703b7e +1.8V line enlarged on C12, C15, C16. not possible on C19 2011-11-03 20:53:43 +01:00
Kevin Redon
2188a0bccb footprint refreched, cap near LDO 2011-11-03 20:38:04 +01:00
Kevin Redon
e27231b676 ftdi 3.3v cut in schema 2011-11-01 10:20:53 +01:00
Harald Welte
5ea4cd2771 simffc: make sure PCB edges really are on the edge, not on Eco2 layer 2011-10-31 22:13:49 +01:00
Kevin Redon
75890af814 cap placed near to CPU, some tracks redrawn 2011-10-26 14:09:34 +02:00
Kevin Redon
85ef0105b9 switched from KiCAD to gEDA (scriptable), SAM3S replaces SAM7S, no PLLRC required, 2.2uF cap replaces 1uF for less different components, uSD slot replaces flash 2011-10-26 14:05:18 +02:00
Holger Hans Peter Freyther
7bb1977810 doc: Use the highlighted picture from Myonium for TEST 2011-10-09 19:40:27 +02:00
Holger Hans Peter Freyther
d568a61aba doc: Comment from Myonium for other modes 2011-10-09 19:33:22 +02:00
Holger Hans Peter Freyther
61dcdc01bc doc: A small note on using DFU to update the firmware 2011-10-09 09:49:19 +02:00
Holger Hans Peter Freyther
e3e2e85a15 doc: Still two (maybe it is the same) firmware bug
Remove the ATR issue as Harald has fixed it, we still have the USB 3.0
and OSX enumeration issue.
2011-10-08 23:51:56 +02:00
Holger Hans Peter Freyther
ec50d509ad doc: Write a bit about programming using the SAM7 Utility 2011-10-08 23:46:34 +02:00
Holger Hans Peter Freyther
81ed5bce33 doc: Introduce a chapter on the firmware
Begin to document how to get the firmware, how to build it, how to
flash it, how to hack on it. Some parts are not there yet.
2011-10-08 15:25:53 +02:00
Holger Hans Peter Freyther
c6310b9281 docs: Move the '.' into the paragraph, fixes a jade error. 2011-10-08 15:02:08 +02:00
Holger Hans Peter Freyther
2daf5ca4cd wireshark: Add one more missing file 2011-08-16 18:11:55 +02:00
Kevin Redon
5c1f1ee9df Merge branch 'master' of git.osmocom.org:simtrace 2011-08-15 18:29:16 +02:00
Holger Hans Peter Freyther
d241286a35 doc: Document the planned but missing modes 2011-08-15 13:23:14 +02:00
Holger Hans Peter Freyther
58285d4e19 doc: Rename using to using_sniff to add more using mode 2011-08-15 13:16:32 +02:00
Holger Hans Peter Freyther
0b05b6bd0d doc: Add ... to indicate omitted output 2011-08-15 13:16:16 +02:00
Holger Hans Peter Freyther
e5a98e5b79 doc: Document building wireshark 2011-08-15 13:12:34 +02:00
Holger Hans Peter Freyther
e3fb596c64 doc: Use the FTDI wording from the wiki 2011-08-15 13:06:02 +02:00
Holger Hans Peter Freyther
7e582473c0 wireshark: Add the sim.c file as well 2011-08-15 12:07:12 +02:00
Holger Hans Peter Freyther
c960a25849 host: Pass all modules to one pkg-config invocation
Invoke pkg-config only once per command, makes the lines a
bit shorter as well.
2011-08-15 11:54:02 +02:00
Holger Hans Peter Freyther
a496d88a79 wireshark: Add a patch that applies to the stable 1.6 branch 2011-08-15 11:53:33 +02:00
Holger Hans Peter Freyther
1bb23171fc doc: Write about the KiCad schematics 2011-08-15 11:32:45 +02:00
Peter Stuge
18ad51fe76 Use libusb-1.0 for USB communication 2011-08-15 10:31:54 +02:00
Peter Stuge
7b76e0ce7c Silence warning: initialization from incompatible pointer type 2011-08-15 10:31:54 +02:00
Peter Stuge
0060806497 Include <stdlib.h> for malloc() and free() 2011-08-15 10:31:54 +02:00
Holger Hans Peter Freyther
a41f102a76 doc: Document the known firmware issues and if they have a workaround 2011-08-14 14:47:21 +02:00
Holger Hans Peter Freyther
2c5d60682f doc: Ask users to disconnect the power at the ftdi connector 2011-08-14 14:37:46 +02:00
Holger Hans Peter Freyther
41cb9903c0 doc: Reformat the text to have a 80 char line limit 2011-08-14 14:36:43 +02:00
Holger Hans Peter Freyther
b230ec61fc doc: Copy Kevin's hardware section into the documentation 2011-08-14 14:36:37 +02:00
Holger Hans Peter Freyther
0c387d5882 doc: Improve wording. Avoid repeating 'This hardware' 2011-08-14 08:21:32 +02:00
Kevin Redon
b3e229729f microSIM footprint added 2011-08-13 15:57:28 +02:00
Kevin Redon
902b6a68f1 microSIM schema created (cpoied from normal SIM) 2011-08-13 15:56:36 +02:00
Kevin Redon
0ce897d341 ftdi vcc disconnected 2011-08-13 13:52:27 +02:00
Kevin Redon
3b942695a9 cap near cpu, routing improved 2011-08-13 13:51:16 +02:00
Harald Welte
9389e50e7a update wireshark patch to work with latest wireshark svn trunk 2011-08-12 14:25:57 +02:00
Harald Welte
29b1190ddc include a copy instead of the symlink 2011-08-12 11:21:24 +02:00
Holger Hans Peter Freyther
d22a14bc29 doc: Document the installation of various things
http://software.opensuse.org/download.html?project=home:zecke23&package=simtrace
comes to rescue to show the binaries and the commands
2011-08-09 18:29:32 +02:00
Holger Hans Peter Freyther
eec6d44a12 doc: Document building from source 2011-08-09 18:16:23 +02:00
Holger Hans Peter Freyther
86323174e2 doc: Add images, add introduction, add usage system 2011-08-09 17:10:38 +02:00
Holger Hans Peter Freyther
ebbc9bef4f usermanual: Start writing some bits about the installation 2011-07-19 23:19:32 +02:00
Holger Hans Peter Freyther
f34b1aa52d simtrace: Add a very simple manpage 2011-07-17 19:17:11 +02:00
Holger Hans Peter Freyther
24ed56588b make: Provide a very simple install target for SIMtrace 2011-07-17 18:07:21 +02:00
Holger Hans Peter Freyther
5953e90599 make: Move the LDFLAGS to the end of the link line for OpenSUSE
The code does not build like this on a OpenSUSE system, it will
not find the libusb and libosmocore library.
2011-07-17 18:05:08 +02:00
Holger Hans Peter Freyther
f1c60623ae misc: Use osmo_hexdump instead of the local variant 2011-07-15 16:09:55 +02:00
Holger Hans Peter Freyther
83e051ce6e main.c: Initialize byte_count with 0. It is never used though. 2011-07-15 15:49:49 +02:00
Kevin Redon
3fc51e7fc5 v1.0p corrected and rendered. BOM updated 2011-07-02 21:01:21 +02:00
Kevin Redon
ba3363e1c0 D2 and D3 now also use STPS340U instead of 1N5819 2011-07-02 19:59:11 +02:00
Kevin Redon
f54394ed28 BOM updated for production 2011-07-02 13:41:47 +02:00
Kevin Redon
34eaeb1684 PS/gerber rendered for production 2011-07-02 13:37:01 +02:00
Kevin Redon
dcf3d0aaed board adapted to new footprints 2011-07-02 13:07:58 +02:00
Kevin Redon
3a4ea6bf43 new footprints select for production in netlist (LED is 0805, schottky is SMB_STPS340U, flash is SO008_wide 2011-07-02 12:51:14 +02:00
Kevin Redon
8872e080df footprints for flash S25FL016A and schottky STPS340U created 2011-07-02 12:42:57 +02:00
Kevin Redon
89d5f8dd33 flash memory S25FL016A replaces SST25VF040B for production. datasheet added 2011-07-02 12:41:55 +02:00
Kevin Redon
415c2c18cf schottky STPS340U replaces MBR0530T1 for production. datasheet added 2011-07-02 12:39:50 +02:00
202 changed files with 159266 additions and 532218 deletions

13
README
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@@ -1,13 +0,0 @@
Osmocom SIMTRACE
======================================================================
(C) 2010 by Harald Welte <laforge@gnumonks.org>
SIMTRACE is a program that can be used for tracing the communication
betewen a phone and the SIM card. More generally, it can trace any
ISO 7816 based smart card interface.
This repository contains a host program 'simtrace' as well as a patch
for wireshark.
The corresponding device firmware can be found in the openpcd.git
repository on git.gnumonks.org.

56
README.md Normal file
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# Osmocom SIMtrace
(C) 2010-2017 by Harald Welte <laforge@gnumonks.org>
SIMTtraceis a program that can be used for tracing the communication
between a phone and the SIM card. More generally, it can trace any
ISO 7816 based smart card interface.
SIMtrace is part of the [Osmocom](https://osmocom.org/) Open Source
Mobile Communications project.
This repository contains a host program 'simtrace' as well as a patch
for wireshark (which is part of mainline wireshark since February 2012)
The corresponding device firmware source code can be found at
<http://git.osmocom.org/openpcd/>
## Homepage
The official homepage of the project is
<https://osmocom.org/projects/simtrace/wiki/>
GIT Repository
--------------
You can clone from the official simtrace.git repository using
git clone https://gitea.osmocom.org/sim-card/simtrace
There is a web interface at <https://gitea.osmocom.org/sim-card/simtrace>
## Documentation
There is a PDF user manual available from
<https://osmocom.org/attachments/download/2139/usermanual.pdf>
Mailing List
------------
Discussions related to simtrace are happening on the
simtrace@lists.osmocom.org mailing list, please see
<https://lists.osmocom.org/mailman/listinfo/simtrace> for subscription
options and the list archive.
Please observe the [Osmocom Mailing List
Rules](https://osmocom.org/projects/cellular-infrastructure/wiki/Mailing_List_Rules)
when posting.
Contributing
------------
Our coding standards are described at
<https://osmocom.org/projects/cellular-infrastructure/wiki/Coding_standards>
We us a e-mail based patch submission/review process on the
above-mentioned mailing list for contributions.

23
contrib/jenkins.sh Executable file
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@@ -0,0 +1,23 @@
#!/bin/sh -e
TOPDIR="$(realpath "$(dirname "$0")/..")"
if ! [ -x "$(command -v osmo-build-dep.sh)" ]; then
echo "Error: missing scripts from osmo-ci.git in PATH!"
exit 2
fi
set -x
osmo-clean-workspace.sh
export deps="$TOPDIR/deps"
export inst="$deps/install"
export PKG_CONFIG_PATH="$inst/lib/pkgconfig:$PKG_CONFIG_PATH"
export LD_LIBRARY_PATH="$inst/lib"
mkdir -p deps
osmo-build-dep.sh libosmocore "" '--disable-doxygen'
cd "$TOPDIR"/host
$MAKE clean
$MAKE

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@@ -1,8 +1,90 @@
<?xml version="1.0" encoding="UTF-8"?>
<chapter id="chapter_building">
<title>Getting and Building the Software</title>
<section id="building_dependencies">
<title>Installing Dependencies</title>
<para></para>
<section id="building_intros">
<title>Building software</title>
<para>There are three parts that can be built. It is the firmware
for the SIMtrace hardware, the SIMtrace software and the modified
version of wireshark. All of these have different source trees and
dependencies.</para>
</section>
<section id="building_simtrace">
<title>Building SIMtrace</title>
<section id="libosmocore">
<title>Building the Osmocom libosmocore library</title>
<screen>
$ <command>git</command> clone https://gitea.osmocom.org/osmocom/libosmocore
$ <command>cd</command> libosmocore
$ <command>autoreconf</command> --install --force
$ <command>./configure</command>
$ <command>sudo</command> <command>make</command> install
</screen>
</section>
<section id="libusb">
<title>Installing libusb</title>
<para>You will need to install the libusb header files
to be able to compile <command>simtrace</command>.</para>
</section>
<section id="simtrace">
<title>Building <command>simtrace</command></title>
<screen>
$ wget https://api.opensuse.org/public/source/home:zecke23/simtrace/simtrace_0.0.1.tar.gz
$ tar xzf simtrace_0.0.1.tar.gz
$ cd simtrace-0.0.1
$ PKG_CONFIG_PATH=/usr/local/lib/pkgconfig make
cc `pkg-config --cflags libosmocore` -o main.o -c main.c
cc `pkg-config --cflags libosmocore` -o usb_helper.o -c usb_helper.c
cc `pkg-config --cflags libosmocore` -o usb.o -c usb.c
cc `pkg-config --cflags libosmocore` -o apdu_split.o -c apdu_split.c
cc -o simtrace main.o usb_helper.o usb.o apdu_split.o -lusb `pkg-config --libs libosmocore` -losmocore
</screen>
</section>
</section>
<section id="building_wireshark">
<title>Building Wireshark</title>
<para>SIMtrace provides a patch against <command>wireshark</command>
version 1.6. It is the easiest to checkout a copy using the 1.6 branch
of wireshark and applying the <filename>simcard.patch</filename> on top
of it. And then use the usual way of building wireshark</para>
<section id="getting_wireshark">
<title>Getting Wireshark</title>
<screen>
$ svn co https://anonsvn.wireshark.org/wireshark/trunk-1.6 wireshark-1.6
...
A wireshark-1.6/isprint.h
U wireshark-1.6
Checked out revision 38543.
</screen>
</section>
<section id="getting_simcard.patch">
<title>SIMCard patch</title>
<para>You will need to download and apply the patch.</para>
<screen>
$ cd wireshark-1.6
$ wget http://cgit.osmocom.org/cgit/simtrace/tree/wireshark/simcard-for-wireshark-1.6.patch
$ cat ../simcard-for-wireshark-1.6.patch | patch -p 0
patching file epan/dissectors/packet-gsm_sim.c
patching file epan/dissectors/packet-gsmtap.c
patching file epan/dissectors/Makefile.common
</screen>
</section>
<section id="building_and_installing">
<title>Building and Installing</title>
<screen>
$ autoreconf --install
$ ./configure
$ make
...
$ sudo ./wireshark
</screen>
</section>
</section>
</chapter>

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<?xml version="1.0" encoding="UTF-8"?>
<chapter id="chapter_firmware">
<title>Getting and Building the Firmware</title>
<section id="building_fw_intro">
<title>Introduction</title>
<para>The Firmware is the Software that is running on the
Microcontroller of the SIMtrace hardware. The Firmware itself
consists out of a couple of components for different parts of
the system. Besides the source code for the firmware you will
also need to have an ARM Cross-Compile Toolchain, a copy of the
SAM7 utilities to initially program the device or recover from
a fatal error and dfu-util to update the main part of the firmware
using the Device Firmware Update (DFU) mode.</para>
</section>
<section id="getting_a_toolchain">
<title>Getting a Toolchain</title>
<para>The toolchain needs to include a GCC newer than 3.4
and it may not be an EABI toolchain. EABI toolchains fail to properly
link the SIMtrace binary. You can easily build a toolchain yourself
or use one of the known working pre-built ones. Please see the
<ulink url="http://bb.osmocom.org/trac/wiki/toolchain">SIMtrace wiki</ulink>
for more information about getting a toolchain.
</para>
</section>
<section id="getting_the_firmware">
<title>Getting and Building the Firmware</title>
<para>The SIMtrace firmware is based on the OpenPCD RFID Reader Firmware and the
SIMtrace firmware code is located in the OpenPCD repository. You can use the
<command>git</command> to clone the repository.
<screen>
$ git clone https://gitea.osmocom.org/sim-card/openpcd
</screen>
</para>
<para>The firmware consists out of two separate binaries that will be concatted
and flashed into the NOR flash of the microcontroller. The main part is the dfu
program that will handle basic USB functionality and respond to Device Firmware
Update (DFU) requests to allow to update the firmware in the NOR or execute
software in RAM.
<screen>
$ cd openpcd/firmware
$ make -f Makefile.dfu BOARD=SIMTRACE
$ make BOARD=SIMTRACE DEBUG=1 TARGET=main_simtrace
$ cat dfu.bin main_simtrace.bin > main_simtrace.samba
$ cd ../..
</screen></para>
</section>
<section id="firmware_details">
<title>Firmware Details</title>
<para>
The handling for the DFU part can be found in the <filename>src/dfu</filename>
directory, it also provides low-level USB routines to work with USB Device
Port (UDP). These functions will be called from the main payload.
</para>
<para>The operating system part is in <filename>src/os</filename> it provides
basic hardware control and services to be used by the main application, this
includes USB enumeration, Watchdog programming, running the mainloop, interrupt
dispatching. The main application for SIMtrace can be found in
<filename>src/simtrace</filename> and this includes programming the two USART,
configuring the bus switch according to the mode.
</para>
</section>
<section id="firmware_programming_sam_ba">
<title>Initial Firmware Programming</title>
<para>In case the NOR Flash of the SAM7 Microcontroller is either blank or has
become corrupted the Microcontrollers support entering a mode called SAM-BA which
then allows flashing the device using the <filename>sam</filename> application. The
SAM-BA mode can be easily entered by following the below procedure.</para>
<procedure>
<title>Entering SAM-BA Mode</title>
<step><para>Unplug the SIMtrace Hardware from USB.</para></step>
<step><para>Short TEST to VCC (3.3V) pin by using the Jumper. Leave PA0, PA1, PA2 unconnected.</para></step>
<step><para>Power up the SIMtrace Hardware from USB.</para></step>
<step><para>Wait for 20 seconds.</para></step>
<step><para>Unplug the SIMtrace Hardware from USB.</para></step>
<step><para>Open/Remove the Jumper.</para></step>
</procedure>
<figure>
<title>TEST Jumper</title>
<mediaobject><imageobject>
<imagedata fileref="images/shortTEST.jpg" width="12cm"/>
</imageobject></mediaobject>
</figure>
<note><title>v1.0p/v1.1p Hardware Owners</title>
<para>Sometimes the SAM-BA mode is not entered. This is the case when the
two LEDs are on when powering up the SIMtrace Hardware with the Jumper set.
The reason for this is unknown but there are several workarounds:
<itemizedlist>
<listitem><para>Press the RESET button while powering up.</para></listitem>
<listitem><para>In addition, remove the jumper and put it back.</para></listitem>
</itemizedlist>
As soon as the two LEDs go off, the SAM-BA mode is properly entered.
</para>
</note>
<para>The <command>sam</command> application can be compiled to either use libusb or
normal files to program the device, depending on the drivers used you will
need to configure the application one way or another. The programming can then
be done using the below command.
<screen>
$ ./sam7 --exec set_clock --exec unlock_regions --exec "flash ../openpcd/firmware/main_simtrace.samba"
</screen>
<note><title>Silent failures</title>
<para>The <command>sam</command> can silently fail when not finding or being
able to configure the device properly. It is best to enter the interactive mode
by not providing any <command>--exec</command> commands.</para>
</note>
</para>
</section>
<section id="firmware_programming_dfu">
<title>Device Firmware Update</title>
<para>The Device Firmware Update (DFU) part of the firmware will be
booted first, it is checking if a button is active or if the software
reset reason was for DFU and then activates the DFU part or jumps to
the main application. DFU can be activated at any time using
<command>dfu-util</command> on the USB Host.</para>
<para>The <command>dfu-util</command> application might be already
packaged for your distribution, the source code can be found on the
<ulink url="http://dfu-util.gnumonks.org/">dfu-util.gnumonks.org</ulink>
website. To update the main part of the firmware simply do:
<screen>
$ dfu-util -d 16c0:0762 -a0 -D ./main_simtrace.bin -R
</screen></para>
</section>
<section id="firmware_programming_upgrade">
<title>Upgrading to v0.4 Firmware</title>
<para>Upgrading to v0.4 requires flashing both the Bootloader and the
SIMtrace application. The procedure is first to flash the bootloader,
then the SIMtrace application and finally reset the device.
</para>
<screen>
$ dfu-util -d 16c0:0762 -a 1 -D ./dfu.bin
$ dfu-util -d 16c0:0762 -a 0 -D ./main_simtrace.bin
... reset the device
</screen>
</section>
<section id="firmware_serial_console">
<title>Serial Console for debugging</title>
<para>The serial console operates at 115200 bauds with 8n1 and no flow control.</para>
</section>
</chapter>

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@@ -0,0 +1,116 @@
<?xml version="1.0" encoding="UTF-8"?>
<chapter id="chapter_hw">
<title>Hardware Details</title>
<section id="hw_design">
<title>HW Design</title>
<para>The Free Software KiCAD EDA was used to design the
hardware and can be used to look at the schematics and the
PCB routing. The hardware design can be found in the git
repository of the SIMtrace sources. For the v1.0 hardware
you will have to look at the v1.0_production branch.
</para>
</section>
<section id="pcb_populated">
<title>Populated PCB</title>
<para>The version v1.0p is the first production that had an
automatic SMT run. Due some production issues the labeling of
components didn't make it to the PCB but can be found in this
manual. The difference between the v1.0 and v1.0p hardware is
in the footprint of some components to utilize the existing
stock of the factory. This was mostly done for the LED and the
shottky diodes.</para>
<figure><title>SIMtrace v1.0 PCB</title>
<mediaobject>
<imageobject>
<imagedata fileref="images/simtrace_hw.jpg" width="15cm"/>
</imageobject>
<textobject><phrase>SIMtrace v1.0 PCB</phrase></textobject>
</mediaobject>
</figure>
</section>
<section id="pcb_surface">
<title>PCB Surface</title>
<para>
<figure><title>SIMtrace v1.0 Surface</title>
<mediaobjectco>
<imageobjectco>
<areaspec id="surface" units="calspair">
<area linkends="link_usb" coords="8800,0 8800,6100" id="usb"/>
<area linkends="link_serial" coords="8800,7000 8800,8000" id="serial"/>
<area linkends="link_debug" coords="8800,9000 8800,9500" id="debug"/>
<area linkends="link_jtag" coords="5000,8900 5000,9000" id="jtag"/>
<area linkends="link_bt1" coords="8900,0 9100,3500" id="bt1"/>
<area linkends="link_ffc" coords="500,3000 700,9000" id="ffc"/>
<area linkends="link_sim" coords="500,500 700,2000" id="sim"/>
<area linkends="link_reset" coords="200,9000 500,9000" id="reset"/>
<area linkends="link_bootloader" coords="1700,9000 1900,9000" id="bootloader"/>
<area linkends="link_test" coords="6500,8700 7000,8900" id="test"/>
<area linkends="link_erase" coords="7100,8700 7600,8900" id="erase"/>
</areaspec>
<imageobject>
<imagedata fileref="images/simtrace_surface.png" width="15cm" />
</imageobject>
<calloutlist>
<callout arearefs="usb" id="link_usb">
<para>USB: USB mini-B connector. The main connector. The
host software communicates (sniffing,...) through USB with
the board. It can also be used to flash the micro-controller
(using DFU).</para>
</callout>
<callout arearefs="serial" id="link_serial">
<para>serial: 2.5 mm jack serial cable, as used by osmocomBB
port used to debug the device (printf goes there).</para>
</callout>
<callout arearefs="debug" id="link_debug">
<para>debug (P3): same as serial, but using the FTDI
serial cable. It is recommended to cut the voltage wire of
the 6pin FTDI connector before plugging the cable into the
simtrace.
</para>
</callout>
<callout arearefs="jtag" id="link_jtag">
<para>jtag (P1): JTAG 20 pin connector to do hardware
assisted debugging.</para>
</callout>
<callout arearefs="bt1" id="link_bt1">
<para>BT1: battery connector (4.5-6V DC). normally the
USB provides power, but the battery port can be used
for autonomous use of SIMtrace. The sniffing can be saved
in the flash (U1).</para>
</callout>
<callout arearefs="ffc" id="link_ffc">
<para>FFC_SIM (P3): to connect the flat flexible cable with
SIM end for the phone.</para>
</callout>
<callout arearefs="sim" id="link_sim">
<para>SIM (P4): put your SIM in there (instead of in the
phone)</para>
</callout>
<callout arearefs="reset" id="link_reset">
<para>reset (SW1): to reset the board (not erasing the
firmware). If your are too lazy to unplug and re-plug
the USB.</para>
</callout>
<callout arearefs="bootloader" id="link_bootloader">
<para>bootloader (SW2): used to start the bootloader so
to flash the device using DFU. press when plugging in
the USB.</para>
</callout>
<callout arearefs="test" id="link_test">
<para>test (JP1): short circuit using a jumper to flash
using SAM-BA.</para>
</callout>
<callout arearefs="erase" id="link_erase">
<para>erase (JP2): short circuit using a jumper to erase
completely erase the firmware.</para>
</callout>
</calloutlist>
</imageobjectco>
</mediaobjectco>
</figure>
</para>
</section>
</chapter>

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<?xml version="1.0" encoding="UTF-8"?>
<chapter id="chapter_installation">
<title>Installation</title>
<para><application>SIMtrace</application> will need a patched version of
<application>wireshark</application> and the <command>simtrace</command>
host utility to fully operate. The installation might be possible from
binary packages or will require building from source. The following
sections provide some hints how to achieve this on the various Linux
distributions. All these operations must be executed as root.</para>
<note>
<title>Wireshark Patches</title>
<para>The SIMtrace patch has been upstreamed. Wireshark 1.7.1 was released
on April the 6th 2012 and is the first development release to support SIMtrace
out of the box. Wireshark 1.8 will be the first stable version.
</para>
</note>
<section id="install_ubuntu_natty">
<title>Installation Ubuntu Natty, Ubuntu Oneiric</title>
<para>Ubuntu Natty and Oneiric users can use the holger+lp/osmocom PPA to install
<application>SIMtrace</application> and upgrade wireshark. The PPA needs to
be added to the system, the package database needs to be refreshed
and the applications can be installed afterwards.</para>
<screen>
$ <command>sudo</command> <command>add-apt-repository</command> ppa:holger+lp/osmocom
[sudo] password for username:
Executing: gpg --ignore-time-conflict --no-options --no-default-keyring --secret-keyring /etc/apt/secring.gpg --trustdb-name /etc/apt/trustdb.gpg --keyring /etc/apt/trusted.gpg --primary-keyring /etc/apt/trusted.gpg --keyserver hkp://keyserver.ubuntu.com:80/ --recv 84C86214C00BAF820F43585CCABF944FA2AD19FA
gpg: requesting key A2AD19FA from hkp server keyserver.ubuntu.com
gpg: Total number processed: 1
gpg: unchanged: 1
</screen>
<para>The next step is to update the package database and install or upgrade
the <application>wireshark</application> application.</para>
<screen>
$ <command>sudo</command> <command>apt-get</command> update
...
$ <command>sudo</command> <command>apt-get</command> install wireshark simtrace
...
</screen>
<note><para>The wireshark will only be installed if it is newer than the version
provided by Ubuntu. Please verify that the above command installed a version
coming from the PPA.</para>
</note>
</section>
<section id="install_opensuse">
<title>Installation OpenSUSE</title>
<para>The installation on OpenSUSE uses zypper. The repository must be added
via the <command>zypper</command> application and then the binary packages
can be installed.</para>
<section>
<title>openSUSE 11.3</title>
<screen>
$ <command>zypper</command> addrepo http://download.opensuse.org/repositories/home:/zecke23/openSUSE_11.3/home:zecke23.repo
$ <command>zypper</command> refresh
$ <command>zypper</command> install wireshark simtrace
</screen>
</section>
<section>
<title>openSUSE 11.4</title>
<screen>
$ <command>zypper</command> addrepo http://download.opensuse.org/repositories/home:/zecke23/openSUSE_11.4/home:zecke23.repo
$ <command>zypper</command> refresh
$ <command>zypper</command> install wireshark simtrace
</screen>
</section>
<section>
<title>openSUSE 12.1</title>
<screen>
$ <command>zypper</command> addrepo http://download.opensuse.org/repositories/home:/zecke23/openSUSE_11.4/home:zecke23.repo
$ <command>zypper</command> refresh
$ <command>zypper</command> install wireshark simtrace
</screen>
</section>
</section>
<section id="install_fedora">
<title>Installation Fedora</title>
<section>
<title>Fedora 14</title>
<screen>
$ cd /etc/yum/repos.d/
$ wget http://download.opensuse.org/repositories/home:zecke23/Fedora_14/home:zecke23.repo
$ yum install wireshark simtrace
</screen>
</section>
<section>
<title>Fedora 15</title>
<screen>
$ cd /etc/yum/repos.d/
$ wget http://download.opensuse.org/repositories/home:zecke23/Fedora_15/home:zecke23.repo
$ yum install wireshark simtrace
</screen>
</section>
<section>
<title>Fedora 16</title>
<screen>
$ cd /etc/yum/repos.d/
$ wget http://download.opensuse.org/repositories/home:zecke23/Fedora_16/home:zecke23.repo
$ yum install wireshark simtrace
</screen>
</section>
</section>
<section id="install_centos">
<title>Installation CentOS</title>
<section>
<title>CentOS 5</title>
<screen>
$ cd /etc/yum/repos.d/
$ wget http://download.opensuse.org/repositories/home:zecke23/CentOS_CentOS-5/home:zecke23.repo
$ yum install wireshark simtrace
</screen>
</section>
<section>
<title>CentOS 6</title>
<screen>
$ cd /etc/yum/repos.d/
$ wget http://download.opensuse.org/repositories/home:zecke23/CentOS_CentOS-6/home:zecke23.repo
$ yum install wireshark simtrace
</screen>
</section>
</section>
<section id="install_mandriva">
<title>Mandriva</title>
<section>
<title>Mandriva 2010.1</title>
<screen>
$ urpmi.addmedia home:zecke23 http://download.opensuse.org/repositories/home:zecke23/Mandriva_2010.1/
$ urpmi.update -a
$ urpmi wireshark simtrace
</screen>
</section>
<section>
<title>Mandriva 2011</title>
<screen>
$ urpmi.addmedia home:zecke23 http://download.opensuse.org/repositories/home:zecke23/Mandriva_2011/
$ urpmi.update -a
$ urpmi wireshark simtrace
</screen>
</section>
</section>
<section id="installation_from_source">
<title>Installation from Source</title>
<para>Please see the <xref linkend="chapter_building"/></para>
</section>
</chapter>

View File

@@ -2,7 +2,42 @@
<chapter id="chapter_introduction">
<title>Introduction</title>
<section id="intro_overview">
<title>History</title>
<para>SIMtrace was created out of necessity. Harald Welte wanted
to see the communication between a GSM Mobile Station (or
what we call a cellphone) and the SIM. He was not able to
find an existing solution, or the existing ones had mayor
drawbacks that made using them very time consuming and slow.
The Atmel AT91SAM7 came to the rescue. This microcontroller
has hardware support for the ISO7816 T0/T1 Smart Card
specification. We can connect the external clock to the UART
and are able to read bytes coming and going to the SIM.
The next step in the project was taken by Kevin Redon
that started to modify an existing AT91SAM7 design, started
to use the Free Software KiCAD CAD Software. In 2011 the project
went from having Schematics to having routed circuits, prototypes
and the final product. The first production run was in August.</para>
</section>
<section id="intro_picture">
<title>Overview</title>
<para></para>
<para>The setup of SIMtrace consists out of a Hardware and a
Software part. The SIM card needs to be put into the SIMtrace
Hardware, the flex cable needs to be connected to the SIMtrace
Hardware and the SIM end needs to be placed in the SIM socket
of the phone. The SIMtrace hardware can be seen as a USB device
from the host, the SIMtrace software will try to find this device
and claim it. The SIMtrace software will receive packets from the
SIMtrace hardware and can forward them using the GSMTAP protocol
to the IANA assigned GSMTAP port (4729). A modified version of Wireshark
can be used to analyze the data.</para>
<figure><title>Schematic Overview</title>
<mediaobject>
<imageobject>
<imagedata fileref="images/setup_overview.png" width="6cm"/>
</imageobject>
<textobject><phrase>SIMtrace being connected</phrase></textobject>
</mediaobject>
</figure>
</section>
</chapter>

View File

@@ -1,20 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<chapter id="chapter_using">
<title>Sniffing your SIM</title>
<section id="launching_simtrace">
<title>Launching SIMtrace</title>
<para></para>
<screen>
$ <command>simtrace</command>
</screen>
</section>
<section id="launching_wireshark">
<title>Launching Wireshark</title>
<para></para>
<screen>
$ <command>wireshark</command>
</screen>
</section>
</chapter>

View File

@@ -0,0 +1,84 @@
<?xml version="1.0" encoding="UTF-8"?>
<chapter id="chapter_sniff">
<title>Sniffing your SIM</title>
<section id="hw_setup">
<title>Connecting your device</title>
<para>You will need to put your SIM into the SIMtrace hardware, connect
one of the four flex cables to the SIMtrace hardware, put the other side
into the SIM socket of your phone. Use USB to connect the SIMtrace hardware
to the PC. On your PC you should be able to see the USB device now.</para>
<figure><title>Connecting the SIMtrace Hardware</title>
<mediaobject>
<imageobject>
<imagedata fileref="images/simtrace_hw_setup.png" width="15cm"/>
</imageobject>
<textobject><phrase>SIMtrace being connected</phrase></textobject>
</mediaobject>
</figure>
</section>
<section id="launching_simtrace">
<title>Launching SIMtrace</title>
<screen>
$ <command>./simtrace</command>
simtrace - GSM SIM and smartcard tracing
(C) 2010 by Harald Welte &lt;laforge@gnumonks.org&gt;
</screen>
<para>Launching the <command>simtrace</command> will try to find
the SIMtrace hardware and then try to claim the USB device. The
application will send the received data encapsulated in the GSMTAP
format on localhost and the IANA assigned GSMTAP port.</para>
</section>
<section id="launching_wireshark">
<title>Launching Wireshark</title>
<para>The <command>wireshark</command> application will start a GUI
and given the right permissions you should be able listen to the
localhost interface and filter for the GSMTAP port on 4729. You should
be able to see the decoded messages like in the figure below.</para>
<figure><title>GSMTAP in Wireshark</title>
<mediaobject>
<imageobject>
<imagedata fileref="images/wireshark-sim.png" width="16cm"/>
</imageobject>
<textobject><phrase>SIMtrace sending data</phrase></textobject>
</mediaobject>
</figure>
</section>
<section id="known_firmware_issues">
<title>Known Firmware Issues</title>
<section>
<title>Combined ATR/APDU message</title>
<para>For some cards the firmware does not send an USB message at
the end of the ATR. The ATR and first APDU will be send in one message
and the host utility fails to split APDUs and nothing will be traced.
A band-aid for the firmware exists and can be found on the mailinglist.
</para>
</section>
<section>
<title>Lost bytes</title>
<para>For some new high speed cards the firmware can lose bytes. The
issue appears to be when the received bytes will be copied to the memory
of the USB controller. The workaround is to reduce the size of the buffer.
</para>
</section>
</section>
<section id="other_modes">
<title>Other modes</title>
<para>The hardware is capable to be used as an ordinary card reader,
provide Man-In-The-Middle (MITM) attacks, or operate as a SIM. The
firmware currently does not have support for these modes.</para>
<para>The SIMtrace hardware supports ISO7816 Part 3 T=0/T=1 protocols,
it basically can be used to intercept and analyze any traffic from (ISO7816)
smart cards. This includes SIM cards, Pay TV cards (smart card for CAM),
ATM cards, chip credit card, PKI smart cards, e-passport etc. etc. However
watch out: You have to make your chip card fitting in the "SIM card size"
ID-000 reader or build another adapter.</para>
</section>
</chapter>

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@@ -6,8 +6,11 @@
<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.2//EN"
"http://www.oasis-open.org/docbook/xml/4.2/docbookx.dtd" [
<!ENTITY chapter-introduction SYSTEM "chapters/introduction.xml">
<!ENTITY chapter-using SYSTEM "chapters/using.xml">
<!ENTITY chapter-installation SYSTEM "chapters/installation.xml">
<!ENTITY chapter-hw-details SYSTEM "chapters/hardware_details.xml">
<!ENTITY chapter-using-sniff SYSTEM "chapters/using_sniff.xml">
<!ENTITY chapter-building SYSTEM "chapters/building.xml">
<!ENTITY chapter-firmware SYSTEM "chapters/firmware.xml">
<!ENTITY chapter-appendix SYSTEM "chapters/appendix.xml">
]>
@@ -20,12 +23,37 @@
<authorinitials>z</authorinitials>
<revremark>Initial</revremark>
</revision>
<revision>
<revnumber>0.0.2</revnumber>
<date>14 August 2011</date>
<authorinitials>z</authorinitials>
<revremark>Copy HW Info from the Wiki</revremark>
</revision>
<revision>
<revnumber>0.0.3</revnumber>
<date>15 August 2011</date>
<authorinitials>z</authorinitials>
<revremark>Document building wireshark</revremark>
</revision>
<revision>
<revnumber>0.0.4</revnumber>
<date>8 October 2011</date>
<authorinitials>z</authorinitials>
<revremark>Document Firmware</revremark>
</revision>
<revision>
<revnumber>0.0.5</revnumber>
<date>10 January 2012</date>
<authorinitials>z</authorinitials>
<revremark>Add additional distro packages, mention the v0.4 firmware
update procedure, add some notes of the SAM-BA mode</revremark>
</revision>
</revhistory>
<title>SIMtrace Usermanual</title>
<copyright>
<year>2011</year>
<year>2011-2012</year>
</copyright>
<legalnotice>
@@ -39,8 +67,11 @@
<!-- Main chapters-->
&chapter-introduction;
&chapter-using;
&chapter-installation;
&chapter-hw-details;
&chapter-using-sniff;
&chapter-building;
&chapter-firmware;
&chapter-appendix;
</book>

35
hardware/README Normal file
View File

@@ -0,0 +1,35 @@
here you will find the files related to the hardware aspect of SIMtrace.
the hardware for SIMtrace (1) and SIMtrace 2 is almost the same.
the main difference is the micro-controller.
SIMtrace (1) uses an Atmel AT91SAM7S micro-controller.
This micro-controller has been deprecated for some time and needed to be replaced.
SIMtrace 2 uses am Atmal ATSAM3S.
Because the micro-controller architecture is difference, the firmware has been rewritten from scratch.
The firmware for SIMtrace 2 will not work on SIMtrace boards with AT91SAM7S micro-controllers.
folders
=======
- releases: archives containing schematic and fabrication output of the various SIMtrace versions
- kicad: the source files for the hardware design (schematic and board layout)
- pcd: schematic and fabrication output of the current SIMtrace version
- datasheet: collection of datasheets for parts used by SIMtrace
- geda: an initial trial of redesigning SIMtrace, abandoned
changelog
=========
v1.5
----
updated schematic:
- made more readable
- uses SAM3S micro-controller for SIMtrace 2
- has several parts marked as Do Not Place (DNP) since they are not required anymore by the SAM3S
the board layout is the same as v1.4.
you just need to use the updated BOM with new micro-controller and fewer parts.
see SIMtrace.csv for DNP parts.
the BOM.ods is outdated but still provided some links for the parts.

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hardware/geda/Rakefile Normal file
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require 'rake/clean'
# ==============
# important info
# ==============
target = "simtrace"
version = IO.read("version").chomp
date = Time.now.strftime("%Y-%m-%d")
revision = `git log --pretty=oneline "#{target}.sch" | wc -l`.chomp.to_i
# symbol library for gschem
LIB = "lib/symbols/"
# gEDA scheme
GEDA_SCHEME_DIRS=["/usr/share/gEDA/scheme","/usr/local/gEDA/scheme"].collect{|path| File.directory?(path) ? path : nil}.compact
unless GEDA_SCHEME_DIRS.size==0 then
GEDA_SCHEME_DIR=GEDA_SCHEME_DIRS[0]
else
GEDA_SCHEME_DIR=nil
puts "warning: could not find gEDA scheme directory. can not print schematic"
end
# schema
sch = "#{target}.sch"
# schema with version
vsch = "#{target}_v#{version}.#{revision.to_s.rjust(3,'0')}.sch"
# ================
# helper functions
# ================
# read schema
# return a list of components
def read_sch(path)
# get all symbols
symbols = read_symbols(LIB)
# read schema
text = IO.read(path)
# parse all elements
elements = []
element = {}
block = false
text.each_line do |line|
l = line.chomp
if l=="{" then
block = true
element[:block] = {} unless element[:block]
elsif l=="}" then
block = false
elsif block then
# only take attributes
if l.include?("=") then
k,v = l.split("=")
element[:block][k] = v
end
elsif !block then
elements << element unless element.empty?
element = {}
element[:line] = l
element[:type] = l[0,1]
if element[:type]=="C" then
element[:symbol] = l.split(" ")[-1]
# get the default attributes (if any)
element[:block] = symbols[element[:symbol]].dup if symbols[element[:symbol]]
end
else
raise "don't know how to handle line: #{l}"
end
end
return elements
end
# read the attributes from a symbol
# return { name => value }
# warning: it only get uniq attributes (not multiple slots, ...)
def read_symbol(file)
text = IO.read(file)
symbol = {}
block = false
text.each_line do |line|
l = line.chomp
if l=="{" then
block = true
elsif l=="}" then
block = false
elsif block then
next
elsif l.include?("=") then
name = l.split("=")[0]
value = l.split("=")[1..-1]*"="
symbol[name] = value
else
next
end
end
return symbol
end
# read all symbols
# return a list fo symbols { name => symbol } (see read_symbol)
def read_symbols(folder)
symbols = {}
Dir.entries(folder).each do |file|
next unless file =~ /\.sym$/
symbols[file.split("/")[-1]] = read_symbol(folder+"/"+file)
end
return symbols
end
# =========
# the tasks
# =========
task :default => [:version,:print,:pdf,:install,:check]
desc "set version in schema"
task :version => vsch
CLEAN.include(vsch)
CLOBBER.include("#{target}_*.sch")
desc "print schema (into ps)"
task :print => "#{target}.ps"
CLEAN.include("#{target}.ps")
desc "get printed schema in pdf"
task :pdf => "#{target}.pdf"
CLEAN.include("#{target}.pdf")
desc "put printed schema in output folder"
task :install => "#{target}.pdf" do
mkdir "../pcb/schema" unless File.directory? "../pcb/schema"
cp "#{target}.pdf","../pcb/schema/#{target}.pdf"
end
CLOBBER.include("../pcb/schema/#{target}.pdf")
# every component should have: refdes without ?, device, value,
# footprint, manufacturer, documentation, digikey
task :check => sch do
elements = read_sch(sch)
elements.each do |element|
if element[:type]=="C" then
if element[:block] and element[:block]["refdes"] then
name = element[:block]["refdes"]
name += " (#{element[:block]['device']})" if element[:block]["device"]
puts name+" has no ID" if element[:block]["refdes"].include? "?"
["device","value","footprint","manufacturer","manufacturer-part","documentation","digikey-part"].each do |attribute|
puts name+" has no "+attribute unless element[:block][attribute]
break if element[:block]["footprint"] =~ /^HEADER/ or element[:block]["footprint"] =~ /^JUMPER/
end
end
end
end
end
# ===============
# file processing
# ===============
file vsch => sch do
sh "cp #{sch} #{vsch}"
# on \ is to prevent ruby interpreting it, th other is for sed
# the version
sh "sed -i 's/\\(version=\\)\\$Version\\$/\\1#{version}/' #{vsch}"
# the date
sh "sed -i 's/\\(date=\\)\\$Date\\$/\\1#{date}/' #{vsch}"
# the revision
sh "sed -i 's/\\(revision=\\)\\$Revision\\$/\\1#{revision}/' #{vsch}"
end
file "#{target}.ps" => vsch do
if GEDA_SCHEME_DIR then
sh "gschem -p -o #{target}.ps -s #{GEDA_SCHEME_DIR}/print.scm #{vsch} > /dev/null 2>&1"
else
puts "can not print schematic. gEDA scheme directory missing"
end
end
file "#{target}.pdf" => "#{target}.ps" do
sh "ps2pdf -sPAPERSIZE=a4 #{target}.ps"
end

3
hardware/geda/gafrc Normal file
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@@ -0,0 +1,3 @@
; .sch gEDA configuration file
(define gedasymbols "lib")
(component-library (build-path gedasymbols "symbols"))

3
hardware/geda/gschemrc Normal file
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@@ -0,0 +1,3 @@
; gschem configuration file
(paper-size 11.69 8.27) ; A4
;(output-color "enabled") ; for color postscript output (black background)

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@@ -0,0 +1,17 @@
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}
B 300 0 1100 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 2500 8 10 1 1 0 0 1
refdes=U?
T 300 2700 8 10 0 0 0 0 1
device=74CBTLV3253
T 300 2900 8 10 0 0 0 0 1
description=Dual 1-of-4 multiplexer/demultiplexer
T 300 3100 8 10 0 0 0 0 1
documentation=http://www.nxp.com/documents/data_sheet/74CBTLV3253.pdf

View File

@@ -0,0 +1,40 @@
v 20081231 1
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T 400 350 8 10 1 1 0 4 1
refdes=FB?
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author=Stefan Salewski
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description=Ferrite bead
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numslots=0
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dist-license=GPL
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L 200 100 600 100 3 0 0 0 -1 -1
B 250 175 300 50 3 0 0 0 -1 -1 3 0 45 10 -1 -1
B 250 -25 300 50 3 0 0 0 -1 -1 3 0 45 10 -1 -1

View File

@@ -0,0 +1,720 @@
v 20110115 2
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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T 0 5200 5 10 0 0 180 0 1
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{
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{
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{
T 0 3000 5 10 0 0 180 0 1
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P 4700 1000 4400 1000 1 0 0
{
T 4700 1000 5 10 0 0 180 0 1
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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T 4345 3395 5 10 1 1 0 6 1
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{
T 4700 3200 5 10 0 0 180 0 1
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{
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{
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{
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{
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{
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{
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{
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P 4700 2800 4400 2800 1 0 0
{
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{
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P 4700 5400 4400 5400 1 0 0
{
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{
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{
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P 4700 6200 4400 6200 1 0 0
{
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pinnumber=31
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P 4700 6400 4400 6400 1 0 0
{
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pintype=unknown
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pinlabel=PA7/XIN32/PGMNVALID
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pinnumber=32
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}
P 4700 6000 4400 6000 1 0 0
{
T 4700 6000 5 10 0 0 180 0 1
pintype=unknown
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}
B 300 0 4100 8000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 8100 8 10 1 1 0 0 1
refdes=IC?
T 300 8500 8 10 0 0 0 0 1
device=AT91SAM3SXB
T 300 8700 8 10 0 0 0 0 1
description=Atmel AT91SAM3S1/2/4B microprocessor
T 300 9100 8 10 0 0 0 0 1
footprint=LQFP64
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alt-footprint=QFN64
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documentation=http://www.atmel.com/dyn/resources/prod_documents/doc6500.pdf
T 300 8900 8 10 0 0 0 0 1
manufacturer=Atmel

View File

@@ -0,0 +1,78 @@
v 20110115 2
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{
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pintype=pwr
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T 305 1045 5 10 1 1 0 6 1
pinnumber=5
T 0 1000 5 10 0 0 0 0 1
pinseq=5
}
P 0 700 400 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=in
T 455 695 5 10 1 1 0 0 1
pinlabel=EN1
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pinnumber=4
T 0 700 5 10 0 0 0 0 1
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}
P 0 400 400 400 1 0 0
{
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pintype=in
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pinlabel=EN2
T 305 445 5 10 1 1 0 6 1
pinnumber=3
T 0 400 5 10 0 0 0 0 1
pinseq=3
}
P 2000 1000 1600 1000 1 0 0
{
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pintype=pwr
T 1545 995 5 10 1 1 0 6 1
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pinnumber=6
T 2000 1000 5 10 0 0 0 0 1
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P 2000 700 1600 700 1 0 0
{
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T 1545 695 5 10 1 1 0 6 1
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P 2000 400 1600 400 1 0 0
{
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pintype=pwr
T 1545 395 5 10 1 1 0 6 1
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T 1695 445 5 10 1 1 0 0 1
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}
B 400 200 1200 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1300 8 10 1 1 0 0 1
refdes=IC?
T 400 1900 8 10 0 0 0 0 1
device=AP7332-SOT26
T 400 1700 8 10 0 0 0 0 1
description=dual 300mA LDO voltage regulator
T 400 1500 8 10 0 0 0 0 1
footprint=SOT26
T 500 0 9 10 1 0 0 0 1
LDO AP7332

View File

@@ -0,0 +1,234 @@
v 20091004 2
P 300 900 0 900 1 0 1
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T 300 900 5 10 0 1 0 6 1
pinseq=2
T 325 900 3 10 1 1 0 1 1
pinlabel=VDD
T 300 900 2 10 0 1 0 5 1
pintype=pwr
}
P 300 1200 0 1200 1 0 1
{
T 275 1225 5 10 1 1 0 6 1
pinnumber=4
T 300 1200 5 10 0 1 0 6 1
pinseq=4
T 325 1200 3 10 1 1 0 1 1
pinlabel=GND
T 300 1200 2 10 0 1 0 5 1
pintype=pwr
}
P 300 1500 0 1500 1 0 1
{
T 275 1525 5 10 1 1 0 6 1
pinnumber=6
T 300 1500 5 10 0 1 0 6 1
pinseq=6
T 325 1500 3 10 1 1 0 1 1
pinlabel=GND
T 300 1500 2 10 0 1 0 5 1
pintype=pwr
}
P 300 1800 0 1800 1 0 1
{
T 275 1825 5 10 1 1 0 6 1
pinnumber=8
T 300 1800 5 10 0 1 0 6 1
pinseq=8
T 325 1800 3 10 1 1 0 1 1
pinlabel=GND
T 300 1800 2 10 0 1 0 5 1
pintype=pwr
}
P 300 2100 0 2100 1 0 1
{
T 275 2125 5 10 1 1 0 6 1
pinnumber=10
T 300 2100 5 10 0 1 0 6 1
pinseq=10
T 325 2100 3 10 1 1 0 1 1
pinlabel=GND
T 300 2100 2 10 0 1 0 5 1
pintype=pwr
}
P 300 2400 0 2400 1 0 1
{
T 275 2425 5 10 1 1 0 6 1
pinnumber=12
T 300 2400 5 10 0 1 0 6 1
pinseq=12
T 325 2400 3 10 1 1 0 1 1
pinlabel=GND
T 300 2400 2 10 0 1 0 5 1
pintype=pwr
}
P 300 2700 0 2700 1 0 1
{
T 275 2725 5 10 1 1 0 6 1
pinnumber=14
T 300 2700 5 10 0 1 0 6 1
pinseq=14
T 325 2700 3 10 1 1 0 1 1
pinlabel=GND
T 300 2700 2 10 0 1 0 5 1
pintype=pwr
}
P 300 3000 0 3000 1 0 1
{
T 275 3025 5 10 1 1 0 6 1
pinnumber=16
T 300 3000 5 10 0 1 0 6 1
pinseq=16
T 325 3000 3 10 1 1 0 1 1
pinlabel=GND
T 300 3000 2 10 0 1 0 5 1
pintype=pwr
}
P 300 3300 0 3300 1 0 1
{
T 275 3325 5 10 1 1 0 6 1
pinnumber=18
T 300 3300 5 10 0 1 0 6 1
pinseq=18
T 325 3300 3 10 1 1 0 1 1
pinlabel=GND
T 300 3300 2 10 0 1 0 5 1
pintype=pwr
}
P 300 3600 0 3600 1 0 1
{
T 275 3625 5 10 1 1 0 6 1
pinnumber=20
T 300 3600 5 10 0 1 0 6 1
pinseq=20
T 325 3600 3 10 1 1 0 1 1
pinlabel=GND
T 300 3600 2 10 0 1 0 5 1
pintype=pwr
}
P 2300 900 2600 900 1 0 1
{
T 2325 925 5 10 1 1 0 0 1
pinnumber=1
T 2300 900 5 10 0 1 0 6 1
pinseq=1
T 2275 900 3 10 1 1 0 7 1
pinlabel=VTREF
T 2300 900 2 10 0 1 0 5 1
pintype=io
}
P 2300 1200 2600 1200 1 0 1
{
T 2325 1225 5 10 1 1 0 0 1
pinnumber=3
T 2300 1200 5 10 0 1 0 6 1
pinseq=3
T 2275 1200 3 10 1 1 0 7 1
pinlabel=NTRST
T 2300 1200 2 10 0 1 0 5 1
pintype=io
}
P 2300 1500 2600 1500 1 0 1
{
T 2325 1525 5 10 1 1 0 0 1
pinnumber=5
T 2300 1500 5 10 0 1 0 6 1
pinseq=5
T 2275 1500 3 10 1 1 0 7 1
pinlabel=TDI
T 2300 1500 2 10 0 1 0 5 1
pintype=in
}
P 2300 1800 2600 1800 1 0 1
{
T 2325 1825 5 10 1 1 0 0 1
pinnumber=7
T 2300 1800 5 10 0 1 0 6 1
pinseq=7
T 2275 1800 3 10 1 1 0 7 1
pinlabel=TMS
T 2300 1800 2 10 0 1 0 5 1
pintype=io
}
P 2300 2100 2600 2100 1 0 1
{
T 2325 2125 5 10 1 1 0 0 1
pinnumber=9
T 2300 2100 5 10 0 1 0 6 1
pinseq=9
T 2275 2100 3 10 1 1 0 7 1
pinlabel=TCK
T 2300 2100 2 10 0 1 0 5 1
pintype=out
}
P 2300 2400 2600 2400 1 0 1
{
T 2325 2425 5 10 1 1 0 0 1
pinnumber=11
T 2300 2400 5 10 0 1 0 6 1
pinseq=11
T 2275 2400 3 10 1 1 0 7 1
pinlabel=RTCK
T 2300 2400 2 10 0 1 0 5 1
pintype=io
}
P 2300 2700 2600 2700 1 0 1
{
T 2325 2725 5 10 1 1 0 0 1
pinnumber=13
T 2300 2700 5 10 0 1 0 6 1
pinseq=13
T 2275 2700 3 10 1 1 0 7 1
pinlabel=TDO
T 2300 2700 2 10 0 1 0 5 1
pintype=out
}
P 2300 3000 2600 3000 1 0 1
{
T 2325 3025 5 10 1 1 0 0 1
pinnumber=15
T 2300 3000 5 10 0 1 0 6 1
pinseq=15
T 2275 3000 3 10 1 1 0 7 1
pinlabel=NSRST
T 2300 3000 2 10 0 1 0 5 1
pintype=io
}
P 2300 3300 2600 3300 1 0 1
{
T 2325 3325 5 10 1 1 0 0 1
pinnumber=17
T 2300 3300 5 10 0 1 0 6 1
pinseq=17
T 2275 3300 3 10 1 1 0 7 1
pinlabel=DBGRQ
T 2300 3300 2 10 0 1 0 5 1
pintype=io
}
P 2300 3600 2600 3600 1 0 1
{
T 2325 3625 5 10 1 1 0 0 1
pinnumber=19
T 2300 3600 5 10 0 1 0 6 1
pinseq=19
T 2275 3600 3 10 1 1 0 7 1
pinlabel=DBGACK
T 2300 3600 2 10 0 1 0 5 1
pintype=io
}
B 300 300 2000 3900 3 10 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1300 2250 2 10 1 1 0 4 1
JTAG
T 0 0 0 1 0 0 0 0 1
device=ARMJTAGCONN
T 2350 4250 5 10 1 1 0 0 1
refdes=J?
T 0 0 0 1 0 0 0 0 1
footprint=
T 0 0 0 1 0 0 0 0 1
description=ARM JTAG Connectro (20 pins)
T 0 0 0 1 0 0 0 0 1
numslots=0

View File

@@ -0,0 +1,76 @@
v 20110115 2
L 600 800 500 600 3 0 0 0 -1 -1
L 500 600 400 800 3 0 0 0 -1 -1
L 400 800 600 800 3 0 0 0 -1 -1
L 600 350 400 350 3 0 0 0 -1 -1
L 600 300 400 300 3 0 0 0 -1 -1
V 500 550 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 500 500 500 350 3 0 0 0 -1 -1
L 550 200 550 300 3 0 0 0 -1 -1
L 450 300 450 200 3 0 0 0 -1 -1
L 700 200 550 200 3 0 0 0 -1 -1
L 450 200 300 200 3 0 0 0 -1 -1
L 500 800 500 1000 3 0 0 0 -1 -1
P 1000 200 700 200 1 0 0
{
T 1000 200 5 10 0 0 180 0 1
pintype=io
T 605 -5 5 10 1 1 0 0 1
pinlabel=B
T 800 0 5 10 0 1 0 0 1
pinseq=3
T 800 300 5 10 1 1 0 0 1
pinnumber=3
}
P 500 1300 500 1000 1 0 0
{
T 900 1000 5 10 0 0 180 0 1
pintype=in
T 605 1102 5 10 1 1 0 0 1
pinlabel=\_OE\_
T 1000 1100 5 10 0 1 0 0 1
pinseq=1
T 300 1100 5 10 1 1 0 0 1
pinnumber=1
}
T 0 1300 8 10 1 1 0 0 1
netname=IC?
T 100 1600 8 10 0 0 0 0 1
device=CB3Q3244
T 100 1800 8 10 0 0 0 0 1
description=2x4-bit FET bus switch
P 0 200 300 200 1 0 0
{
T 0 200 5 10 0 0 180 0 1
pintype=io
T 300 -5 5 10 1 1 0 0 1
pinlabel=A
T 100 0 5 10 0 1 0 0 1
pinseq=2
T 100 300 5 10 1 1 0 0 1
pinnumber=2
}
T 100 2000 8 10 0 0 0 0 1
net=GND:10
T 100 2200 8 10 0 0 0 0 1
net=VCC:20
T 100 2400 8 10 0 0 0 0 1
slotdef=1:1,2,18
T 100 2600 8 10 0 0 0 0 1
slotdef=2:1,4,16
T 100 2800 8 10 0 0 0 0 1
slotdef=3:1,6,14
T 100 3000 8 10 0 0 0 0 1
slotdef=4:1,8,12
T 100 3200 8 10 0 0 0 0 1
slotdef=5:19,11,9
T 100 3400 8 10 0 0 0 0 1
slotdef=6:19,13,7
T 100 3600 8 10 0 0 0 0 1
slotdef=7:19,15,5
T 100 3800 8 10 0 0 0 0 1
slotdef=8:19,17,3
T 100 4000 8 10 0 0 0 0 1
numslots=8
T 700 500 8 10 1 0 0 0 1
slot=1

View File

@@ -0,0 +1,67 @@
v 20110115 2
P 0 900 300 900 1 0 0
{
T 0 900 5 10 0 0 0 0 1
pintype=pwr
T 355 895 5 10 1 1 0 0 1
pinlabel=VIN
T 205 945 5 10 1 1 0 6 1
pinnumber=5
T 0 900 5 10 0 0 0 0 1
pinseq=5
}
P 0 600 300 600 1 0 0
{
T 0 600 5 10 0 0 0 0 1
pintype=in
T 355 595 5 10 1 1 0 0 1
pinlabel=ON
T 205 645 5 10 1 1 0 6 1
pinnumber=4
T 0 600 5 10 0 0 0 0 1
pinseq=4
}
P 1000 0 1000 300 1 0 0
{
T 1000 0 5 10 0 0 0 0 1
pintype=pwr
T 1145 500 5 10 1 1 180 0 1
pinlabel=GND
T 950 205 5 10 1 1 90 6 1
pinnumber=2
T 1000 0 5 10 0 0 0 0 1
pinseq=2
}
P 2000 600 1700 600 1 0 0
{
T 2000 600 5 10 0 0 0 0 1
pintype=out
T 1645 595 5 10 1 1 0 6 1
pinlabel=FLAGB
T 1795 645 5 10 1 1 0 0 1
pinnumber=3
T 2000 600 5 10 0 0 0 0 1
pinseq=3
}
P 2000 900 1700 900 1 0 0
{
T 2000 900 5 10 0 0 0 0 1
pintype=pwr
T 1645 895 5 10 1 1 0 6 1
pinlabel=VOUT
T 1795 945 5 10 1 1 0 0 1
pinnumber=1
T 2000 900 5 10 0 0 0 0 1
pinseq=1
}
B 300 300 1400 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 295 1795 8 10 0 0 0 0 1
device=FPF2005
T 300 1600 8 10 0 0 0 0 1
description=load switch
T 300 1200 8 10 1 1 0 0 1
refdes=IC?
T 300 1400 8 10 0 0 0 0 1
footprint=SC70-5
T 1000 1200 9 10 1 0 0 0 1
FPF2005

View File

@@ -0,0 +1,100 @@
v 20110115 2
P 0 1300 300 1300 1 0 0
{
T 0 1300 5 10 0 0 0 0 1
pintype=pwr
T 355 1295 5 10 1 1 0 0 1
pinlabel=IN
T 205 1345 5 10 1 1 0 6 1
pinnumber=2
T 0 1300 5 10 0 0 0 0 1
pinseq=2
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=in
T 355 695 5 10 1 1 0 0 1
pinlabel=\_ONA\_
T 205 745 5 10 1 1 0 6 1
pinnumber=3
T 0 700 5 10 0 0 0 0 1
pinseq=3
}
P 0 400 300 400 1 0 0
{
T 0 400 5 10 0 0 0 0 1
pintype=in
T 355 395 5 10 1 1 0 0 1
pinlabel=\_ONB\_
T 205 445 5 10 1 1 0 6 1
pinnumber=4
T 0 400 5 10 0 0 0 0 1
pinseq=4
}
P 2200 1300 1900 1300 1 0 0
{
T 2200 1300 5 10 0 0 0 0 1
pintype=out
T 1845 1295 5 10 1 1 0 6 1
pinlabel=\_FLAGA\_
T 1995 1345 5 10 1 1 0 0 1
pinnumber=8
T 2200 1300 5 10 0 0 0 0 1
pinseq=8
}
P 2200 1000 1900 1000 1 0 0
{
T 2200 1000 5 10 0 0 0 0 1
pintype=out
T 1845 995 5 10 1 1 0 6 1
pinlabel=\_FLAGB\_
T 1995 1045 5 10 1 1 0 0 1
pinnumber=5
T 2200 1000 5 10 0 0 0 0 1
pinseq=5
}
P 2200 700 1900 700 1 0 0
{
T 2200 700 5 10 0 0 0 0 1
pintype=pwr
T 1845 695 5 10 1 1 0 6 1
pinlabel=OUTA
T 1995 745 5 10 1 1 0 0 1
pinnumber=7
T 2200 700 5 10 0 0 0 0 1
pinseq=7
}
P 1200 0 1200 300 1 0 0
{
T 1200 0 5 10 0 0 0 0 1
pintype=pwr
T 1200 355 5 10 1 1 90 0 1
pinlabel=GND
T 1150 205 5 10 1 1 90 6 1
pinnumber=1
T 1200 0 5 10 0 0 0 0 1
pinseq=1
}
P 2200 400 1900 400 1 0 0
{
T 2200 400 5 10 0 0 0 0 1
pintype=pwr
T 1845 395 5 10 1 1 0 6 1
pinlabel=OUTB
T 1995 445 5 10 1 1 0 0 1
pinnumber=6
T 2200 400 5 10 0 0 0 0 1
pinseq=6
}
B 300 300 1600 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1600 8 10 1 1 0 0 1
refdes=IC?
T 1100 1600 8 10 1 1 0 0 1
device=FPF230X
T 300 1800 8 10 0 0 0 0 1
description=Dual-Output Current Limit Switch
T 300 2000 8 10 0 0 0 0 1
footprint=SO8
T 300 2200 8 10 0 0 0 0 1
alt-footprint=MLP8

View File

@@ -0,0 +1,74 @@
v 20110115 2
P 0 1100 300 1100 1 0 0
{
T 0 1100 5 10 0 0 0 0 1
pintype=pwr
T 355 1095 5 10 1 1 0 0 1
pinlabel=GND
T 205 1145 5 10 1 1 0 6 1
pinnumber=1
T 0 1100 5 10 0 0 0 0 1
pinseq=1
}
P 0 900 300 900 1 0 0
{
T 0 900 5 10 0 0 0 0 1
pintype=out
T 355 895 5 10 1 1 0 0 1
pinlabel=CTS
T 205 945 5 10 1 1 0 6 1
pinnumber=2
T 0 900 5 10 0 0 0 0 1
pinseq=2
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=pwr
T 355 695 5 10 1 1 0 0 1
pinlabel=VCC
T 205 745 5 10 1 1 0 6 1
pinnumber=3
T 0 700 5 10 0 0 0 0 1
pinseq=3
}
P 0 500 300 500 1 0 0
{
T 0 500 5 10 0 0 0 0 1
pintype=out
T 355 495 5 10 1 1 0 0 1
pinlabel=TXD
T 205 545 5 10 1 1 0 6 1
pinnumber=4
T 0 500 5 10 0 0 0 0 1
pinseq=4
}
P 0 300 300 300 1 0 0
{
T 0 300 5 10 0 0 0 0 1
pintype=in
T 355 295 5 10 1 1 0 0 1
pinlabel=RXD
T 205 345 5 10 1 1 0 6 1
pinnumber=5
T 0 300 5 10 0 0 0 0 1
pinseq=5
}
P 0 100 300 100 1 0 0
{
T 0 100 5 10 0 0 0 0 1
pintype=in
T 355 95 5 10 1 1 0 0 1
pinlabel=RTS
T 205 145 5 10 1 1 0 6 1
pinnumber=6
T 0 100 5 10 0 0 0 0 1
pinseq=6
}
B 300 0 500 1300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1400 8 10 1 1 0 0 1
refdes=J?
T 300 1800 8 10 0 0 0 0 1
device=FTDI
T 300 1600 8 10 0 0 0 0 1
description=FTDI UART interface

View File

@@ -0,0 +1,34 @@
v 20110115 2
L 3700 900 3700 0 15 0 0 0 -1 -1
B 0 0 7600 1400 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 0 900 7600 900 15 0 0 0 -1 -1
T 1000 700 9 10 1 1 0 0 1
date=$Date$
T 5100 700 9 10 1 1 0 0 1
org=$Organisation$
T 5100 400 9 10 1 1 0 0 1
authors=$Authors$
T 3500 1200 9 14 1 1 0 4 1
title=TITLE
T 3900 400 15 8 1 0 0 0 1
AUTHORS:
T 3900 100 15 8 1 0 0 0 1
LICENCE:
T 100 100 15 8 1 0 0 0 1
REVISION:
T 100 1100 15 8 1 0 0 0 1
TITLE:
T 100 400 15 8 1 0 0 0 1
VERSION:
T 900 1900 8 10 0 0 0 0 1
graphical=1
T 3900 700 15 8 1 0 0 0 1
ORGANISATION:
T 100 700 15 8 1 0 0 0 1
DATE:
T 1000 400 9 10 1 1 0 0 1
v=$Version$
T 1000 100 9 10 1 1 0 0 1
rev=$Revision$
T 5100 100 9 10 1 1 0 0 1
licence=$Licence$

View File

@@ -0,0 +1,43 @@
v 20110115 2
L 1600 0 1600 700 3 0 0 0 -1 -1
L 1600 700 1500 700 3 0 0 0 -1 -1
L 1500 0 1500 700 3 0 0 0 -1 -1
L 1500 0 1600 0 3 0 0 0 -1 -1
L 1300 0 1200 100 3 0 0 0 -1 -1
L 1200 100 1100 0 3 0 0 0 -1 -1
L 1100 0 500 0 3 0 0 0 -1 -1
L 1000 400 900 300 3 0 0 0 -1 -1
L 900 300 800 400 3 0 0 0 -1 -1
L 800 400 500 400 3 0 0 0 -1 -1
L 1500 700 500 700 3 0 0 0 -1 -1
P 0 0 500 0 1 0 0
{
T 200 45 5 10 1 1 0 6 1
pinnumber=3
T 900 100 5 10 0 0 180 0 1
pinseq=3
T 300 0 5 10 1 1 0 0 1
pinlabel=RING
}
P 0 400 500 400 1 0 0
{
T 200 445 5 10 1 1 0 6 1
pinnumber=2
T 900 500 5 10 0 0 180 0 1
pinseq=2
T 300 400 5 10 1 1 0 0 1
pinlabel=TIP
}
P 0 700 500 700 1 0 0
{
T 200 745 5 10 1 1 0 6 1
pinnumber=1
T 900 800 5 10 0 0 180 0 1
pinseq=1
T 300 700 5 10 1 1 0 0 1
pinlabel=SLEEVE
}
T 1300 800 8 10 1 1 0 0 1
refdes=P?
T 0 1200 8 10 0 0 0 0 1
description=stereo jack

View File

@@ -0,0 +1,100 @@
v 20110115 2
P 0 1000 300 1000 1 0 0
{
T 0 1000 5 10 0 0 0 0 1
pintype=pwr
T 355 995 5 10 1 1 0 0 1
pinlabel=VIN
T 205 1045 5 10 1 1 0 6 1
pinnumber=1
T 0 1000 5 10 0 0 0 0 1
pinseq=1
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=in
T 355 695 5 10 1 1 0 0 1
pinlabel=\_SD1\_
T 205 745 5 10 1 1 0 6 1
pinnumber=2
T 0 700 5 10 0 0 0 0 1
pinseq=2
}
P 0 400 300 400 1 0 0
{
T 0 400 5 10 0 0 0 0 1
pintype=in
T 355 395 5 10 1 1 0 0 1
pinlabel=\_SD2\_
T 205 445 5 10 1 1 0 6 1
pinnumber=3
T 0 400 5 10 0 0 0 0 1
pinseq=3
}
P 0 100 300 100 1 0 0
{
T 0 100 5 10 0 0 0 0 1
pintype=pwr
T 355 95 5 10 1 1 0 0 1
pinlabel=GND
T 205 145 5 10 1 1 0 6 1
pinnumber=4
T 0 100 5 10 0 0 0 0 1
pinseq=4
}
P 2100 1000 1800 1000 1 0 0
{
T 2100 1000 5 10 0 0 0 0 1
pintype=pwr
T 1745 995 5 10 1 1 0 6 1
pinlabel=VOUT1
T 1895 1045 5 10 1 1 0 0 1
pinnumber=8
T 2100 1000 5 10 0 0 0 0 1
pinseq=8
}
P 2100 700 1800 700 1 0 0
{
T 2100 700 5 10 0 0 0 0 1
pintype=pwr
T 1745 695 5 10 1 1 0 6 1
pinlabel=VOUT2
T 1895 745 5 10 1 1 0 0 1
pinnumber=7
T 2100 700 5 10 0 0 0 0 1
pinseq=7
}
P 2100 400 1800 400 1 0 0
{
T 2100 400 5 10 0 0 0 0 1
pintype=out
T 1745 395 5 10 1 1 0 6 1
pinlabel=\_ERROR1\_
T 1895 445 5 10 1 1 0 0 1
pinnumber=6
T 2100 400 5 10 0 0 0 0 1
pinseq=6
}
P 2100 100 1800 100 1 0 0
{
T 2100 100 5 10 0 0 0 0 1
pintype=out
T 1745 95 5 10 1 1 0 6 1
pinlabel=\_ERROR2\_
T 1895 145 5 10 1 1 0 0 1
pinnumber=5
T 2100 100 5 10 0 0 0 0 1
pinseq=5
}
B 300 0 1500 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1300 8 10 1 1 0 0 1
refdes=IC?
T 1200 1300 8 10 1 1 0 0 1
device=LP2966
T 300 1500 8 10 0 0 0 0 1
description=Dual 150mA Ultra Low-Dropout Regulator
T 300 1700 8 10 0 0 0 0 1
footprint=MSOP8
T 300 1900 8 10 0 0 0 0 1
manufacturer=National Semiconductor

View File

@@ -0,0 +1,122 @@
v 20110115 2
P 0 1900 300 1900 1 0 0
{
T 0 1900 5 10 0 0 0 0 1
pintype=io
T 355 1895 5 10 1 1 0 0 1
pinlabel=DAT2
T 205 1945 5 10 1 1 0 6 1
pinnumber=1
T 0 1900 5 10 0 0 0 0 1
pinseq=1
}
P 0 1700 300 1700 1 0 0
{
T 0 1700 5 10 0 0 0 0 1
pintype=io
T 355 1695 5 10 1 1 0 0 1
pinlabel=CD/DAT3
T 205 1745 5 10 1 1 0 6 1
pinnumber=2
T 0 1700 5 10 0 0 0 0 1
pinseq=2
}
P 0 1500 300 1500 1 0 0
{
T 0 1500 5 10 0 0 0 0 1
pintype=in
T 355 1495 5 10 1 1 0 0 1
pinlabel=CMD
T 205 1545 5 10 1 1 0 6 1
pinnumber=3
T 0 1500 5 10 0 0 0 0 1
pinseq=3
}
P 0 1300 300 1300 1 0 0
{
T 0 1300 5 10 0 0 0 0 1
pintype=pwr
T 355 1295 5 10 1 1 0 0 1
pinlabel=VDD
T 205 1345 5 10 1 1 0 6 1
pinnumber=4
T 0 1300 5 10 0 0 0 0 1
pinseq=4
}
P 0 1100 300 1100 1 0 0
{
T 0 1100 5 10 0 0 0 0 1
pintype=in
T 355 1095 5 10 1 1 0 0 1
pinlabel=CLK
T 205 1145 5 10 1 1 0 6 1
pinnumber=5
T 0 1100 5 10 0 0 0 0 1
pinseq=5
}
P 0 900 300 900 1 0 0
{
T 0 900 5 10 0 0 0 0 1
pintype=pwr
T 355 895 5 10 1 1 0 0 1
pinlabel=VSS
T 205 945 5 10 1 1 0 6 1
pinnumber=6
T 0 900 5 10 0 0 0 0 1
pinseq=6
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=io
T 355 695 5 10 1 1 0 0 1
pinlabel=DAT0
T 205 745 5 10 1 1 0 6 1
pinnumber=7
T 0 700 5 10 0 0 0 0 1
pinseq=7
}
P 0 500 300 500 1 0 0
{
T 0 500 5 10 0 0 0 0 1
pintype=io
T 355 495 5 10 1 1 0 0 1
pinlabel=DAT1
T 205 545 5 10 1 1 0 6 1
pinnumber=8
T 0 500 5 10 0 0 0 0 1
pinseq=8
}
P 0 300 300 300 1 0 0
{
T 0 300 5 10 0 0 0 0 1
pintype=pas
T 355 295 5 10 1 1 0 0 1
pinlabel=SW_A
T 205 345 5 10 1 1 0 6 1
pinnumber=9
T 0 300 5 10 0 0 0 0 1
pinseq=9
}
P 0 100 300 100 1 0 0
{
T 0 100 5 10 0 0 0 0 1
pintype=pas
T 355 95 5 10 1 1 0 0 1
pinlabel=SW_B
T 205 145 5 10 1 1 0 6 1
pinnumber=10
T 0 100 5 10 0 0 0 0 1
pinseq=10
}
V 950 100 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 300 300 900 300 3 0 0 0 -1 -1
L 900 300 1050 150 3 0 0 0 -1 -1
L 300 100 900 100 3 0 0 0 -1 -1
B 300 0 900 2100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 2200 8 10 1 1 0 0 1
refdes=J?
T 300 2600 8 10 0 0 0 0 1
device=microSD
T 300 2400 8 10 0 0 0 0 1
description=microSD slot with normally open presence switch

View File

@@ -0,0 +1,49 @@
v 20110115 2
P 600 1000 600 800 1 0 0
{
T 500 850 5 6 1 1 0 0 1
pinnumber=3
T 500 850 5 6 0 0 0 0 1
pinseq=3
T 600 850 5 6 1 1 0 0 1
pinlabel=C
T 500 850 5 6 0 1 0 0 1
pintype=pas
}
P 600 200 600 0 1 0 1
{
T 500 50 5 6 1 1 0 0 1
pinnumber=2
T 500 50 5 6 0 0 0 0 1
pinseq=2
T 600 50 5 6 1 1 0 0 1
pinlabel=E
T 500 50 5 6 0 1 0 0 1
pintype=pas
}
V 500 501 316 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 900 500 5 10 0 0 0 0 1
device=NPN_TRANSISTOR
L 600 200 400 400 3 0 0 0 -1 -1
L 600 800 400 600 3 0 0 0 -1 -1
L 400 700 400 300 3 0 0 0 -1 -1
P 0 500 184 500 1 0 0
{
T 0 550 5 6 1 1 0 0 1
pinnumber=1
T 100 550 5 6 0 0 0 0 1
pinseq=1
T 100 550 5 6 1 1 0 0 1
pinlabel=B
T 100 550 5 6 0 1 0 0 1
pintype=pas
}
L 400 500 184 500 3 0 0 0 -1 -1
T 900 500 8 10 1 1 0 0 1
refdes=Q?
H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5
M 510,240
L 601,200
L 555,295
L 535,265
z

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@@ -0,0 +1,122 @@
v 20110115 2
P 0 1000 300 1000 1 0 0
{
T 0 1000 5 10 0 0 0 0 1
pintype=io
T 355 995 5 10 1 1 0 0 1
pinlabel=A1
T 205 1045 5 10 1 1 0 6 1
pinnumber=3
T 0 1000 5 10 0 0 0 0 1
pinseq=3
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=io
T 355 695 5 10 1 1 0 0 1
pinlabel=A2
T 205 745 5 10 1 1 0 6 1
pinnumber=4
T 0 700 5 10 0 0 0 0 1
pinseq=4
}
P 0 400 300 400 1 0 0
{
T 0 400 5 10 0 0 0 0 1
pintype=io
T 355 395 5 10 1 1 0 0 1
pinlabel=A3
T 205 445 5 10 1 1 0 6 1
pinnumber=5
T 0 400 5 10 0 0 0 0 1
pinseq=5
}
P 800 1800 800 1500 1 0 0
{
T 800 1800 5 10 0 0 0 0 1
pintype=pwr
T 800 1445 5 10 1 1 90 6 1
pinlabel=VREFA
T 750 1595 5 10 1 1 90 0 1
pinnumber=2
T 800 1800 5 10 0 0 0 0 1
pinseq=2
}
P 1200 1800 1200 1500 1 0 0
{
T 1200 1800 5 10 0 0 0 0 1
pintype=pwr
T 1200 1445 5 10 1 1 90 6 1
pinlabel=VREFB
T 1150 1595 5 10 1 1 90 0 1
pinnumber=9
T 1200 1800 5 10 0 0 0 0 1
pinseq=9
}
P 1000 0 1000 300 1 0 0
{
T 1000 0 5 10 0 0 0 0 1
pintype=pwr
T 1000 355 5 10 1 1 90 0 1
pinlabel=GND
T 950 205 5 10 1 1 90 6 1
pinnumber=1
T 1000 0 5 10 0 0 0 0 1
pinseq=1
}
P 1900 1300 1600 1300 1 0 0
{
T 1900 1300 5 10 0 0 0 0 1
pintype=in
T 1545 1295 5 10 1 1 0 6 1
pinlabel=EN
T 1695 1345 5 10 1 1 0 0 1
pinnumber=10
T 1900 1300 5 10 0 0 0 0 1
pinseq=10
}
P 1900 1000 1600 1000 1 0 0
{
T 1900 1000 5 10 0 0 0 0 1
pintype=io
T 1545 995 5 10 1 1 0 6 1
pinlabel=B1
T 1695 1045 5 10 1 1 0 0 1
pinnumber=8
T 1900 1000 5 10 0 0 0 0 1
pinseq=8
}
P 1900 700 1600 700 1 0 0
{
T 1900 700 5 10 0 0 0 0 1
pintype=io
T 1545 695 5 10 1 1 0 6 1
pinlabel=B2
T 1695 745 5 10 1 1 0 0 1
pinnumber=7
T 1900 700 5 10 0 0 0 0 1
pinseq=7
}
P 1900 400 1600 400 1 0 0
{
T 1900 400 5 10 0 0 0 0 1
pintype=io
T 1545 395 5 10 1 1 0 6 1
pinlabel=B3
T 1695 445 5 10 1 1 0 0 1
pinnumber=6
T 1900 400 5 10 0 0 0 0 1
pinseq=6
}
B 300 300 1300 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1900 8 10 1 1 0 0 1
refdes=U?
T 300 2100 8 10 0 0 0 0 1
device=NVT2003
T 300 2300 8 10 0 0 0 0 1
description=Bidirectional voltage-level translator
T 300 2500 8 10 0 0 0 0 1
manufacturer=NXP
T 300 2700 8 10 0 0 0 0 1
footprint=TSSOP10

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@@ -0,0 +1,74 @@
v 20110115 2
P 0 1100 300 1100 1 0 0
{
T 0 1100 5 10 0 0 0 0 1
pintype=pwr
T 355 1095 5 10 1 1 0 0 1
pinlabel=VCC
T 205 1145 5 10 1 1 0 6 1
pinnumber=1
T 0 1100 5 10 0 0 0 0 1
pinseq=1
}
P 0 900 300 900 1 0 0
{
T 0 900 5 10 0 0 0 0 1
pintype=in
T 355 895 5 10 1 1 0 0 1
pinlabel=RST
T 205 945 5 10 1 1 0 6 1
pinnumber=2
T 0 900 5 10 0 0 0 0 1
pinseq=2
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=in
T 355 695 5 10 1 1 0 0 1
pinlabel=CLK
T 205 745 5 10 1 1 0 6 1
pinnumber=3
T 0 700 5 10 0 0 0 0 1
pinseq=3
}
P 0 500 300 500 1 0 0
{
T 0 500 5 10 0 0 0 0 1
pintype=io
T 355 495 5 10 1 1 0 0 1
pinlabel=I/O
T 205 545 5 10 1 1 0 6 1
pinnumber=4
T 0 500 5 10 0 0 0 0 1
pinseq=4
}
P 0 300 300 300 1 0 0
{
T 0 300 5 10 0 0 0 0 1
pintype=pas
T 355 295 5 10 1 1 0 0 1
pinlabel=VPP
T 205 345 5 10 1 1 0 6 1
pinnumber=5
T 0 300 5 10 0 0 0 0 1
pinseq=5
}
P 0 100 300 100 1 0 0
{
T 0 100 5 10 0 0 0 0 1
pintype=pwr
T 355 95 5 10 1 1 0 0 1
pinlabel=GND
T 205 145 5 10 1 1 0 6 1
pinnumber=6
T 0 100 5 10 0 0 0 0 1
pinseq=6
}
B 300 0 500 1300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1400 8 10 1 1 0 0 1
refdes=J?
T 300 1800 8 10 0 0 0 0 1
device=REBELSIM
T 300 1600 8 10 0 0 0 0 1
description=RebelSim FFC connector

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@@ -0,0 +1,129 @@
v 20110115 2
P 0 1700 300 1700 1 0 0
{
T 0 1700 5 10 0 0 0 0 1
pintype=pwr
T 355 1695 5 10 1 1 0 0 1
pinlabel=VCC
T 205 1745 5 10 1 1 0 6 1
pinnumber=C1
T 0 1700 5 10 0 0 0 0 1
pinseq=1
}
P 0 1400 300 1400 1 0 0
{
T 0 1400 5 10 0 0 0 0 1
pintype=io
T 355 1395 5 10 1 1 0 0 1
pinlabel=RST
T 205 1445 5 10 1 1 0 6 1
pinnumber=C2
T 0 1400 5 10 0 0 0 0 1
pinseq=2
}
P 0 1100 300 1100 1 0 0
{
T 0 1100 5 10 0 0 0 0 1
pintype=io
T 355 1095 5 10 1 1 0 0 1
pinlabel=CLK
T 205 1145 5 10 1 1 0 6 1
pinnumber=C3
T 0 1100 5 10 0 0 0 0 1
pinseq=3
}
P 0 800 300 800 1 0 0
{
T 0 800 5 10 0 0 0 0 1
pintype=pas
T 355 795 5 10 1 1 0 0 1
pinlabel=RFU
T 205 845 5 10 1 1 0 6 1
pinnumber=C4
T 0 800 5 10 0 0 0 0 1
pinseq=4
}
P 1600 1700 1300 1700 1 0 0
{
T 1600 1700 5 10 0 0 0 0 1
pintype=pwr
T 1245 1695 5 10 1 1 0 6 1
pinlabel=GND
T 1395 1745 5 10 1 1 0 0 1
pinnumber=C5
T 1600 1700 5 10 0 0 0 0 1
pinseq=5
}
P 1600 1400 1300 1400 1 0 0
{
T 1600 1400 5 10 0 0 0 0 1
pintype=pas
T 1245 1395 5 10 1 1 0 6 1
pinlabel=VPP
T 1395 1445 5 10 1 1 0 0 1
pinnumber=C6
T 1600 1400 5 10 0 0 0 0 1
pinseq=6
}
P 1600 1100 1300 1100 1 0 0
{
T 1600 1100 5 10 0 0 0 0 1
pintype=io
T 1245 1095 5 10 1 1 0 6 1
pinlabel=I/O
T 1395 1145 5 10 1 1 0 0 1
pinnumber=C7
T 1600 1100 5 10 0 0 0 0 1
pinseq=7
}
P 1600 800 1300 800 1 0 0
{
T 1600 800 5 10 0 0 0 0 1
pintype=pas
T 1245 795 5 10 1 1 0 6 1
pinlabel=RFU
T 1395 845 5 10 1 1 0 0 1
pinnumber=C8
T 1600 800 5 10 0 0 0 0 1
pinseq=8
}
P 0 300 300 300 1 0 0
{
T 0 300 5 10 0 0 0 0 1
pintype=pas
T 255 -5 5 10 1 1 0 0 1
pinlabel=SW1
T 205 345 5 10 1 1 0 6 1
pinnumber=9
T 0 300 5 10 0 0 0 0 1
pinseq=9
}
P 1700 300 1400 300 1 0 0
{
T 1700 300 5 10 0 0 0 0 1
pintype=pas
T 1445 -5 5 10 1 1 0 6 1
pinlabel=SW2
T 1495 345 5 10 1 1 0 0 1
pinnumber=10
T 1700 300 5 10 0 0 0 0 1
pinseq=10
}
V 1300 300 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 300 300 1300 500 3 0 0 0 -1 -1
B 300 1600 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 300 1300 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 300 1000 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 300 700 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 800 1600 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 800 1300 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 800 1000 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 800 700 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 2000 8 10 1 1 0 0 1
refdes=J?
T 300 2400 8 10 0 0 0 0 1
device=SC
T 300 2200 8 10 0 0 0 0 1
description=smart card interface with normally open presence switch
T 1000 2000 9 10 1 0 0 0 1
SC

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@@ -0,0 +1,79 @@
v 20110115 2
P 0 200 300 200 1 0 0
{
T 0 200 5 10 0 0 0 0 1
pintype=in
T 105 -5 5 10 1 1 0 0 1
pinlabel=A
T 205 245 5 10 1 1 0 6 1
pinnumber=2
T 0 200 5 10 0 0 0 0 1
pinseq=2
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=in
T 5 495 5 10 1 1 0 0 1
pinlabel=\_OE\_
T 205 745 5 10 1 1 0 6 1
pinnumber=1
T 0 700 5 10 0 0 0 0 1
pinseq=1
}
P 1200 200 900 200 1 0 0
{
T 1200 200 5 10 0 0 0 0 1
pintype=out
T 1005 -5 5 10 1 1 0 0 1
pinlabel=Y
T 995 245 5 10 1 1 0 0 1
pinnumber=3
T 1200 200 5 10 0 0 0 0 1
pinseq=3
}
L 400 500 400 900 3 0 0 0 -1 -1
L 400 500 700 700 3 0 0 0 -1 -1
L 400 900 700 700 3 0 0 0 -1 -1
L 300 400 300 0 3 0 0 0 -1 -1
L 600 200 300 0 3 0 0 0 -1 -1
L 300 400 600 200 3 0 0 0 -1 -1
V 350 700 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 650 200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 700 200 900 200 3 0 0 0 -1 -1
L 450 300 450 400 3 0 0 0 -1 -1
L 450 400 800 400 3 0 0 0 -1 -1
L 800 400 800 700 3 0 0 0 -1 -1
L 800 700 700 700 3 0 0 0 -1 -1
T 0 950 8 10 1 1 0 0 1
refdes=U?
T 700 900 8 10 1 0 0 0 1
slot=1
T 0 1200 8 10 0 0 0 0 1
device=SN74LVC240A
T 0 1400 8 10 0 0 0 0 1
description=2x4 inverter
T 0 1600 8 10 0 0 0 0 1
numslots=8
T 0 1800 8 10 0 0 0 0 1
documentation=http://www.ti.com/lit/ds/symlink/sn74lvc240a.pdf
T 0 2000 8 10 0 0 0 0 1
net=Vcc:20
T 0 2200 8 10 0 0 0 0 1
net=GND:10
T 0 2400 8 10 0 0 0 0 1
slotdef=1:1,2,18
T 0 2600 8 10 0 0 0 0 1
slotdef=2:1,4,16
T 0 2800 8 10 0 0 0 0 1
slotdef=3:1,6,14
T 0 3000 8 10 0 0 0 0 1
slotdef=4:1,8,12
T 0 3200 8 10 0 0 0 0 1
slotdef=5:19,11,9
T 0 3400 8 10 0 0 0 0 1
slotdef=6:19,13,7
T 0 3600 8 10 0 0 0 0 1
slotdef=7:19,15,5
T 0 3800 8 10 0 0 0 0 1
slotdef=8:19,17,3

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@@ -0,0 +1,65 @@
v 20110115 2
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=pwr
T 355 695 5 10 1 1 0 0 1
pinlabel=Vin
T 205 745 5 10 1 1 0 6 1
pinnumber=1
T 0 700 5 10 0 0 0 0 1
pinseq=1
}
P 0 400 300 400 1 0 0
{
T 0 400 5 10 0 0 0 0 1
pintype=pwr
T 355 395 5 10 1 1 0 0 1
pinlabel=GND
T 205 445 5 10 1 1 0 6 1
pinnumber=2
T 0 400 5 10 0 0 0 0 1
pinseq=2
}
P 0 100 300 100 1 0 0
{
T 0 100 5 10 0 0 0 0 1
pintype=in
T 355 95 5 10 1 1 0 0 1
pinlabel=\_SHDN\_
T 205 145 5 10 1 1 0 6 1
pinnumber=3
T 0 100 5 10 0 0 0 0 1
pinseq=3
}
P 1700 700 1400 700 1 0 0
{
T 1700 700 5 10 0 0 0 0 1
pintype=pwr
T 1345 695 5 10 1 1 0 6 1
pinlabel=Vout
T 1495 745 5 10 1 1 0 0 1
pinnumber=5
T 1700 700 5 10 0 0 0 0 1
pinseq=5
}
P 1700 100 1400 100 1 0 0
{
T 1700 100 5 10 0 0 0 0 1
pintype=passive
T 1345 95 5 10 1 1 0 6 1
pinlabel=ADJ
T 1495 145 5 10 1 1 0 0 1
pinnumber=4
T 1700 100 5 10 0 0 0 0 1
pinseq=4
}
B 300 0 1100 900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1000 8 10 1 1 0 0 1
refdes=U?
T 300 1200 8 10 0 0 0 0 1
device=TC1071
T 300 1400 8 10 0 0 0 0 1
manufacturer=Microchip
T 300 1600 8 10 0 0 0 0 1
documentation=http://ww1.microchip.com/downloads/en/DeviceDoc/21353E.pdf

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@@ -0,0 +1,107 @@
v 20070818 1
P 1900 1700 2200 1700 1 0 1
{
T 1550 1650 5 8 1 1 0 0 1
pinnumber=2
T 750 1650 5 8 0 0 0 0 1
pinseq=2
T 750 1650 5 8 0 1 0 0 1
pinlabel=2
T 750 1650 5 8 0 1 0 0 1
pintype=pas
}
P 1900 1100 2200 1100 1 0 1
{
T 1550 1050 5 8 1 1 0 0 1
pinnumber=4
T 750 1050 5 8 0 0 0 0 1
pinseq=4
T 750 1050 5 8 0 1 0 0 1
pinlabel=4
T 750 1050 5 8 0 1 0 0 1
pintype=pas
}
P 1900 2000 2200 2000 1 0 1
{
T 1550 1950 5 8 1 1 0 0 1
pinnumber=1
T 750 1950 5 8 0 0 0 0 1
pinseq=1
T 750 1950 5 8 0 1 0 0 1
pinlabel=1
T 750 1950 5 8 0 1 0 0 1
pintype=pas
}
P 1900 1400 2200 1400 1 0 1
{
T 1550 1350 5 8 1 1 0 0 1
pinnumber=3
T 750 1350 5 8 0 0 0 0 1
pinseq=3
T 750 1350 5 8 0 1 0 0 1
pinlabel=3
T 750 1350 5 8 0 1 0 0 1
pintype=pas
}
P 900 300 900 0 1 0 1
{
T 900 850 5 8 1 1 180 6 1
pinnumber=G
T 850 1450 5 8 0 0 270 0 1
pinseq=6
T 900 350 5 8 0 1 90 0 1
pinlabel=G
T 850 1450 5 8 0 1 270 0 1
pintype=pas
}
L 1900 2000 1700 2000 3 0 0 0 -1 -1
L 1900 1700 1700 1700 3 0 0 0 -1 -1
L 1900 1400 1700 1400 3 0 0 0 -1 -1
L 1900 1100 1700 1100 3 0 0 0 -1 -1
L 900 500 900 300 3 0 0 0 -1 -1
T 100 2200 5 10 0 0 0 0 1
author=andrewmATthehacktoryDOTcom
T 100 2300 8 10 1 1 0 0 1
refdes=CONN?
V 900 600 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 1000 600 1700 600 3 0 0 0 -1 -1
L 1700 2200 0 2200 3 0 0 0 -1 -1
L 1700 2200 1700 600 3 0 0 0 -1 -1
L 800 600 0 600 3 0 0 0 -1 -1
L 0 2200 0 600 3 0 0 0 -1 -1
L 100 2200 100 600 3 0 0 0 -1 -1
T 100 2400 5 10 0 0 0 0 1
dist-license=GPL
T 100 2600 5 10 0 0 0 0 1
use-license=unlimited
T 1450 2000 9 10 1 0 0 7 1
5V
T 1450 1700 9 10 1 0 0 7 1
D-
T 1450 1400 9 10 1 0 0 7 1
D+
T 1450 1100 9 10 1 0 0 7 1
ID
P 1900 800 2200 800 1 0 1
{
T 1550 750 5 8 1 1 0 0 1
pinnumber=5
T 750 750 5 8 0 0 0 0 1
pinseq=5
T 750 750 5 8 0 1 0 0 1
pinlabel=5
T 750 750 5 8 0 1 0 0 1
pintype=pas
}
L 1900 800 1700 800 3 0 0 0 -1 -1
T 1450 800 9 10 1 0 0 7 1
GND
L 200 1900 200 900 3 0 0 0 -1 -1
L 200 900 400 900 3 0 0 0 -1 -1
L 400 900 600 700 3 0 0 0 -1 -1
L 600 700 800 700 3 0 0 0 -1 -1
L 800 700 800 2100 3 0 0 0 -1 -1
L 800 2100 600 2100 3 0 0 0 -1 -1
L 600 2100 400 1900 3 0 0 0 -1 -1
L 400 1900 200 1900 3 0 0 0 -1 -1
L 500 2100 400 2100 3 0 0 0 -1 -1

2371
hardware/geda/simtrace.sch Normal file

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1
hardware/geda/version Normal file
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1.5

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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Device_Battery
#
DEF Device_Battery BT 0 0 N N 1 F N
F0 "BT" 100 100 50 H V L CNN
F1 "Device_Battery" 100 0 50 H V L CNN
F2 "" 0 60 50 V I C CNN
F3 "" 0 60 50 V I C CNN
DRAW
S -80 -55 80 -65 0 1 0 F
S -80 70 80 60 0 1 0 F
S -52 -78 50 -98 0 1 0 F
S -52 47 50 27 0 1 0 F
P 2 0 1 0 0 -60 0 -50 N
P 2 0 1 0 0 -40 0 -30 N
P 2 0 1 0 0 -20 0 -10 N
P 2 0 1 0 0 0 0 10 N
P 2 0 1 0 0 20 0 30 N
P 2 0 1 0 0 70 0 100 N
P 2 0 1 10 10 105 50 105 N
P 2 0 1 10 30 125 30 85 N
X + 1 0 200 100 D 50 50 1 1 P
X - 2 0 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Crystal
#
DEF Device_Crystal Y 0 40 N N 1 F N
F0 "Y" 0 150 50 H V C CNN
F1 "Device_Crystal" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Crystal*
$ENDFPLIST
DRAW
S -45 100 45 -100 0 1 12 N
P 2 0 1 0 -100 0 -75 0 N
P 2 0 1 20 -75 -50 -75 50 N
P 2 0 1 20 75 -50 75 50 N
P 2 0 1 0 100 0 75 0 N
X 1 1 -150 0 50 R 50 50 1 1 P
X 2 2 150 0 50 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Ferrite_Bead
#
DEF Device_Ferrite_Bead FB 0 0 N Y 1 F N
F0 "FB" -150 25 50 V V C CNN
F1 "Device_Ferrite_Bead" 150 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Inductor_*
L_*
*Ferrite*
$ENDFPLIST
DRAW
P 2 0 1 0 0 -50 0 -48 N
P 2 0 1 0 0 50 0 51 N
P 5 0 1 0 -109 16 -67 89 109 -12 66 -85 -109 16 N
X ~ 1 0 150 100 D 50 50 1 1 P
X ~ 2 0 -150 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Jumper
#
DEF Device_Jumper JP 0 30 Y N 1 F N
F0 "JP" 0 150 50 H V C CNN
F1 "Device_Jumper" 0 -80 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SolderJumper*
$ENDFPLIST
DRAW
A 0 -26 125 1426 373 0 1 0 N -98 50 99 50
C -100 0 35 0 1 0 N
C 100 0 35 0 1 0 N
X 1 1 -300 0 165 R 50 50 0 1 P
X 2 2 300 0 165 L 50 50 0 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 8 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# SIMtrace_AP7332
#
DEF SIMtrace_AP7332 IC 0 40 Y Y 1 F N
F0 "IC" 0 250 60 H V C CNN
F1 "SIMtrace_AP7332" 0 -250 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 200 300 -200 0 1 0 N
X VOUT2 1 450 0 150 L 50 50 1 1 w
X GND 2 450 -100 150 L 50 50 1 1 W
X EN2 3 -450 -100 150 R 50 50 1 1 I
X EN1 4 -450 0 150 R 50 50 1 1 I
X VIN 5 -450 100 150 R 50 50 1 1 W
X VOUT1 6 450 100 150 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# SIMtrace_BC847
#
DEF SIMtrace_BC847 Q 0 0 Y Y 1 F N
F0 "Q" 0 -150 50 H V R CNN
F1 "SIMtrace_BC847" 0 150 50 H V R CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 100 100 N
P 3 0 1 10 0 75 0 -75 0 -75 N
P 3 0 1 0 50 -50 0 0 0 0 N
P 3 0 1 0 90 -90 100 -100 100 -100 N
P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F
X B 1 -200 0 200 R 40 40 1 1 I
X E 2 100 -200 100 U 40 40 1 1 P
X C 3 100 200 100 D 40 40 1 1 P
ENDDRAW
ENDDEF
#
# SIMtrace_CB3Q3244
#
DEF SIMtrace_CB3Q3244 IC 0 0 Y Y 9 L N
F0 "IC" -150 200 60 H V C CNN
F1 "SIMtrace_CB3Q3244" -300 -150 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C -85 0 10 1 1 0 N
C -85 0 10 2 1 0 N
C -85 0 10 3 1 0 N
C -85 0 10 4 1 0 N
C -85 0 10 5 1 0 N
C -85 0 10 6 1 0 N
C -85 0 10 7 1 0 N
C -85 0 10 8 1 0 N
P 3 1 1 0 -200 0 -250 0 -250 0 N
P 3 1 1 0 0 0 -75 0 -75 0 N
P 3 1 1 0 0 50 0 -50 0 -50 N
P 3 1 1 0 25 50 25 -50 25 -50 N
P 4 1 1 0 25 -25 100 -25 100 -100 100 -100 N
P 4 1 1 0 25 25 100 25 100 100 100 100 N
P 5 1 1 0 -200 50 -100 0 -200 -50 -200 50 -200 50 N
P 3 2 1 0 -200 0 -250 0 -250 0 N
P 3 2 1 0 0 0 -75 0 -75 0 N
P 3 2 1 0 0 50 0 -50 0 -50 N
P 3 2 1 0 25 50 25 -50 25 -50 N
P 4 2 1 0 25 -25 100 -25 100 -100 100 -100 N
P 4 2 1 0 25 25 100 25 100 100 100 100 N
P 5 2 1 0 -200 50 -200 -50 -100 0 -200 50 -200 50 N
P 3 3 1 0 -200 0 -250 0 -250 0 N
P 3 3 1 0 0 0 -75 0 -75 0 N
P 3 3 1 0 0 50 0 -50 0 -50 N
P 3 3 1 0 25 50 25 -50 25 -50 N
P 4 3 1 0 25 -25 100 -25 100 -100 100 -100 N
P 4 3 1 0 25 25 100 25 100 100 100 100 N
P 5 3 1 0 -200 50 -200 -50 -100 0 -200 50 -200 50 N
P 3 4 1 0 -200 0 -250 0 -250 0 N
P 3 4 1 0 0 0 -75 0 -75 0 N
P 3 4 1 0 0 50 0 -50 0 -50 N
P 3 4 1 0 25 50 25 -50 25 -50 N
P 4 4 1 0 25 -25 100 -25 100 -100 100 -100 N
P 4 4 1 0 25 25 100 25 100 100 100 100 N
P 5 4 1 0 -200 50 -200 -50 -100 0 -200 50 -200 50 N
P 3 5 1 0 -250 0 -200 0 -200 0 N
P 3 5 1 0 0 0 -75 0 -75 0 N
P 3 5 1 0 0 50 0 -50 0 -50 N
P 3 5 1 0 25 50 25 -50 25 -50 N
P 4 5 1 0 25 -25 100 -25 100 -100 100 -100 N
P 4 5 1 0 25 25 100 25 100 100 100 100 N
P 5 5 1 0 -200 50 -200 -50 -100 0 -200 50 -200 50 N
P 3 6 1 0 0 0 -75 0 -75 0 N
P 3 6 1 0 0 50 0 -50 0 -50 N
P 3 6 1 0 25 50 25 -50 25 -50 N
P 4 6 1 0 -200 0 -250 0 -250 0 -250 0 N
P 4 6 1 0 25 -25 100 -25 100 -100 100 -100 N
P 4 6 1 0 25 25 100 25 100 100 100 100 N
P 5 6 1 0 -200 50 -200 -50 -100 0 -200 50 -200 50 N
P 3 7 1 0 -200 0 -250 0 -250 0 N
P 3 7 1 0 0 0 -75 0 -75 0 N
P 3 7 1 0 0 50 0 -50 0 -50 N
P 3 7 1 0 25 50 25 -50 25 -50 N
P 4 7 1 0 25 -25 100 -25 100 -100 100 -100 N
P 4 7 1 0 25 25 100 25 100 100 100 100 N
P 5 7 1 0 -200 50 -200 -50 -100 0 -200 50 -200 50 N
P 3 8 1 0 -200 0 -250 0 -250 0 N
P 3 8 1 0 0 0 -75 0 -75 0 N
P 3 8 1 0 0 50 0 -50 0 -50 N
P 3 8 1 0 25 50 25 -50 25 -50 N
P 4 8 1 0 25 -25 100 -25 100 -100 100 -100 N
P 4 8 1 0 25 25 100 25 100 100 100 100 N
P 5 8 1 0 -200 50 -200 -50 -100 0 -200 50 -200 50 N
X /1OE 1 -400 0 150 R 60 60 1 1 I
X 1B1 18 100 -250 150 U 60 60 1 1 B
X 1A1 2 100 250 150 D 60 60 1 1 B
X /1OE 1 -400 0 150 R 60 60 2 1 I
X 1B2 16 100 -250 150 U 60 60 2 1 B
X 1A2 4 100 250 150 D 60 60 2 1 B
X /1OE 1 -400 0 150 R 60 60 3 1 I
X 1B3 14 100 -250 150 U 60 60 3 1 B
X 1A3 6 100 250 150 D 60 60 3 1 B
X /1OE 1 -400 0 150 R 60 60 4 1 I
X 1B4 12 100 -250 150 U 60 60 4 1 B
X 1A4 8 100 250 150 D 60 60 4 1 B
X 2A1 11 100 250 150 D 60 60 5 1 B
X /2OE 19 -400 0 150 R 60 60 5 1 I
X 2B1 9 100 -250 150 U 60 60 5 1 B
X 2A2 13 100 250 150 D 60 60 6 1 B
X /2OE 19 -400 0 150 R 60 60 6 1 I
X 2B2 7 100 -250 150 U 60 60 6 1 B
X 2A3 15 100 250 150 D 60 60 7 1 B
X /2OE 19 -400 0 150 R 60 60 7 1 I
X 2B3 5 100 -250 150 U 60 60 7 1 B
X 2A4 17 100 250 150 D 60 60 8 1 B
X /2OE 19 -400 0 150 R 60 60 8 1 I
X 2B4 3 100 -250 150 U 60 60 8 1 B
X GND 10 100 -250 150 U 60 60 9 1 W
X VCC 20 100 250 150 D 60 60 9 1 W
ENDDRAW
ENDDEF
#
# SIMtrace_DEBUG
#
DEF SIMtrace_DEBUG P 0 30 Y Y 1 F N
F0 "P" 0 350 60 H V C CNN
F1 "SIMtrace_DEBUG" 200 0 60 V V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -100 300 150 -300 0 1 0 N
X GND 1 -350 250 250 R 60 60 1 1 W I
X CTS 2 -350 150 250 R 60 60 1 1 O I
X VCC 3 -350 50 250 R 60 60 1 1 W I
X TXD 4 -350 -50 250 R 60 60 1 1 O I
X RXD 5 -350 -150 250 R 60 60 1 1 I I
X RTS 6 -350 -250 250 R 60 60 1 1 I I
ENDDRAW
ENDDEF
#
# SIMtrace_FLASH_SPI
#
DEF SIMtrace_FLASH_SPI U 0 40 Y Y 1 F N
F0 "U" 0 300 60 H V C CNN
F1 "SIMtrace_FLASH_SPI" 0 -300 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -350 250 350 -250 0 1 0 N
X /CS 1 -600 150 250 R 60 60 1 1 I
X SO 2 -600 50 250 R 60 60 1 1 O
X /WP 3 -600 -50 250 R 60 60 1 1 O
X GND 4 -600 -150 250 R 60 60 1 1 W
X SI 5 600 -150 250 L 60 60 1 1 I
X SCK 6 600 -50 250 L 60 60 1 1 I
X /HOLD 7 600 50 250 L 60 60 1 1 I
X VCC 8 600 150 250 L 60 60 1 1 W
ENDDRAW
ENDDEF
#
# SIMtrace_FPF210X
#
DEF SIMtrace_FPF210X IC 0 40 Y Y 1 F N
F0 "IC" 0 350 60 H V C CNN
F1 "SIMtrace_FPF210X" 0 250 60 H V C CNN
F2 "SOT23-5" 0 450 60 H I C CNN
F3 "https://www.fairchildsemi.com/ds/FP/FPF2110.pdf" 0 -600 60 H I C CNN
DRAW
S -250 200 250 -350 0 1 0 N
X VIN 1 -400 100 150 R 50 50 1 1 W
X GND 2 0 -500 150 U 50 50 1 1 W
X ON 3 -400 -100 150 R 50 50 1 1 I
X FLAGB 4 400 -100 150 L 50 50 1 1 I
X VOUT 5 400 100 150 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# SIMtrace_JACK_2.5
#
DEF SIMtrace_JACK_2.5 J 0 0 Y Y 1 F N
F0 "J" -50 150 50 H V L BNN
F1 "SIMtrace_JACK_2.5" -150 -200 50 H V L BNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -180 -100 -120 50 1 1 0 F
P 2 1 0 0 -150 100 -150 50 N
P 3 0 1 0 -150 100 250 100 250 100 N
P 5 0 1 0 250 -100 150 -100 100 -50 50 -100 50 -100 N
P 5 0 1 0 250 0 50 0 0 -50 -50 0 -50 0 N
X SLEEVE 1 350 100 100 L 40 30 1 1 P
X TIP 2 350 -100 100 L 40 30 1 1 P
X RING 3 350 0 100 L 40 30 1 1 P
ENDDRAW
ENDDEF
#
# SIMtrace_JTAG
#
DEF SIMtrace_JTAG P 0 10 Y Y 1 F N
F0 "P" 0 550 60 H V C CNN
F1 "SIMtrace_JTAG" 0 -550 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -150 500 150 -500 0 1 0 N
X VREF 1 -450 450 300 R 60 30 1 1 P I
X GND 10 450 50 300 L 60 30 1 1 P I
X RTCK 11 -450 -50 300 R 60 30 1 1 P I
X GND 12 450 -50 300 L 60 30 1 1 P I
X TDO 13 -450 -150 300 R 60 30 1 1 P I
X GND 14 450 -150 300 L 60 30 1 1 P I
X nSRST 15 -450 -250 300 R 60 30 1 1 P I
X GND 16 450 -250 300 L 60 30 1 1 P I
X DBGRQ 17 -450 -350 300 R 60 30 1 1 P I
X GND 18 450 -350 300 L 60 30 1 1 P I
X DGBACK 19 -450 -450 300 R 60 30 1 1 P I
X VCC 2 450 450 300 L 60 30 1 1 P I
X GND 20 450 -450 300 L 60 30 1 1 P I
X nTRST 3 -450 350 300 R 60 30 1 1 P I
X GND 4 450 350 300 L 60 30 1 1 P I
X TDI 5 -450 250 300 R 60 30 1 1 P I
X GND 6 450 250 300 L 60 30 1 1 P I
X TMS 7 -450 150 300 R 60 30 1 1 P I
X GND 8 450 150 300 L 60 30 1 1 P I
X TCK 9 -450 50 300 R 60 30 1 1 P I
ENDDRAW
ENDDEF
#
# SIMtrace_SCHOTTKY
#
DEF SIMtrace_SCHOTTKY D 0 40 Y N 1 F N
F0 "D" 0 100 40 H V C CNN
F1 "SIMtrace_SCHOTTKY" 0 -100 40 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
D?
S*
$ENDFPLIST
DRAW
P 3 0 1 0 -50 50 50 0 -50 -50 F
P 6 0 1 8 75 25 75 50 50 50 50 -50 25 -50 25 -25 N
X K 1 200 0 150 L 40 40 1 1 P
X A 2 -200 0 150 R 40 40 1 1 P
ENDDRAW
ENDDEF
#
# SIMtrace_USB-B_MINI
#
DEF SIMtrace_USB-B_MINI J 0 40 Y Y 1 F N
F0 "J" 50 450 50 H V L BNN
F1 "SIMtrace_USB-B_MINI" -100 -450 50 H V L BNN
F2 "" 0 150 50 H I C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A -50 -250 50 -1799 -901 1 1 0 N -100 -250 -50 -300
A -50 250 50 901 1799 1 1 0 N -50 300 -100 250
A 0 -350 50 370 899 1 1 0 N 40 -320 0 -300
A 0 350 50 -899 -369 1 1 0 N 0 300 40 320
A 100 -275 75 -1430 -901 1 1 0 N 40 -320 100 -350
A 100 275 75 901 1431 1 1 0 N 100 350 40 320
A 200 -300 50 -899 -1 1 1 0 N 200 -350 250 -300
A 200 300 50 1 899 1 1 0 N 250 300 200 350
P 2 1 0 0 -100 250 -100 -250 N
P 2 1 0 0 -50 -300 0 -300 N
P 2 1 0 0 -50 300 0 300 N
P 2 1 0 0 0 -200 50 -250 N
P 2 1 0 0 0 200 0 -200 N
P 2 1 0 0 50 -250 150 -250 N
P 2 1 0 0 50 250 0 200 N
P 2 1 0 0 100 -350 200 -350 N
P 2 1 0 0 100 350 200 350 N
P 2 1 0 0 150 -250 150 250 N
P 2 1 0 0 150 250 50 250 N
P 2 1 0 0 250 -300 250 300 N
X VCC 1 400 200 250 L 40 40 1 1 w
X D- 2 400 100 250 L 40 40 1 1 B
X D+ 3 400 0 250 L 40 40 1 1 B
X ID 4 400 -100 250 L 40 40 1 1 P
X GND 5 400 -200 250 L 40 40 1 1 W
ENDDRAW
ENDDEF
#
# Switch_SW_Push
#
DEF Switch_SW_Push SW 0 40 N N 1 F N
F0 "SW" 50 100 50 H V L CNN
F1 "Switch_SW_Push" 0 -60 50 H V C CNN
F2 "" 0 200 50 H I C CNN
F3 "" 0 200 50 H I C CNN
DRAW
C -80 0 20 0 1 0 N
C 80 0 20 0 1 0 N
P 2 0 1 0 0 50 0 120 N
P 2 0 1 0 100 50 -100 50 N
X 1 1 -200 0 100 R 50 50 0 1 P
X 2 2 200 0 100 L 50 50 0 1 P
ENDDRAW
ENDDEF
#
# at91sam7sxxx-au_AT91SAM7S512_256_128_64_321-AU
#
DEF at91sam7sxxx-au_AT91SAM7S512_256_128_64_321-AU IC 0 40 Y Y 1 L N
F0 "IC" -1000 2300 50 H V L BNN
F1 "at91sam7sxxx-au_AT91SAM7S512_256_128_64_321-AU" -1000 -2400 50 H V L BNN
F2 "at91sam7sxxx-au-LQFP64" 0 150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 1 0 0 -1000 -2300 1000 -2300 N
P 2 1 0 0 -1000 2200 -1000 -2300 N
P 2 1 0 0 1000 -2300 1000 2200 N
P 2 1 0 0 1000 2200 -1000 2200 N
X ADVREF 1 1200 -1800 200 L 40 40 1 1 P
X PA18/RD/PCK2/AD1 10 1200 800 200 L 40 40 1 1 B
X PA21/RXD1/PCK1 11 1200 1100 200 L 40 40 1 1 B
X VDDCORE@0 12 -1200 -1500 200 R 40 40 1 1 W
X PA19/RK/FIQ 13 1200 900 200 L 40 40 1 1 B
X PA22/TXD1/NPCS3 14 1200 1200 200 L 40 40 1 1 B
X PA23/SCK1/PWM0 15 1200 1300 200 L 40 40 1 1 B
X PA20/RF/IRQ0/AD3 16 1200 1000 200 L 40 40 1 1 B
X GND@1 17 -1200 -2000 200 R 40 40 1 1 W
X VDDIO@0 18 -1200 -700 200 R 40 40 1 1 W
X PA16/TK/TIOB1 19 1200 600 200 L 40 40 1 1 B
X GND@0 2 -1200 -1900 200 R 40 40 1 1 W
X PA15/TF/TIOA1 20 1200 500 200 L 40 40 1 1 B
X PA14/SPCK/PWM3 21 1200 400 200 L 40 40 1 1 B
X PA13/MOSI/PWM2 22 1200 300 200 L 40 40 1 1 B
X PA24/RTS1/PWM1 23 1200 1400 200 L 40 40 1 1 B
X VDDCORE@1 24 -1200 -1600 200 R 40 40 1 1 W
X PA25/CTS1/PWM2 25 1200 1500 200 L 40 40 1 1 B
X PA26/DCD1/TIOA2 26 1200 1600 200 L 40 40 1 1 B
X PA12/MISO/PWM1 27 1200 200 200 L 40 40 1 1 B
X PA11/NPCS0/PWM0 28 1200 100 200 L 40 40 1 1 B
X PA10/DTXD/NPCS2 29 1200 0 200 L 40 40 1 1 B
X AD4 3 1200 -1600 200 L 40 40 1 1 P
X PA9/DRXD/NPCS1 30 1200 -100 200 L 40 40 1 1 B
X PA8/CTS0/ADTRG 31 1200 -200 200 L 40 40 1 1 B
X PA7/RTS0/PWM3 32 1200 -300 200 L 40 40 1 1 B
X TDI 33 -1200 1600 200 R 40 40 1 1 I
X PA6/TXD0/PCK0 34 1200 -400 200 L 40 40 1 1 B
X PA5/RXD0/NPCS3 35 1200 -500 200 L 40 40 1 1 B
X PA4/TWCK/TLCK0 36 1200 -600 200 L 40 40 1 1 B
X PA27/DTR1/TIOB2 37 1200 1700 200 L 40 40 1 1 B
X PA28/DSR1/TCLK1 38 1200 1800 200 L 40 40 1 1 B
X /NRST 39 -1200 1900 200 R 40 40 1 1 B I
X AD5 4 1200 -1500 200 L 40 40 1 1 P
X TST 40 -1200 2000 200 R 40 40 1 1 I
X PA29/RI1/TCLK2 41 1200 1900 200 L 40 40 1 1 B
X PA30/IRQ1/NPCS2 42 1200 2000 200 L 40 40 1 1 B
X PA3/TWD/NPCS3 43 1200 -700 200 L 40 40 1 1 B
X PA2/PWM2/SCK0 44 1200 -800 200 L 40 40 1 1 B
X VDDIO@1 45 -1200 -800 200 R 40 40 1 1 W
X GND@2 46 -1200 -2100 200 R 40 40 1 1 W
X PA1/PWM1/TIOB0 47 1200 -900 200 L 40 40 1 1 B
X PA0/PWM0/TIOA0 48 1200 -1000 200 L 40 40 1 1 B
X TDO 49 -1200 1300 200 R 40 40 1 1 O
X AD6 5 1200 -1400 200 L 40 40 1 1 P
X JTAGSEL 50 -1200 1200 200 R 40 40 1 1 I
X TMS 51 -1200 1500 200 R 40 40 1 1 I
X PA31/NPCS1/PCK2 52 1200 2100 200 L 40 40 1 1 B
X TCK 53 -1200 1400 200 R 40 40 1 1 I
X VDDCORE@2 54 -1200 -1700 200 R 40 40 1 1 W
X ERASE 55 -1200 2100 200 R 40 40 1 1 I
X DDM 56 -1200 900 200 R 40 40 1 1 P
X DDP 57 -1200 800 200 R 40 40 1 1 P
X VDDIO@2 58 -1200 -900 200 R 40 40 1 1 W
X VDDFLASH 59 -1200 -500 200 R 40 40 1 1 W
X AD7 6 1200 -1300 200 L 40 40 1 1 P
X GND@3 60 -1200 -2200 200 R 40 40 1 1 W
X XOUT 61 -1200 500 200 R 40 40 1 1 P
X XIN 62 -1200 300 200 R 40 40 1 1 P
X PLLRC 63 -1200 0 200 R 40 40 1 1 P
X VDDPLL 64 -1200 -1300 200 R 40 40 1 1 W
X VDDIN 7 -1200 -300 200 R 40 40 1 1 W
X VDDOUT 8 -1200 -1100 200 R 40 40 1 1 w
X PA17/TD/PCK1/AD0 9 1200 700 200 L 40 40 1 1 B
ENDDRAW
ENDDEF
#
# power_+1V8
#
DEF power_+1V8 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+1V8" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +1V8 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3.3V
#
DEF power_+3.3V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3.3V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3V3
#
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_PWR_FLAG
#
DEF power_PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 75 50 H I C CNN
F1 "power_PWR_FLAG" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
X pwr 1 0 0 0 U 50 50 0 0 w
ENDDRAW
ENDDEF
#
# power_VBUS
#
DEF power_VBUS #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_VBUS" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VBUS 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# smartcard_ISO7816_NO
#
DEF smartcard_ISO7816_NO P 0 40 Y Y 2 F N
F0 "P" 0 250 60 H V C CNN
F1 "smartcard_ISO7816_NO" 0 -250 60 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C -150 0 50 2 1 0 N
C 150 0 50 2 1 0 N
S -250 200 250 -200 1 1 0 N
P 3 1 1 0 -250 -100 250 -100 250 -100 N
P 3 1 1 0 -250 0 -50 0 -50 0 N
P 3 1 1 0 -50 100 -250 100 -250 100 N
P 3 1 1 0 0 -100 0 -200 0 -200 N
P 3 1 1 0 50 -100 50 100 50 100 N
P 3 1 1 0 50 0 250 0 250 0 N
P 3 1 1 0 50 100 250 100 250 100 N
P 5 1 1 0 0 200 0 100 -50 100 -50 -100 -50 -100 N
P 4 2 1 0 -100 0 100 100 100 100 100 100 N
X VCC C1 -550 150 300 R 50 50 1 1 W
X RST C2 -550 50 300 R 50 50 1 1 I
X CLK C3 -550 -50 300 R 50 50 1 1 I
X RFU C4 -550 -150 300 R 50 50 1 1 U
X GND C5 550 150 300 L 50 50 1 1 W
X VPP C6 550 50 300 L 50 50 1 1 W
X I/O C7 550 -50 300 L 50 50 1 1 B
X RFU C8 550 -150 300 L 50 50 1 1 U
X ~ SW1 -500 0 300 R 50 50 2 1 P
X ~ SW2 500 0 300 L 50 50 2 1 P
ENDDRAW
ENDDEF
#
# smartcard_REBELSIM
#
DEF smartcard_REBELSIM P 0 30 Y Y 1 F N
F0 "P" 50 350 60 H V C CNN
F1 "smartcard_REBELSIM" 200 0 60 V V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -100 300 250 -300 0 1 0 N
X VCC 1 -350 250 250 R 60 60 1 1 w I
X RST 2 -350 150 250 R 60 60 1 1 O I
X CLK 3 -350 50 250 R 60 60 1 1 O I
X I/O 4 -350 -50 250 R 60 60 1 1 B I
X VPP 5 -350 -150 250 R 60 60 1 1 w I
X GND 6 -350 -250 250 R 60 60 1 1 w I
ENDDRAW
ENDDEF
#
#End Library

File diff suppressed because it is too large Load Diff

View File

@@ -1,4 +1,4 @@
Cmp-Mod V01 Created by CvPCB (2011-06-08)-testing date = Sa 02 Jul 2011 17:52:11 CEST
Cmp-Mod V01 Created by CvPcb (2013-may-18)-stable date = Mo 28 Okt 2013 10:59:43 CET
BeginCmp
TimeStamp = /4DC804A6;
@@ -87,8 +87,8 @@ EndCmp
BeginCmp
TimeStamp = /4DC6A5DE;
Reference = C14;
ValeurCmp = 1uF;
IdModule = SM0603;
ValeurCmp = 4.7uF;
IdModule = SM0805;
EndCmp
BeginCmp
@@ -162,23 +162,23 @@ IdModule = SM0603;
EndCmp
BeginCmp
TimeStamp = /4DC7A27C;
TimeStamp = /526C4CBB;
Reference = D1;
ValeurCmp = Schottky;
ValeurCmp = MBR0530;
IdModule = SOD123;
EndCmp
BeginCmp
TimeStamp = /4DCB8C13;
TimeStamp = /526C4CDD;
Reference = D2;
ValeurCmp = 1N5819;
ValeurCmp = MBR0530;
IdModule = SOD123;
EndCmp
BeginCmp
TimeStamp = /4DCB8C0D;
TimeStamp = /526C4CEC;
Reference = D3;
ValeurCmp = 1N5819;
ValeurCmp = MBR0530;
IdModule = SOD123;
EndCmp
@@ -196,6 +196,13 @@ ValeurCmp = GREEN;
IdModule = LED-0805;
EndCmp
BeginCmp
TimeStamp = /526C4D13;
Reference = D6;
ValeurCmp = MBR0530;
IdModule = SOD123;
EndCmp
BeginCmp
TimeStamp = /4DC79E48;
Reference = FB1;
@@ -210,6 +217,13 @@ ValeurCmp = FILTER;
IdModule = SM0805;
EndCmp
BeginCmp
TimeStamp = /526C41E4;
Reference = IC1;
ValeurCmp = FPF2109;
IdModule = SOT23-5;
EndCmp
BeginCmp
TimeStamp = /4DFF8B97;
Reference = IC2;
@@ -225,31 +239,24 @@ IdModule = TQFP_64;
EndCmp
BeginCmp
TimeStamp = /4DC6A187;
TimeStamp = /4EB57076;
Reference = IC4;
ValeurCmp = CB3Q3244;
IdModule = SSOP20_BDQ;
EndCmp
BeginCmp
TimeStamp = /4DFF9774;
Reference = IC5;
ValeurCmp = FPF2005;
IdModule = SOT353;
EndCmp
BeginCmp
TimeStamp = /4CFAC6EA;
Reference = J1;
ValeurCmp = USB;
IdModule = USB-MINI-B_54819-0519;
ValeurCmp = USB-B_MINI;
IdModule = USB-MINI-B_UX60;
EndCmp
BeginCmp
TimeStamp = /4DCBE233;
Reference = J2;
ValeurCmp = JACK_2.5;
IdModule = JACK2.5_SJ1-2503A;
IdModule = JACK_2.5;
EndCmp
BeginCmp
@@ -270,7 +277,7 @@ BeginCmp
TimeStamp = /4CFCD6C9;
Reference = P1;
ValeurCmp = JTAG;
IdModule = pin_array_10x2;
IdModule = PIN_ARRAY_10X2;
EndCmp
BeginCmp
@@ -294,13 +301,6 @@ ValeurCmp = SIM;
IdModule = SIM_AMPHENOL;
EndCmp
BeginCmp
TimeStamp = /4E0D8A18;
Reference = P5;
ValeurCmp = SAM;
IdModule = SAM_FCI;
EndCmp
BeginCmp
TimeStamp = /4DC7A1CA;
Reference = Q1;
@@ -413,6 +413,13 @@ ValeurCmp = 150R;
IdModule = SM0603;
EndCmp
BeginCmp
TimeStamp = /526C5035;
Reference = R15;
ValeurCmp = 100K;
IdModule = SM0603;
EndCmp
BeginCmp
TimeStamp = /4DC7A441;
Reference = R16;
@@ -462,6 +469,20 @@ ValeurCmp = 100K;
IdModule = SM0603;
EndCmp
BeginCmp
TimeStamp = /4FB50700;
Reference = R23;
ValeurCmp = 100K;
IdModule = SM0603;
EndCmp
BeginCmp
TimeStamp = /526C5026;
Reference = R24;
ValeurCmp = 100K;
IdModule = SM0603;
EndCmp
BeginCmp
TimeStamp = /4D020733;
Reference = SW1;
@@ -480,7 +501,7 @@ BeginCmp
TimeStamp = /4DC5A250;
Reference = U1;
ValeurCmp = FLASH;
IdModule = SOIC8;
IdModule = SOC008_WIDE;
EndCmp
BeginCmp

File diff suppressed because it is too large Load Diff

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@@ -1,100 +1,26 @@
update=Fr 01 Jul 2011 23:18:53 CEST
last_client=pcbnew
update=Di 03 Sep 2019 14:46:50 CEST
last_client=kicad
[general]
version=1
[eeschema]
version=1
LibDir=
NetFmt=1
HPGLSpd=20
HPGLDm=15
HPGLNum=1
offX_A4=0
offY_A4=0
offX_A3=0
offY_A3=0
offX_A2=0
offY_A2=0
offX_A1=0
offY_A1=0
offX_A0=0
offY_A0=0
offX_A=0
offY_A=0
offX_B=0
offY_B=0
offX_C=0
offY_C=0
offX_D=0
offY_D=0
offX_E=0
offY_E=0
RptD_X=0
RptD_Y=100
RptLab=1
SimCmd=
UseNetN=0
LabSize=60
PrintMonochrome=1
ShowSheetReferenceAndTitleBlock=1
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=lib/at91sam7sxxx-au
LibName32=lib/SIMtrace
LibName33=lib/smartcard
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew]
version=1
PadDrlX=0
PadDimH=472
PadDimV=2165
PadDimH=157
PadDimV=197
BoardThickness=630
TxtPcbV=299
TxtPcbH=299
SgPcb45=1
TxtPcbV=800
TxtPcbH=600
TxtModV=600
TxtModH=600
TxtModW=120
VEgarde=100
DrawLar=60
DrawLar=150
EdgeLar=80
TxtLar=120
MSegLar=100
LastNetListRead=SIMtrace.net
[pcbnew/libraries]
LibDir=
LibName1=sockets
LibName2=connect
LibName3=discret
@@ -108,3 +34,23 @@ LibName10=dip_sockets
LibName11=lib/SIMtrace
LibName12=lib/smartcard
LibName13=lib/logo
LibName14=lib/production
LibDir=
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[eeschema]
version=1
LibDir=
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=../pcb/schema/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

File diff suppressed because it is too large Load Diff

View File

@@ -1,4 +1,4 @@
EESchema-DOCLIB Version 2.0 Date: Mo 20 Jun 2011 20:03:28 CEST
EESchema-DOCLIB Version 2.0 Date: So 27 Okt 2013 10:58:11 CET
#
$CMP BC847
F transistors/bipolar/*.*
@@ -8,6 +8,10 @@ $CMP CB3Q3244
D SN74CB3Q3244
$ENDCMP
#
$CMP FPF210X
D Fairchild Semiconductors FPF2108-FPF2110 IC-switch
$ENDCMP
#
$CMP JTAG
D symbole general de connecteur
K CONN

View File

@@ -1,4 +1,4 @@
EESchema-DOCLIB Version 2.0 Date: Mo 20 Jun 2011 20:53:23 CEST
EESchema-DOCLIB Version 2.0 Date: So 27 Okt 2013 12:00:41 CET
#
$CMP BC847
F transistors/bipolar/*.*
@@ -8,6 +8,10 @@ $CMP CB3Q3244
D SN74CB3Q3244
$ENDCMP
#
$CMP FPF210X
D Fairchild Semiconductors FPF2108-FPF2110 IC-switch
$ENDCMP
#
$CMP JTAG
D symbole general de connecteur
K CONN
@@ -21,4 +25,8 @@ $CMP LM3046M
F datasheet/LM3046.pdf
$ENDCMP
#
$CMP SCHOTTKY
D Diode schottky
$ENDCMP
#
#End Doc Library

View File

@@ -1,10 +1,13 @@
EESchema-LIBRARY Version 2.3 Date: Mo 20 Jun 2011 20:53:23 CEST
EESchema-LIBRARY Version 2.3 Date: So 27 Okt 2013 12:00:41 CET
#encoding utf-8
#
# AP7332
#
DEF AP7332 IC 0 40 Y Y 1 F N
F0 "IC" 0 250 60 H V C CNN
F1 "AP7332" 0 -250 60 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
S -300 200 300 -200 0 1 0 N
X VOUT2 1 450 0 150 L 50 50 1 1 w
@@ -21,6 +24,8 @@ ENDDEF
DEF BC847 Q 0 0 Y Y 1 F N
F0 "Q" 0 -150 50 H V R CNN
F1 "BC847" 0 150 50 H V R CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 100 100 N
@@ -39,6 +44,8 @@ ENDDEF
DEF CB3Q3244 IC 0 0 Y Y 9 L N
F0 "IC" -150 200 60 H V C CNN
F1 "CB3Q3244" -300 -150 60 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
C -85 0 10 1 1 0 N
P 3 1 1 0 -200 0 -250 0 -250 0 N
@@ -138,6 +145,8 @@ ENDDEF
DEF DEBUG P 0 30 Y Y 1 F N
F0 "P" 0 350 60 H V C CNN
F1 "DEBUG" 200 0 60 V V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
S -100 300 150 -300 0 1 0 N
X GND 1 -350 250 250 R 60 60 1 1 W I
@@ -154,6 +163,8 @@ ENDDEF
DEF FLASH_SPI U 0 40 Y Y 1 F N
F0 "U" 0 300 60 H V C CNN
F1 "FLASH_SPI" 0 -300 60 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
S -350 250 350 -250 0 1 0 N
X /CS 1 -600 150 250 R 60 60 1 1 I
@@ -172,6 +183,8 @@ ENDDEF
DEF FPF200X IC 0 40 Y Y 1 F N
F0 "IC" 0 350 60 H V C CNN
F1 "FPF200X" 0 250 60 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
S -250 200 250 -350 0 1 0 N
X VOUT 1 400 100 150 L 50 50 1 1 w
@@ -182,11 +195,30 @@ X VIN 5 -400 100 150 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# FPF210X
#
DEF FPF210X IC 0 40 Y Y 1 F N
F0 "IC" 0 350 60 H V C CNN
F1 "FPF210X" 0 250 60 H V C CNN
F2 "SOT23-5" 0 450 60 H I C CNN
F3 "https://www.fairchildsemi.com/ds/FP/FPF2110.pdf" 0 -600 60 H I C CNN
DRAW
S -250 200 250 -350 0 1 0 N
X VIN 1 -400 100 150 R 50 50 1 1 W
X GND 2 0 -500 150 U 50 50 1 1 W
X ON 3 -400 -100 150 R 50 50 1 1 I
X FLAGB 4 400 -100 150 L 50 50 1 1 I
X VOUT 5 400 100 150 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# JACK
#
DEF JACK J 0 0 Y Y 1 F N
F0 "J" 0 150 50 H V L BNN
F1 "JACK" -50 -200 50 H V L BNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
P 2 1 0 0 -100 100 -100 50 N
P 2 1 0 0 0 -40 -30 -100 N
@@ -209,6 +241,8 @@ ENDDEF
DEF JACK_2.5 J 0 0 Y Y 1 F N
F0 "J" -50 150 50 H V L BNN
F1 "JACK_2.5" -150 -200 50 H V L BNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
P 2 1 0 0 -150 100 -150 50 N
P 3 0 1 0 -150 100 250 100 250 100 N
@@ -226,6 +260,8 @@ ENDDEF
DEF JTAG P 0 10 Y Y 1 F N
F0 "P" 0 550 60 H V C CNN
F1 "JTAG" 0 -550 50 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
S -150 500 150 -500 0 1 0 N
X VREF 1 -450 450 300 R 60 30 1 1 P I
@@ -256,6 +292,8 @@ ENDDEF
DEF LM3046 Q 0 40 Y Y 5 F N
F0 "Q" 0 225 50 H V C CNN
F1 "LM3046" 0 -175 50 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
$FPLIST
SO14E
$ENDFPLIST
@@ -290,6 +328,8 @@ ENDDEF
DEF LM3046M Q 0 40 Y Y 5 F N
F0 "Q" 0 225 50 H V C CNN
F1 "LM3046M" 0 -175 50 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
$FPLIST
SO14E
$ENDFPLIST
@@ -324,6 +364,8 @@ ENDDEF
DEF QS3244 IC 0 0 Y Y 9 L N
F0 "IC" -150 200 60 H V C CNN
F1 "QS3244" -225 -175 60 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
C -85 0 10 1 1 0 N
P 3 1 1 0 -200 0 -250 0 -250 0 N
@@ -423,6 +465,8 @@ ENDDEF
DEF QS3245 IC 0 0 Y Y 9 L N
F0 "IC" -150 200 60 H V C CNN
F1 "QS3245" -225 -175 60 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
C -85 0 10 1 1 0 N
P 3 1 1 0 0 0 -75 0 -75 0 N
@@ -514,6 +558,8 @@ ENDDEF
DEF SC120 IC 0 40 Y Y 1 F N
F0 "IC" 0 350 60 H V C CNN
F1 "SC120" 0 -350 60 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
S -250 250 250 -250 0 1 0 N
X IN 1 -500 150 250 R 60 60 1 1 W
@@ -525,11 +571,32 @@ X EN 6 -500 0 250 R 60 60 1 1 I
ENDDRAW
ENDDEF
#
# SCHOTTKY
#
DEF SCHOTTKY D 0 40 Y N 1 F N
F0 "D" 0 100 40 H V C CNN
F1 "SCHOTTKY" 0 -100 40 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
$FPLIST
D?
S*
$ENDFPLIST
DRAW
P 3 0 1 0 -50 50 50 0 -50 -50 F
P 6 0 1 8 75 25 75 50 50 50 50 -50 25 -50 25 -25 N
X K 1 200 0 150 L 40 40 1 1 P
X A 2 -200 0 150 R 40 40 1 1 P
ENDDRAW
ENDDEF
#
# TPS736XX
#
DEF TPS736XX IC 0 40 Y Y 1 F N
F0 "IC" 0 450 60 H V C CNN
F1 "TPS736XX" 0 350 60 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
S -300 300 300 -50 0 1 0 N
X IN 1 -450 200 150 R 60 60 1 1 W
@@ -547,6 +614,7 @@ DEF USB-B_MINI J 0 40 Y Y 1 F N
F0 "J" 50 450 50 H V L BNN
F1 "USB-B_MINI" -100 -450 50 H V L BNN
F2 "~" 0 150 50 H I C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
P 2 1 0 0 -100 250 -100 -250 N
P 2 1 0 0 -50 -300 0 -300 N
@@ -581,6 +649,8 @@ ENDDEF
DEF USBUF IC 0 40 Y Y 1 F N
F0 "IC" 0 400 60 H V C CNN
F1 "USBUF" 0 -300 60 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
S -250 300 250 -200 0 1 0 N
X D1 1 -400 200 150 R 60 60 1 1 B

View File

@@ -1,26 +1,24 @@
PCBNEW-LibModule-V1 Fr 01 Jul 2011 13:26:08 CEST
PCBNEW-LibModule-V1 Thu 03 Nov 2011 11:53:58 CET
# encoding utf-8
$INDEX
JACK2.5_SJ1-2503A
USB-MINI-B_54819-0519
$EndINDEX
$INDEX
CAP_AVE_E
FFC_REBELSIM
JACK2.5_SJ-2523-SMT
JACK2.5_SJ1-2503A
PUSH_BUTTON
SC_ID0
SC_ID000
SOD123
SOT223-6
USB_MINI-B
pin_array_10x2
FFC_REBELSIM
PUSH_BUTTON
SOIC8
SOT223-6
SOT23_BC847
USB-MINI-B_UX60
SSOP20_BDQ
SOT26
SOT353
JACK2.5_SJ-2523-SMT
SSOP20_BDQ
USB-MINI-B_54819-0519
USB-MINI-B_UX60
USB_MINI-B
pin_array_10x2
$EndINDEX
$MODULE CAP_AVE_E
Po 0 0 0 15 4CFCEE9A 00000000 ~~
@@ -324,167 +322,57 @@ Ne 0 ""
Po 630 -2402
$EndPAD
$EndMODULE USB_MINI-B
$MODULE pin_array_10x2
Po 0 0 0 15 4DCBEF17 00000000 ~~
Li pin_array_10x2
Cd Double rangee de contacts 2 x 12 pins
Kw CONN
$MODULE JACK_2.5
Po 0 0 0 15 4DCBED33 00000000 ~~
Li JACK_2.5
Sc 00000000
AR
Op 0 0 0
T0 0 -1500 400 400 0 100 N V 21 N"PIN_ARRAY_10X2"
T1 0 1500 400 400 0 80 N V 21 N"Val**"
DS 4000 1000 -6000 1000 150 21
DS 4000 -1000 -6000 -1000 150 21
DS -6000 -1000 -6000 1000 150 21
DS 4002 1000 4002 -1000 150 21
T0 0 2677 600 600 0 120 N V 21 N"JACK_2.5"
T1 10 -2697 600 600 0 120 N V 21 N"VAL**"
DS -2362 -787 -2953 -787 150 21
DS -2953 -787 -2953 787 150 21
DS -2953 787 -2362 787 150 21
DS -2362 -984 2362 -984 150 21
DS 2362 -984 2362 984 150 21
DS 2362 984 -2362 984 150 21
DS -2362 984 -2362 -984 150 21
$PAD
Sh "1" R 600 600 0 0 0
Dr 320 0 0
At STD N 00E0FFFF
Sh "1" R 945 1161 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -5500 500
Po -1693 1289
$EndPAD
$PAD
Sh "2" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Sh "3" R 945 1161 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -5500 -500
Po -630 -1181
$EndPAD
$PAD
Sh "3" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Sh "2" R 945 1043 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -4500 500
Po 2126 1348
$EndPAD
$PAD
Sh "4" C 600 600 0 0 0
Dr 400 0 0
Sh "" C 394 394 0 0 0
Dr 394 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -4500 -500
Po -1181 0
$EndPAD
$PAD
Sh "5" C 600 600 0 0 0
Dr 400 0 0
Sh "" C 394 394 0 0 0
Dr 394 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -3500 500
Po 1181 0
$EndPAD
$PAD
Sh "6" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -3500 -500
$EndPAD
$PAD
Sh "7" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -2500 500
$EndPAD
$PAD
Sh "8" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -2500 -500
$EndPAD
$PAD
Sh "9" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -1500 500
$EndPAD
$PAD
Sh "10" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -1500 -500
$EndPAD
$PAD
Sh "11" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -500 500
$EndPAD
$PAD
Sh "12" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -500 -500
$EndPAD
$PAD
Sh "13" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 500 500
$EndPAD
$PAD
Sh "14" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 500 -500
$EndPAD
$PAD
Sh "15" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 1500 500
$EndPAD
$PAD
Sh "16" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 1500 -500
$EndPAD
$PAD
Sh "17" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2500 500
$EndPAD
$PAD
Sh "18" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2500 -500
$EndPAD
$PAD
Sh "19" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 3500 500
$EndPAD
$PAD
Sh "20" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 3500 -500
$EndPAD
$SHAPE3D
Na "pin_array/pins_array_12x2.wrl"
Sc 1.000000 1.000000 1.000000
Of 0.000000 0.000000 0.000000
Ro 0.000000 0.000000 0.000000
$EndSHAPE3D
$EndMODULE pin_array_10x2
$EndMODULE JACK_2.5
$MODULE FFC_REBELSIM
Po 0 0 0 15 4DCBF7BC 00000000 ~~
Li FFC_REBELSIM
@@ -1150,189 +1038,165 @@ Ne 0 ""
Po 256 -374
$EndPAD
$EndMODULE SOT353
$MODULE JACK2.5_SJ-2523-SMT
Po 0 0 0 15 4DCBED33 00000000 ~~
Li JACK2.5_SJ-2523-SMT
Sc 00000000
AR
Op 0 0 0
T0 0 2677 600 600 0 120 N V 21 N "JACK2.5_SJ-2523-SMT"
T1 10 -2697 600 600 0 120 N V 21 N "VAL**"
DS -2362 -787 -2953 -787 150 21
DS -2953 -787 -2953 787 150 21
DS -2953 787 -2362 787 150 21
DS -2362 -984 2362 -984 150 21
DS 2362 -984 2362 984 150 21
DS 2362 984 -2362 984 150 21
DS -2362 984 -2362 -984 150 21
$PAD
Sh "1" R 945 1161 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -1693 1289
$EndPAD
$PAD
Sh "3" R 945 1161 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -630 -1181
$EndPAD
$PAD
Sh "2" R 945 1043 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 2126 1348
$EndPAD
$PAD
Sh "" C 394 394 0 0 0
Dr 394 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -1181 0
$EndPAD
$PAD
Sh "" C 394 394 0 0 0
Dr 394 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 1181 0
$EndPAD
$EndMODULE JACK2.5_SJ-2523-SMT
$MODULE JACK2.5_SJ1-2503A
Po 0 0 0 15 4E0DAD20 00000000 ~~
Li JACK2.5_SJ1-2503A
Sc 00000000
AR
Op 0 0 0
T0 0 1772 600 600 0 120 N V 21 N "JACK2.5_SJ1-2503A"
T1 0 -1614 600 600 0 120 N V 21 N "VAL**"
DS -1378 -787 -2559 -787 100 21
DS -2559 -787 -2559 787 100 21
DS -2559 787 -1378 787 100 21
DS -1378 -984 1693 -984 100 21
DS 1693 -984 1693 984 100 21
DS 1693 984 -1378 984 100 21
DS -1378 984 -1378 -984 100 21
$PAD
Sh "" C 472 472 0 0 0
Dr 472 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 0 0
$EndPAD
$PAD
Sh "1" R 276 591 0 0 0
Dr 118 0 0 O 118 472
At STD N 00E00001
Ne 0 ""
Po -945 0
$EndPAD
$PAD
Sh "2" R 591 276 0 0 0
Dr 472 0 0 O 472 118
At STD N 00E00001
Ne 0 ""
Po 984 -728
$EndPAD
$PAD
Sh "2" R 591 276 0 0 0
Dr 472 0 0 O 472 118
At STD N 00E00001
Ne 0 ""
Po 984 728
$EndPAD
$PAD
Sh "3" R 276 591 0 0 0
Dr 118 0 0 O 118 472
At STD N 00E0FFFF
Ne 0 ""
Po 1772 0
$EndPAD
$EndMODULE JACK2.5_SJ1-2503A
$MODULE USB-MINI-B_54819-0519
Po 0 0 0 15 4E0DAECA 00000000 ~~
Li USB-MINI-B_54819-0519
$MODULE PIN_ARRAY_10X2
Po 0 0 0 15 4DCBEF17 00000000 ~~
Li PIN_ARRAY_10X2
Cd Double rangee de contacts 2 x 12 pins
Kw CONN
Sc 00000000
AR
Op 0 0 0
T0 0 2657 600 600 0 120 N V 21 N "USB-MINI-B_54819-0519"
T1 0 -2520 600 600 0 120 N V 21 N "VAL**"
DS -787 -1516 2756 -1516 100 21
DS 2756 -1516 2756 1516 100 21
DS 2756 1516 -787 1516 100 21
DS -787 1516 -787 -1516 100 21
T0 0 -1500 400 400 0 100 N V 21 N "PIN_ARRAY_10X2"
T1 0 1500 400 400 0 80 N V 21 N "Val**"
DS 4000 1000 -6000 1000 150 21
DS 4000 -1000 -6000 -1000 150 21
DS -6000 -1000 -6000 1000 150 21
DS 4002 1000 4002 -1000 150 21
$PAD
Sh "" R 472 2441 0 0 0
Dr 0 0 0
At SMD N 00008000
Sh "1" R 600 600 0 0 0
Dr 320 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 236 0
Po -5500 500
$EndPAD
$PAD
Sh "" R 984 551 0 0 0
Dr 0 0 0
At SMD N 00008000
Sh "2" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2461 1457
Po -5500 -500
$EndPAD
$PAD
Sh "" R 984 551 0 0 0
Dr 0 0 0
At SMD N 00008000
Sh "3" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2461 -1457
Po -4500 500
$EndPAD
$PAD
Sh "" O 1063 669 0 0 0
Dr 748 0 0 O 748 354
At STD N 00E00001
Sh "4" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 689 -1437
Po -4500 -500
$EndPAD
$PAD
Sh "" O 1063 669 0 0 0
Dr 748 0 0 O 748 354
At STD N 00E00001
Sh "5" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 689 1437
Po -3500 500
$EndPAD
$PAD
Sh "1" O 650 433 0 0 0
Dr 276 108 0
At STD N 00E00001
Sh "6" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2677 -630
Po -3500 -500
$EndPAD
$PAD
Sh "3" O 650 433 0 0 0
Dr 276 108 0
At STD N 00E00001
Sh "7" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2677 0
Po -2500 500
$EndPAD
$PAD
Sh "5" O 650 433 0 0 0
Dr 276 108 0
At STD N 00E00001
Sh "8" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2677 630
Po -2500 -500
$EndPAD
$PAD
Sh "2" O 650 433 0 0 0
Dr 276 -108 0
At STD N 00E00001
Sh "9" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2205 -315
Po -1500 500
$EndPAD
$PAD
Sh "4" O 650 433 0 0 0
Dr 276 -108 0
At STD N 00E00001
Sh "10" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2205 315
Po -1500 -500
$EndPAD
$EndMODULE USB-MINI-B_54819-0519
$PAD
Sh "11" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -500 500
$EndPAD
$PAD
Sh "12" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -500 -500
$EndPAD
$PAD
Sh "13" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 500 500
$EndPAD
$PAD
Sh "14" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 500 -500
$EndPAD
$PAD
Sh "15" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 1500 500
$EndPAD
$PAD
Sh "16" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 1500 -500
$EndPAD
$PAD
Sh "17" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2500 500
$EndPAD
$PAD
Sh "18" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2500 -500
$EndPAD
$PAD
Sh "19" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 3500 500
$EndPAD
$PAD
Sh "20" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 3500 -500
$EndPAD
$SHAPE3D
Na "pin_array/pins_array_12x2.wrl"
Sc 1.000000 1.000000 1.000000
Of 0.000000 0.000000 0.000000
Ro 0.000000 0.000000 0.000000
$EndSHAPE3D
$EndMODULE PIN_ARRAY_10X2
$EndLIBRARY

File diff suppressed because it is too large Load Diff

View File

@@ -0,0 +1,104 @@
PCBNEW-LibModule-V1 Fr 01 Jul 2011 10:24:13 CEST
# encoding utf-8
$INDEX
SOC008_WIDE
SMB_STPS340U
$EndINDEX
$MODULE SOC008_WIDE
Po 0 0 0 15 4E0CEDCE 4E0D83AE ~~
Li SOC008_WIDE
Sc 4E0D83AE
AR SOC008_WIDE
Op 0 0 0
T0 0 2441 600 600 0 120 N V 21 N "SOC008_WIDE"
T1 0 -2205 600 600 0 120 N V 21 N "VAL**"
DC 787 -787 866 -787 100 21
DS -1043 -1043 1043 -1043 100 21
DS 1043 -1043 1043 1043 100 21
DS 1043 1043 -1043 1043 100 21
DS -1043 1043 -1043 -1043 100 21
$PAD
Sh "4" R 197 379 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -750 -1455
$EndPAD
$PAD
Sh "1" R 197 379 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 750 -1455
$EndPAD
$PAD
Sh "2" R 197 379 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 250 -1455
$EndPAD
$PAD
Sh "3" R 197 379 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -250 -1455
$EndPAD
$PAD
Sh "8" R 197 379 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 750 1455
$EndPAD
$PAD
Sh "7" R 197 379 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 250 1455
$EndPAD
$PAD
Sh "6" R 197 379 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -250 1454
$EndPAD
$PAD
Sh "5" R 197 379 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -750 1455
$EndPAD
$EndMODULE SOC008_WIDE
$MODULE SMB_STPS340U
Po 0 0 0 15 4E0CCA27 00000000 ~~
Li SMB_STPS340U
Sc 00000000
AR
Op 0 0 0
T0 0 1240 600 600 0 120 N V 21 N "SMB_STPS340U"
T1 0 -1102 600 600 0 120 N V 21 N "VAL**"
DS -846 -709 846 -709 100 21
DS 846 -709 846 709 100 21
DS 846 709 -846 709 100 21
DS -846 709 -846 -709 100 21
$PAD
Sh "1" R 598 906 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -839 0
$EndPAD
$PAD
Sh "2" R 598 906 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 839 0
$EndPAD
$EndMODULE SMB_STPS340U
$EndLIBRARY

View File

@@ -1,15 +1,12 @@
PCBNEW-LibModule-V1 Do 07 Jul 2011 23:16:30 CEST
PCBNEW-LibModule-V1 Sa 13 Aug 2011 15:51:03 CEST
# encoding utf-8
$INDEX
FFC
SAM_FCI
SIM
FFC
SIM_LIGHT
$EndINDEX
$INDEX
SIM_AMPHENOL
SIM
FFC
SIM_LIGHT
microSIM_card
$EndINDEX
$MODULE SIM_AMPHENOL
Po 0 0 0 15 4DFF4BD6 00000000 ~~
@@ -502,4 +499,74 @@ Po 4969 3417
Le 48
$EndPAD
$EndMODULE SIM_LIGHT
$MODULE microSIM_card
Po 0 0 0 15 4E468144 00000000 ~~
Li microSIM_card
Sc 00000000
AR
Op 0 0 0
T0 0 3150 600 600 0 120 N V 21 N "microSIM_card"
T1 0 -3051 600 600 0 120 N V 21 N "VAL**"
DS -2953 -2362 2953 -2362 100 28
DS 2953 -2362 2953 1378 100 28
DS 2953 1378 1969 2362 100 28
DS 1969 2362 -2953 2362 100 28
DS -2953 2362 -2953 -2362 100 28
$PAD
Sh "C1" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -1713 -1500
$EndPAD
$PAD
Sh "C2" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -1713 -500
$EndPAD
$PAD
Sh "C3" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -1713 500
$EndPAD
$PAD
Sh "C4" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -1713 1500
$EndPAD
$PAD
Sh "C5" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1287 -1500
$EndPAD
$PAD
Sh "C6" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1287 -500
$EndPAD
$PAD
Sh "C7" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1287 500
$EndPAD
$PAD
Sh "C8" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1287 1500
$EndPAD
$EndMODULE microSIM_card
$EndLIBRARY

View File

@@ -0,0 +1,59 @@
Cmp-Mod V01 Created by CvPCB (2011-07-19)-testing date = Sa 13 Aug 2011 15:54:00 CEST
BeginCmp
TimeStamp = /4E158ACC;
Reference = FFC1;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E159114;
Reference = FFC2;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E15911B;
Reference = FFC3;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E159134;
Reference = FFC4;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E158AC1;
Reference = SIM1;
ValeurCmp = ISO7816_CARD;
IdModule = microSIM_card;
EndCmp
BeginCmp
TimeStamp = /4E159115;
Reference = SIM2;
ValeurCmp = ISO7816_CARD;
IdModule = microSIM_card;
EndCmp
BeginCmp
TimeStamp = /4E15911A;
Reference = SIM3;
ValeurCmp = ISO7816_CARD;
IdModule = microSIM_card;
EndCmp
BeginCmp
TimeStamp = /4E159135;
Reference = SIM4;
ValeurCmp = ISO7816_CARD;
IdModule = microSIM_card;
EndCmp
EndListe

View File

@@ -0,0 +1,76 @@
# EESchema Netlist Version 1.1 created Sa 13 Aug 2011 15:54:00 CEST
(
( /4E158ACC FFC FFC1 FFC
( 1 /VCC1 )
( 2 /RST1 )
( 3 /CLK1 )
( 4 /I-O1 )
( 5 /VPP1 )
( 6 /GND1 )
)
( /4E159114 FFC FFC2 FFC
( 1 /VCC2 )
( 2 /RST2 )
( 3 /CLK2 )
( 4 /I-O2 )
( 5 /VPP2 )
( 6 /GND2 )
)
( /4E15911B FFC FFC3 FFC
( 1 /VCC3 )
( 2 /RST3 )
( 3 /CLK3 )
( 4 /I-O3 )
( 5 /VPP3 )
( 6 /GND3 )
)
( /4E159134 FFC FFC4 FFC
( 1 /VCC4 )
( 2 /RST4 )
( 3 /CLK4 )
( 4 /I-O4 )
( 5 /VPP4 )
( 6 /GND4 )
)
( /4E158AC1 microSIM_card SIM1 ISO7816_CARD
( C1 /VCC1 )
( C2 /RST1 )
( C3 /CLK1 )
( C4 ? )
( C5 /GND1 )
( C6 /VPP1 )
( C7 /I-O1 )
( C8 ? )
)
( /4E159115 microSIM_card SIM2 ISO7816_CARD
( C1 /VCC2 )
( C2 /RST2 )
( C3 /CLK2 )
( C4 ? )
( C5 /GND2 )
( C6 /VPP2 )
( C7 /I-O2 )
( C8 ? )
)
( /4E15911A microSIM_card SIM3 ISO7816_CARD
( C1 /VCC3 )
( C2 /RST3 )
( C3 /CLK3 )
( C4 ? )
( C5 /GND3 )
( C6 /VPP3 )
( C7 /I-O3 )
( C8 ? )
)
( /4E159135 microSIM_card SIM4 ISO7816_CARD
( C1 /VCC4 )
( C2 /RST4 )
( C3 /CLK4 )
( C4 ? )
( C5 /GND4 )
( C6 /VPP4 )
( C7 /I-O4 )
( C8 ? )
)
)
*

View File

@@ -0,0 +1,86 @@
update=Sa 13 Aug 2011 15:53:03 CEST
last_client=cvpcb
[eeschema]
version=1
LibDir=
NetFmt=1
HPGLSpd=20
HPGLDm=15
HPGLNum=1
offX_A4=0
offY_A4=0
offX_A3=0
offY_A3=0
offX_A2=0
offY_A2=0
offX_A1=0
offY_A1=0
offX_A0=0
offY_A0=0
offX_A=0
offY_A=0
offX_B=0
offY_B=0
offX_C=0
offY_C=0
offX_D=0
offY_D=0
offX_E=0
offY_E=0
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=lib/SIMtrace
LibName32=lib/smartcard
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew]
[pcbnew/libraries]
LibName1=sockets
LibName2=connect
LibName3=discret
LibName4=pin_array
LibName5=divers
LibName6=libcms
LibName7=display
LibName8=valves
LibName9=led
LibName10=dip_sockets
LibName11=lib/SIMtrace
LibName12=lib/smartcard
LibDir=

View File

@@ -0,0 +1,367 @@
EESchema Schematic File Version 2 date Do 07 Jul 2011 13:03:38 CEST
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:smartcard
EELAYER 25 0
EELAYER END
$Descr A4 11700 8267
encoding utf-8
Sheet 1 1
Title "noname.sch"
Date "7 jul 2011"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Label 4450 1850 0 60 ~ 0
I-O2
Text Label 4450 1950 0 60 ~ 0
VPP2
Text Label 4450 2050 0 60 ~ 0
GND2
Text Label 3450 1850 0 60 ~ 0
CLK2
Text Label 3450 1950 0 60 ~ 0
RST2
Text Label 3450 2050 0 60 ~ 0
VCC2
Text Label 2550 1850 0 60 ~ 0
I-O1
Text Label 2550 1950 0 60 ~ 0
VPP1
Text Label 2550 2050 0 60 ~ 0
GND1
$Comp
L ISO7816_CARD SIM4
U 1 1 4E159135
P 7850 1250
F 0 "SIM4" H 7850 1500 60 0000 C CNN
F 1 "ISO7816_CARD" H 7850 1000 60 0000 C CNN
1 7850 1250
1 0 0 -1
$EndComp
$Comp
L FFC FFC4
U 1 1 4E159134
P 7850 2450
F 0 "FFC4" H 7900 2800 60 0000 C CNN
F 1 "FFC" V 8050 2450 60 0000 C CNN
1 7850 2450
0 -1 1 0
$EndComp
Text Label 7250 1850 0 60 ~ 0
CLK4
Text Label 7250 1950 0 60 ~ 0
RST4
Text Label 7250 2050 0 60 ~ 0
VCC4
Wire Wire Line
8650 1200 8650 1950
Wire Wire Line
7900 1850 8600 1850
Wire Wire Line
7900 1850 7900 2100
Wire Wire Line
7700 2100 7700 1950
Wire Wire Line
7700 1950 7050 1950
Wire Wire Line
7100 1300 7100 1850
Wire Wire Line
8400 1300 8600 1300
Wire Wire Line
8100 2100 8100 2050
Wire Wire Line
8100 2050 8700 2050
Wire Wire Line
8700 2050 8700 1100
Wire Wire Line
8700 1100 8400 1100
Wire Wire Line
7300 1200 7050 1200
Wire Wire Line
7300 1100 7000 1100
Wire Wire Line
7000 1100 7000 2050
Wire Wire Line
7000 2050 7600 2050
Wire Wire Line
7600 2050 7600 2100
Wire Wire Line
7100 1300 7300 1300
Wire Wire Line
8650 1200 8400 1200
Wire Wire Line
7100 1850 7800 1850
Wire Wire Line
7800 1850 7800 2100
Wire Wire Line
7050 1200 7050 1950
Wire Wire Line
8600 1300 8600 1850
Wire Wire Line
8000 2100 8000 1950
Wire Wire Line
8000 1950 8650 1950
Text Label 8250 1850 0 60 ~ 0
I-O4
Text Label 8250 1950 0 60 ~ 0
VPP4
Text Label 8250 2050 0 60 ~ 0
GND4
NoConn ~ 8400 1400
NoConn ~ 7300 1400
NoConn ~ 5400 1400
NoConn ~ 6500 1400
Text Label 6350 2050 0 60 ~ 0
GND3
Text Label 6350 1950 0 60 ~ 0
VPP3
Text Label 6350 1850 0 60 ~ 0
I-O3
Wire Wire Line
6100 1950 6750 1950
Wire Wire Line
6100 1950 6100 2100
Wire Wire Line
6700 1300 6700 1850
Wire Wire Line
5150 1200 5150 1950
Wire Wire Line
5900 2100 5900 1850
Wire Wire Line
5900 1850 5200 1850
Wire Wire Line
6500 1200 6750 1200
Wire Wire Line
5400 1300 5200 1300
Wire Wire Line
5700 2100 5700 2050
Wire Wire Line
5700 2050 5100 2050
Wire Wire Line
5100 2050 5100 1100
Wire Wire Line
5100 1100 5400 1100
Wire Wire Line
5150 1200 5400 1200
Wire Wire Line
6500 1100 6800 1100
Wire Wire Line
6800 1100 6800 2050
Wire Wire Line
6800 2050 6200 2050
Wire Wire Line
6200 2050 6200 2100
Wire Wire Line
6700 1300 6500 1300
Wire Wire Line
5200 1300 5200 1850
Wire Wire Line
5150 1950 5800 1950
Wire Wire Line
5800 1950 5800 2100
Wire Wire Line
6000 2100 6000 1850
Wire Wire Line
6000 1850 6700 1850
Wire Wire Line
6750 1200 6750 1950
Text Label 5350 2050 0 60 ~ 0
VCC3
Text Label 5350 1950 0 60 ~ 0
RST3
Text Label 5350 1850 0 60 ~ 0
CLK3
$Comp
L FFC FFC3
U 1 1 4E15911B
P 5950 2450
F 0 "FFC3" H 6000 2800 60 0000 C CNN
F 1 "FFC" V 6150 2450 60 0000 C CNN
1 5950 2450
0 -1 1 0
$EndComp
$Comp
L ISO7816_CARD SIM3
U 1 1 4E15911A
P 5950 1250
F 0 "SIM3" H 5950 1500 60 0000 C CNN
F 1 "ISO7816_CARD" H 5950 1000 60 0000 C CNN
1 5950 1250
1 0 0 -1
$EndComp
$Comp
L ISO7816_CARD SIM2
U 1 1 4E159115
P 4050 1250
F 0 "SIM2" H 4050 1500 60 0000 C CNN
F 1 "ISO7816_CARD" H 4050 1000 60 0000 C CNN
1 4050 1250
1 0 0 -1
$EndComp
$Comp
L FFC FFC2
U 1 1 4E159114
P 4050 2450
F 0 "FFC2" H 4100 2800 60 0000 C CNN
F 1 "FFC" V 4250 2450 60 0000 C CNN
1 4050 2450
0 -1 1 0
$EndComp
Wire Wire Line
4850 1200 4850 1950
Wire Wire Line
4100 1850 4800 1850
Wire Wire Line
4100 1850 4100 2100
Wire Wire Line
3900 2100 3900 1950
Wire Wire Line
3900 1950 3250 1950
Wire Wire Line
3300 1300 3300 1850
Wire Wire Line
4600 1300 4800 1300
Wire Wire Line
4300 2100 4300 2050
Wire Wire Line
4300 2050 4900 2050
Wire Wire Line
4900 2050 4900 1100
Wire Wire Line
4900 1100 4600 1100
Wire Wire Line
3500 1200 3250 1200
Wire Wire Line
3500 1100 3200 1100
Wire Wire Line
3200 1100 3200 2050
Wire Wire Line
3200 2050 3800 2050
Wire Wire Line
3800 2050 3800 2100
Wire Wire Line
3300 1300 3500 1300
Wire Wire Line
4850 1200 4600 1200
Wire Wire Line
3300 1850 4000 1850
Wire Wire Line
4000 1850 4000 2100
Wire Wire Line
3250 1200 3250 1950
Wire Wire Line
4800 1300 4800 1850
Wire Wire Line
4200 2100 4200 1950
Wire Wire Line
4200 1950 4850 1950
NoConn ~ 4600 1400
NoConn ~ 3500 1400
NoConn ~ 1600 1400
NoConn ~ 2700 1400
Wire Wire Line
2300 1950 2950 1950
Wire Wire Line
2300 1950 2300 2100
Wire Wire Line
2900 1300 2900 1850
Wire Wire Line
1350 1200 1350 1950
Wire Wire Line
2100 2100 2100 1850
Wire Wire Line
2100 1850 1400 1850
Wire Wire Line
2700 1200 2950 1200
Wire Wire Line
1600 1300 1400 1300
Wire Wire Line
1900 2100 1900 2050
Wire Wire Line
1900 2050 1300 2050
Wire Wire Line
1300 2050 1300 1100
Wire Wire Line
1300 1100 1600 1100
Wire Wire Line
1350 1200 1600 1200
Wire Wire Line
2700 1100 3000 1100
Wire Wire Line
3000 1100 3000 2050
Wire Wire Line
3000 2050 2400 2050
Wire Wire Line
2400 2050 2400 2100
Wire Wire Line
2900 1300 2700 1300
Wire Wire Line
1400 1300 1400 1850
Wire Wire Line
1350 1950 2000 1950
Wire Wire Line
2000 1950 2000 2100
Wire Wire Line
2200 2100 2200 1850
Wire Wire Line
2200 1850 2900 1850
Wire Wire Line
2950 1200 2950 1950
Text Label 1550 2050 0 60 ~ 0
VCC1
Text Label 1550 1950 0 60 ~ 0
RST1
Text Label 1550 1850 0 60 ~ 0
CLK1
$Comp
L FFC FFC1
U 1 1 4E158ACC
P 2150 2450
F 0 "FFC1" H 2200 2800 60 0000 C CNN
F 1 "FFC" V 2350 2450 60 0000 C CNN
1 2150 2450
0 -1 1 0
$EndComp
$Comp
L ISO7816_CARD SIM1
U 1 1 4E158AC1
P 2150 1250
F 0 "SIM1" H 2150 1500 60 0000 C CNN
F 1 "ISO7816_CARD" H 2150 1000 60 0000 C CNN
1 2150 1250
1 0 0 -1
$EndComp
$EndSCHEMATC

View File

@@ -0,0 +1,461 @@
PCBNEW-BOARD Version 1 date Sat 25 Feb 2012 03:47:15 PM CET
# Created by Pcbnew(2011-07-02 BZR 3034)-testing
$GENERAL
encoding utf-8
LayerCount 2
Ly 1FFF8001
EnabledLayers 1FFF8001
Links 6
NoConn 0
Di 23724 20224 48876 37216
Ndraw 8
Ntrack 44
Nzone 0
BoardThickness 630
Nmodule 2
Nnets 7
$EndGENERAL
$SHEETDESCR
Sheet A4 11700 8267
Title ""
Date "25 feb 2012"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndSHEETDESCR
$SETUP
InternalUnit 0.000100 INCH
Layers 2
Layer[0] Back signal
Layer[15] Front signal
TrackWidth 236
TrackClearence 100
ZoneClearence 200
TrackMinWidth 80
DrawSegmWidth 150
EdgeSegmWidth 150
ViaSize 350
ViaDrill 236
ViaMinSize 350
ViaMinDrill 200
MicroViaSize 200
MicroViaDrill 50
MicroViasAllowed 0
MicroViaMinSize 200
MicroViaMinDrill 50
TextPcbWidth 120
TextPcbSize 600 800
EdgeModWidth 150
TextModSize 600 600
TextModWidth 120
PadSize 600 600
PadDrill 320
Pad2MaskClearance 100
AuxiliaryAxisOrg 23800 36600
PcbPlotParams (pcbplotparams (layerselection 15761409) (usegerberextensions true) (excludeedgelayer false) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk true) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory /sunbeam/home/laforge/projects/git/simtrace/hardware/pcb/gerber/))
$EndSETUP
$EQUIPOT
Na 0 ""
St ~
$EndEQUIPOT
$EQUIPOT
Na 1 "N-000001"
St ~
$EndEQUIPOT
$EQUIPOT
Na 2 "N-000002"
St ~
$EndEQUIPOT
$EQUIPOT
Na 3 "N-000003"
St ~
$EndEQUIPOT
$EQUIPOT
Na 4 "N-000005"
St ~
$EndEQUIPOT
$EQUIPOT
Na 5 "N-000007"
St ~
$EndEQUIPOT
$EQUIPOT
Na 6 "N-000008"
St ~
$EndEQUIPOT
$NCLASS
Name "Default"
Desc "This is the default net class."
Clearance 100
TrackWidth 236
ViaDia 350
ViaDrill 236
uViaDia 200
uViaDrill 50
AddNet ""
AddNet "N-000001"
AddNet "N-000002"
AddNet "N-000003"
AddNet "N-000005"
AddNet "N-000007"
AddNet "N-000008"
$EndNCLASS
$MODULE SAM_FCI
Po 36300 28400 0 15 4E0DAC7D 4F3FC169 ~~
Li SAM_FCI
Sc 4F3FC169
AR /4F3FBFC0
Op 0 0 0
T0 0 1102 600 600 0 120 N V 21 N "P2"
T1 0 -984 600 600 0 120 N V 21 N "ISO7816_NO"
DS -12205 -7874 12205 -7874 100 21
DS 12205 -7874 12205 7874 100 21
DS 12205 7874 -12205 7874 100 21
DS -12205 7874 -12205 -7874 100 21
$PAD
Sh "" C 866 866 0 0 0
Dr 866 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -11417 0
Le 95
$EndPAD
$PAD
Sh "" C 866 866 0 0 0
Dr 866 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 11417 0
Le 111
$EndPAD
$PAD
Sh "" C 1299 1299 0 0 0
Dr 1299 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -11417 -3937
Le 400128
$EndPAD
$PAD
Sh "" C 1299 1299 0 0 0
Dr 1299 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -11417 3937
Le 373504
$EndPAD
$PAD
Sh "" C 1299 1299 0 0 0
Dr 1299 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 11417 -3937
Le 373760
$EndPAD
$PAD
Sh "" C 1299 1299 0 0 0
Dr 1299 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 11417 3937
Le 397568
$EndPAD
$PAD
Sh "C5" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 4 "N-000005"
Po 2709 -7500
Le 400128
$EndPAD
$PAD
Sh "C6" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 1 "N-000001"
Po 1709 -7500
Le 373760
$EndPAD
$PAD
Sh "C7" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 6 "N-000008"
Po 709 -7500
Le 379136
$EndPAD
$PAD
Sh "C8" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po -291 -7500
Le 373030
$EndPAD
$PAD
Sh "C1" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 2 "N-000002"
Po 2709 7500
Le 372787
$EndPAD
$PAD
Sh "C2" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 3 "N-000003"
Po 1709 7500
Le 32
$EndPAD
$PAD
Sh "C3" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 5 "N-000007"
Po 709 7500
Le 20
$EndPAD
$PAD
Sh "C4" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po -291 7500
Le 23
$EndPAD
$PAD
Sh "SW1" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po -1791 7500
Le 20
$EndPAD
$PAD
Sh "SW2" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po -1791 6500
Le 23
$EndPAD
$EndMODULE SAM_FCI
$MODULE FFC_REBELSIM
Po 30900 34000 1800 0 4DCBF7BC 4F3FC16A ~~
Li FFC_REBELSIM
Sc 4F3FC16A
AR /4F3FBFB5
Op 0 0 0
T0 0 -2756 600 600 1800 120 M V 20 N "P1"
T1 0 1614 600 600 1800 120 M V 20 N "REBELSIM"
DS -2087 -1693 -2087 0 150 20
DS -2087 0 2087 0 150 20
DS 2087 0 2087 -1693 150 20
DS -2717 -2165 -2717 -1693 150 20
DS 2717 -2165 2717 -1693 150 20
DS -2717 -2165 2717 -2165 150 20
DS 2717 -1693 -2717 -1693 150 20
$PAD
Sh "1" R 236 787 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 2 "N-000002"
Po -984 197
Le 1
$EndPAD
$PAD
Sh "2" R 236 787 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 3 "N-000003"
Po -591 197
Le 3
$EndPAD
$PAD
Sh "3" R 236 787 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 5 "N-000007"
Po -197 197
Le 72
$EndPAD
$PAD
Sh "4" R 236 787 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 6 "N-000008"
Po 197 197
Le 6
$EndPAD
$PAD
Sh "5" R 236 787 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 1 "N-000001"
Po 591 197
Le 76
$EndPAD
$PAD
Sh "6" R 236 787 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 4 "N-000005"
Po 984 197
Le 90
$EndPAD
$PAD
Sh "" R 276 1654 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 0 ""
Po -1378 -630
Le 76
$EndPAD
$PAD
Sh "" R 276 1654 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 0 ""
Po 1378 -630
Le 80
$EndPAD
$EndMODULE FFC_REBELSIM
$TEXTPCB
Te "D45197"
Po 45800 35200 600 800 120 0
De 20 0 0 Normal
$EndTEXTPCB
$TEXTPCB
Te "D45197"
Po 45800 35200 600 800 120 0
De 21 1 0 Normal
$EndTEXTPCB
$TEXTPCB
Te "sysmocom"
nl "SAM-FPC-Adapter"
Po 30900 22100 600 800 120 0
De 15 1 0 Normal
$EndTEXTPCB
$TEXTPCB
Te "sysmocom"
nl "SAM-FPC-Adapter"
Po 30800 22100 600 800 120 0
De 0 0 0 Normal
$EndTEXTPCB
$DRAWSEGMENT
Po 0 23800 20300 23800 36600 150
De 28 0 900 0 0
$EndDRAWSEGMENT
$DRAWSEGMENT
Po 0 48800 20300 23800 20300 150
De 28 0 900 0 0
$EndDRAWSEGMENT
$DRAWSEGMENT
Po 0 48800 36600 48800 20300 150
De 28 0 900 0 0
$EndDRAWSEGMENT
$DRAWSEGMENT
Po 0 23800 36600 48800 36600 150
De 28 0 900 0 0
$EndDRAWSEGMENT
$TRACK
Po 0 30309 33803 30309 32091 236 -1
De 0 0 1 0 400000
Po 0 38000 20900 38009 20900 236 -1
De 0 0 1 0 800000
Po 0 38000 30800 38000 20900 236 -1
De 0 0 1 0 0
Po 3 38000 30800 38000 30800 350 -1
De 15 1 1 0 0
Po 0 35500 30800 38000 30800 236 -1
De 15 0 1 0 0
Po 3 35500 30800 35500 30800 350 -1
De 15 1 1 0 0
Po 0 31600 30800 35500 30800 236 -1
De 0 0 1 0 0
Po 0 30309 32091 31600 30800 236 -1
De 0 0 1 0 0
Po 0 31884 33803 31884 33116 236 -1
De 0 0 2 0 400000
Po 0 39000 35900 39009 35900 236 -1
De 0 0 2 0 800000
Po 0 39000 33700 39000 35900 236 -1
De 0 0 2 0 0
Po 0 38200 32900 39000 33700 236 -1
De 0 0 2 0 0
Po 0 32100 32900 38200 32900 236 -1
De 0 0 2 0 0
Po 0 31884 33116 32100 32900 236 -1
De 0 0 2 0 0
Po 0 31491 33803 31491 32909 236 -1
De 0 0 3 0 400000
Po 0 38000 35900 38009 35900 236 -1
De 0 0 3 0 800000
Po 0 38000 33500 38000 35900 236 -1
De 0 0 3 0 0
Po 3 38000 33500 38000 33500 350 -1
De 15 1 3 0 0
Po 0 38000 32400 38000 33500 236 -1
De 15 0 3 0 0
Po 3 38000 32400 38000 32400 350 -1
De 15 1 3 0 0
Po 0 32000 32400 38000 32400 236 -1
De 0 0 3 0 0
Po 0 31491 32909 32000 32400 236 -1
De 0 0 3 0 0
Po 0 29916 33803 29916 31784 236 -1
De 0 0 4 0 400000
Po 0 39000 20800 39009 20900 236 -1
De 0 0 4 0 800000
Po 0 39000 30200 39000 20800 236 -1
De 0 0 4 0 0
Po 3 39000 30200 39000 30200 350 -1
De 15 1 4 0 0
Po 0 36000 30200 39000 30200 236 -1
De 15 0 4 0 0
Po 3 36000 30200 36000 30200 350 -1
De 15 1 4 0 0
Po 0 31500 30200 36000 30200 236 -1
De 0 0 4 0 0
Po 0 29916 31784 31500 30200 236 -1
De 0 0 4 0 0
Po 0 31097 33803 31097 32703 236 -1
De 0 0 5 0 400000
Po 0 37000 35800 37009 35900 236 -1
De 0 0 5 0 800000
Po 0 37000 33500 37000 35800 236 -1
De 0 0 5 0 0
Po 3 37000 33500 37000 33500 350 -1
De 15 1 5 0 0
Po 0 37000 31900 37000 33500 236 -1
De 15 0 5 0 0
Po 3 37000 31900 37000 31900 350 -1
De 15 1 5 0 0
Po 0 31900 31900 37000 31900 236 -1
De 0 0 5 0 0
Po 0 31097 32703 31900 31900 236 -1
De 0 0 5 0 0
Po 0 30703 33803 30703 32397 236 -1
De 0 0 6 0 400000
Po 0 37000 20800 37009 20900 236 -1
De 0 0 6 0 800000
Po 0 37000 30100 37000 20800 236 -1
De 0 0 6 0 0
Po 0 35700 31400 37000 30100 236 -1
De 0 0 6 0 0
Po 0 31700 31400 35700 31400 236 -1
De 0 0 6 0 0
Po 0 30703 32397 31700 31400 236 -1
De 0 0 6 0 0
$EndTRACK
$ZONE
$EndZONE
$EndBOARD

View File

@@ -0,0 +1,17 @@
Cmp-Mod V01 Created by CvPCB (2011-07-02 BZR 3034)-testing date = Sat 18 Feb 2012 04:35:11 PM CET
BeginCmp
TimeStamp = /4F3FBFB5;
Reference = P1;
ValeurCmp = REBELSIM;
IdModule = FFC_REBELSIM;
EndCmp
BeginCmp
TimeStamp = /4F3FBFC0;
Reference = P2;
ValeurCmp = ISO7816_NO;
IdModule = SAM_FCI;
EndCmp
EndListe

View File

@@ -0,0 +1,22 @@
# EESchema Netlist Version 1.1 created Sat 18 Feb 2012 04:35:11 PM CET
(
( /4F3FBFB5 FFC_REBELSIM P1 REBELSIM
( 1 N-000002 )
( 2 N-000003 )
( 3 N-000007 )
( 4 N-000008 )
( 5 N-000001 )
( 6 N-000005 )
)
( /4F3FBFC0 SAM_FCI P2 ISO7816_NO
( C1 N-000002 )
( C2 N-000003 )
( C3 N-000007 )
( C4 ? )
( C5 N-000005 )
( C6 N-000001 )
( C7 N-000008 )
( C8 ? )
)
)
*

View File

@@ -1,8 +1,11 @@
update=Di 21 Jun 2011 21:05:47 CEST
last_client=pcbnew
update=Sat 18 Feb 2012 04:35:01 PM CET
version=1
last_client=cvpcb
[general]
version=1
[eeschema]
version=1
LibDir=lib
LibDir=/sunbeam/home/laforge/projects/git/simtrace/hardware/kicad/lib
NetFmt=1
HPGLSpd=20
HPGLDm=15
@@ -63,11 +66,6 @@ LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=smartcard
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew]
version=1
PadDrlX=320
@@ -84,9 +82,8 @@ DrawLar=150
EdgeLar=150
TxtLar=120
MSegLar=150
LastNetListRead=simcable.net
LastNetListRead=simadapter1.net
[pcbnew/libraries]
LibDir=
LibName1=sockets
LibName2=connect
LibName3=discret
@@ -97,4 +94,12 @@ LibName7=display
LibName8=valves
LibName9=led
LibName10=dip_sockets
LibName11=lib/smartcard
LibName11=FPC_6PIN
LibName12=smartcard
LibName13=SIMtrace
LibDir=/sunbeam/home/laforge/projects/git/simtrace/hardware/kicad/lib
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms

View File

@@ -0,0 +1,113 @@
EESchema Schematic File Version 2 date Sat 18 Feb 2012 04:48:32 PM CET
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:smartcard
EELAYER 43 0
EELAYER END
$Descr A4 11700 8267
encoding utf-8
Sheet 1 1
Title ""
Date "18 feb 2012"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
5750 2450 6100 2450
Wire Wire Line
6100 2450 6100 1900
Wire Wire Line
6100 1900 5200 1900
Wire Wire Line
5200 1900 5200 1650
Wire Wire Line
5750 2250 5900 2250
Wire Wire Line
5900 2250 5900 1700
Wire Wire Line
5900 1700 5400 1700
Wire Wire Line
5400 1700 5400 1650
Wire Wire Line
4650 2350 4400 2350
Wire Wire Line
4400 2350 4400 1800
Wire Wire Line
4400 1800 5000 1800
Wire Wire Line
5000 1800 5000 1650
Wire Wire Line
4650 2250 4500 2250
Wire Wire Line
4500 2250 4500 1700
Wire Wire Line
4500 1700 4900 1700
Wire Wire Line
4900 1700 4900 1650
Wire Wire Line
5100 1650 5100 1900
Wire Wire Line
5100 1900 4300 1900
Wire Wire Line
4300 1900 4300 2450
Wire Wire Line
4300 2450 4650 2450
Wire Wire Line
5300 1650 5300 1800
Wire Wire Line
5300 1800 6000 1800
Wire Wire Line
6000 1800 6000 2350
Wire Wire Line
6000 2350 5750 2350
$Comp
L ISO7816_NO P2
U 1 1 4F3FBFC0
P 5200 2400
F 0 "P2" H 5200 2650 60 0000 C CNN
F 1 "ISO7816_NO" H 5200 2150 60 0000 C CNN
1 5200 2400
1 0 0 -1
$EndComp
$Comp
L REBELSIM P1
U 1 1 4F3FBFB5
P 5150 1300
F 0 "P1" H 5200 1650 60 0000 C CNN
F 1 "REBELSIM" V 5350 1300 60 0000 C CNN
1 5150 1300
0 -1 -1 0
$EndComp
$EndSCHEMATC

View File

@@ -1,59 +0,0 @@
Cmp-Mod V01 Created by CvPCB (2011-06-08)-testing date = Sa 02 Jul 2011 10:33:03 CEST
BeginCmp
TimeStamp = /4E0084E2;
Reference = P_DOWN2;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E0084D4;
Reference = P_LEFT3;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E0084DD;
Reference = P_RIGHT4;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E0084D9;
Reference = P_UP1;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E0ED4A7;
Reference = SIM_DOWN2;
ValeurCmp = ISO7816_CARD;
IdModule = SIM;
EndCmp
BeginCmp
TimeStamp = /4E0ED4DA;
Reference = SIM_LEFT3;
ValeurCmp = ISO7816_CARD;
IdModule = SIM;
EndCmp
BeginCmp
TimeStamp = /4E0ED4DB;
Reference = SIM_RIGHT4;
ValeurCmp = ISO7816_CARD;
IdModule = SIM;
EndCmp
BeginCmp
TimeStamp = /4E0085A5;
Reference = SIM_UP1;
ValeurCmp = ISO7816_CARD;
IdModule = SIM;
EndCmp
EndListe

View File

@@ -1,76 +0,0 @@
# EESchema Netlist Version 1.1 created Sa 02 Jul 2011 10:33:03 CEST
(
( /4E0084E2 FFC P_DOWN2 FFC
( 1 N-000032 )
( 2 N-000029 )
( 3 N-000002 )
( 4 N-000003 )
( 5 N-000027 )
( 6 N-000004 )
)
( /4E0084D4 FFC P_LEFT3 FFC
( 1 N-000011 )
( 2 N-000023 )
( 3 N-000024 )
( 4 N-000025 )
( 5 N-000028 )
( 6 N-000026 )
)
( /4E0084DD FFC P_RIGHT4 FFC
( 1 N-000012 )
( 2 N-000001 )
( 3 N-000013 )
( 4 N-000018 )
( 5 N-000009 )
( 6 N-000019 )
)
( /4E0084D9 FFC P_UP1 FFC
( 1 N-000020 )
( 2 N-000030 )
( 3 N-000017 )
( 4 N-000021 )
( 5 N-000022 )
( 6 N-000031 )
)
( /4E0ED4A7 SIM SIM_DOWN2 ISO7816_CARD
( C1 N-000032 )
( C2 N-000029 )
( C3 N-000002 )
( C4 ? )
( C5 N-000004 )
( C6 N-000027 )
( C7 N-000003 )
( C8 ? )
)
( /4E0ED4DA SIM SIM_LEFT3 ISO7816_CARD
( C1 N-000011 )
( C2 N-000023 )
( C3 N-000024 )
( C4 ? )
( C5 N-000026 )
( C6 N-000028 )
( C7 N-000025 )
( C8 ? )
)
( /4E0ED4DB SIM SIM_RIGHT4 ISO7816_CARD
( C1 N-000012 )
( C2 N-000001 )
( C3 N-000013 )
( C4 ? )
( C5 N-000019 )
( C6 N-000009 )
( C7 N-000018 )
( C8 ? )
)
( /4E0085A5 SIM SIM_UP1 ISO7816_CARD
( C1 N-000020 )
( C2 N-000030 )
( C3 N-000017 )
( C4 ? )
( C5 N-000031 )
( C6 N-000022 )
( C7 N-000021 )
( C8 ? )
)
)
*

View File

@@ -1,311 +0,0 @@
EESchema Schematic File Version 2 date Sa 02 Jul 2011 10:31:49 CEST
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:smartcard
EELAYER 25 0
EELAYER END
$Descr A4 11700 8267
encoding utf-8
Sheet 1 1
Title "SIM card for FFC"
Date "2 jul 2011"
Rev "v1.0"
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
NoConn ~ 9500 2850
NoConn ~ 8400 2850
Wire Wire Line
9500 2750 10000 2750
Wire Wire Line
10000 2950 9600 2950
Wire Wire Line
9600 2950 9600 2550
Wire Wire Line
9600 2550 9500 2550
Wire Wire Line
8400 2650 8150 2650
Wire Wire Line
8150 2650 8150 2200
Wire Wire Line
8150 2200 9850 2200
Wire Wire Line
9850 2200 9850 2550
Wire Wire Line
9850 2550 10000 2550
Wire Wire Line
6350 2550 6050 2550
Wire Wire Line
6050 2550 6050 2950
Wire Wire Line
6050 2950 5800 2950
Wire Wire Line
5800 2750 6350 2750
Wire Wire Line
7450 2650 7600 2650
Wire Wire Line
7600 2650 7600 2200
Wire Wire Line
7600 2200 5900 2200
Wire Wire Line
5900 2200 5900 2550
Wire Wire Line
5900 2550 5800 2550
Wire Wire Line
3600 2700 3600 2550
Wire Wire Line
3600 2550 4600 2550
Wire Wire Line
4600 2550 4600 1800
Wire Wire Line
4600 1800 4400 1800
Wire Wire Line
3800 2700 3800 2450
Wire Wire Line
3800 2450 4500 2450
Wire Wire Line
4500 2450 4500 2000
Wire Wire Line
4500 2000 4400 2000
Wire Wire Line
3100 2400 4100 2400
Wire Wire Line
3100 2400 3100 1800
Wire Wire Line
3100 1800 3300 1800
Wire Wire Line
3900 2700 3900 2300
Wire Wire Line
3900 2300 3200 2300
Wire Wire Line
3200 2300 3200 2000
Wire Wire Line
3200 2000 3300 2000
Wire Wire Line
2000 2300 2000 2450
Wire Wire Line
2000 2450 2550 2450
Wire Wire Line
2550 2450 2550 3050
Wire Wire Line
2550 3050 2400 3050
Wire Wire Line
1800 2300 1800 2500
Wire Wire Line
1800 2500 1100 2500
Wire Wire Line
1100 2500 1100 3150
Wire Wire Line
1100 3150 1300 3150
Wire Wire Line
1600 2300 1600 2400
Wire Wire Line
1600 2400 1200 2400
Wire Wire Line
1200 2400 1200 2950
Wire Wire Line
1200 2950 1300 2950
Wire Wire Line
1300 3050 1150 3050
Wire Wire Line
1150 3050 1150 2450
Wire Wire Line
1150 2450 1700 2450
Wire Wire Line
1700 2450 1700 2300
Wire Wire Line
2400 2950 2500 2950
Wire Wire Line
2500 2950 2500 2400
Wire Wire Line
2500 2400 2100 2400
Wire Wire Line
2100 2400 2100 2300
Wire Wire Line
2400 3150 2600 3150
Wire Wire Line
2600 3150 2600 2500
Wire Wire Line
2600 2500 1900 2500
Wire Wire Line
1900 2500 1900 2300
Wire Wire Line
3300 1900 3150 1900
Wire Wire Line
3150 1900 3150 2350
Wire Wire Line
3150 2350 4000 2350
Wire Wire Line
4000 2350 4000 2700
Wire Wire Line
4100 2400 4100 2700
Wire Wire Line
4400 1900 4550 1900
Wire Wire Line
4550 1900 4550 2500
Wire Wire Line
4550 2500 3700 2500
Wire Wire Line
3700 2500 3700 2700
Wire Wire Line
5800 2450 5850 2450
Wire Wire Line
5850 2450 5850 2150
Wire Wire Line
5850 2150 7550 2150
Wire Wire Line
7550 2150 7550 2550
Wire Wire Line
7550 2550 7450 2550
Wire Wire Line
5800 2650 5950 2650
Wire Wire Line
5950 2650 5950 2250
Wire Wire Line
5950 2250 7650 2250
Wire Wire Line
7650 2250 7650 2750
Wire Wire Line
7650 2750 7450 2750
Wire Wire Line
5800 2850 6000 2850
Wire Wire Line
6000 2850 6000 2650
Wire Wire Line
6000 2650 6350 2650
Wire Wire Line
10000 2450 9900 2450
Wire Wire Line
9900 2450 9900 2150
Wire Wire Line
9900 2150 8200 2150
Wire Wire Line
8200 2150 8200 2550
Wire Wire Line
8200 2550 8400 2550
Wire Wire Line
10000 2650 9800 2650
Wire Wire Line
9800 2650 9800 2250
Wire Wire Line
9800 2250 8100 2250
Wire Wire Line
8100 2250 8100 2750
Wire Wire Line
8100 2750 8400 2750
Wire Wire Line
9500 2650 9650 2650
Wire Wire Line
9650 2650 9650 2850
Wire Wire Line
9650 2850 10000 2850
NoConn ~ 7450 2850
NoConn ~ 6350 2850
NoConn ~ 4400 2100
NoConn ~ 3300 2100
$Comp
L FFC P_DOWN2
U 1 1 4E0084E2
P 3850 3050
F 0 "P_DOWN2" H 3900 3400 60 0000 C CNN
F 1 "FFC" V 4050 3050 60 0000 C CNN
1 3850 3050
0 1 1 0
$EndComp
NoConn ~ 1300 3250
NoConn ~ 2400 3250
$Comp
L ISO7816_CARD SIM_RIGHT4
U 1 1 4E0ED4DB
P 8950 2700
F 0 "SIM_RIGHT4" H 8950 2950 60 0000 C CNN
F 1 "ISO7816_CARD" H 8950 2450 60 0000 C CNN
1 8950 2700
1 0 0 -1
$EndComp
$Comp
L ISO7816_CARD SIM_LEFT3
U 1 1 4E0ED4DA
P 6900 2700
F 0 "SIM_LEFT3" H 6900 2950 60 0000 C CNN
F 1 "ISO7816_CARD" H 6900 2450 60 0000 C CNN
1 6900 2700
1 0 0 -1
$EndComp
$Comp
L ISO7816_CARD SIM_DOWN2
U 1 1 4E0ED4A7
P 3850 1950
F 0 "SIM_DOWN2" H 3850 2200 60 0000 C CNN
F 1 "ISO7816_CARD" H 3850 1700 60 0000 C CNN
1 3850 1950
1 0 0 -1
$EndComp
$Comp
L ISO7816_CARD SIM_UP1
U 1 1 4E0085A5
P 1850 3100
F 0 "SIM_UP1" H 1850 3350 60 0000 C CNN
F 1 "ISO7816_CARD" H 1850 2850 60 0000 C CNN
1 1850 3100
1 0 0 -1
$EndComp
$Comp
L FFC P_RIGHT4
U 1 1 4E0084DD
P 10350 2700
F 0 "P_RIGHT4" H 10400 3050 60 0000 C CNN
F 1 "FFC" V 10550 2700 60 0000 C CNN
1 10350 2700
1 0 0 -1
$EndComp
$Comp
L FFC P_UP1
U 1 1 4E0084D9
P 1850 1950
F 0 "P_UP1" H 1900 2300 60 0000 C CNN
F 1 "FFC" V 2050 1950 60 0000 C CNN
1 1850 1950
0 -1 -1 0
$EndComp
$Comp
L FFC P_LEFT3
U 1 1 4E0084D4
P 5450 2700
F 0 "P_LEFT3" H 5500 3050 60 0000 C CNN
F 1 "FFC" V 5650 2700 60 0000 C CNN
1 5450 2700
-1 0 0 1
$EndComp
$EndSCHEMATC

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