139 Commits

Author SHA1 Message Date
Kévin Redon
18ed2c1ed8 add v1.1p release files
Change-Id: Ie0f05b912df1f1c44157be2cea24c12d75627374
2019-10-01 14:30:46 +02:00
Kévin Redon
dc4cb0a9ac Merge branch 'v1.1_production'
Change-Id: Ie064c379c9625b3cf6910912fd859e8e4dd0326e
2019-10-01 14:28:01 +02:00
Kévin Redon
74eb7fad6d add v1.0p release files
Change-Id: Id4b69f1b6deac0a7d0f3725f2d96d75c5b6c6ca8
2019-10-01 14:25:31 +02:00
Kévin Redon
8c202c012b Merge branch 'v1.0_production'
Change-Id: I481a6b1802993ceb6d02e7edcbd3b6d853f1e487
2019-10-01 14:21:04 +02:00
Kévin Redon
ceeb2b1ad8 add v1.0 release files
Change-Id: I879d35bca5bbaf2bc9616d181b085b4af7196fdc
2019-10-01 14:17:35 +02:00
Harald Welte
6fde8e1c26 update README with current information + convert to Markdown 2017-03-17 22:49:14 +01:00
Harald Welte
197ed82a32 add 'sysmocom' name to mini-UICC and nano-UICC adapters
As sysmocom is the only company manufacturing them for now, we add this
branding to the design files.
2016-04-01 13:13:53 +02:00
Harald Welte
46aceb222a remove second copy of mini-UICC FPC adapter 2016-04-01 10:06:09 +02:00
Harald Welte
0a530496b5 Add 4FF (nanoSIM) adapter 2015-08-19 15:02:51 +02:00
Harald Welte
b8d4927137 mini-UICC-reverse: re-generate gerber and add outline GBR 2014-04-30 20:27:36 +02:00
Harald Welte
e179a32048 add PCB design of mini-UICC (original and reverse) adapters 2014-04-26 09:37:22 +02:00
Harald Welte
eee3243dda add GEDA and gerber data for microSIM (3FF) adapter cable
Original by Kevin Redon, layout improvements by myself.
2013-06-12 18:41:21 +02:00
Holger Hans Peter Freyther
68ae3e3d0f usermanual: Document the serial console settings 2012-11-10 08:58:36 +01:00
Harald Welte
067dad1ae3 import v1.2p release schematics (pdf) and gerber 2012-05-20 01:31:11 +02:00
Holger Hans Peter Freyther
203312eb41 issues: Add a new issue and reword the old one 2012-04-07 13:12:15 +02:00
Holger Hans Peter Freyther
cc4fa2571c wireshark: Mention that our patch has been upstreamed
Starting with Wireshark 1.7.1 we will not need to patch wireshark
anymore.
2012-04-07 13:01:33 +02:00
Holger Hans Peter Freyther
fe56d0df14 firmware: Point to the wiki for links about toolchains. 2012-04-07 12:37:19 +02:00
Holger Hans Peter Freyther
adf48db1b3 usermanual: Obey the docbook schema for xmlto
dblatex was more forgiving, add missing tags to make xmlto happy
2012-04-07 11:39:07 +02:00
Harald Welte
7e2c289d2e production version of SIM-SAM adapter 2012-03-16 08:52:00 +01:00
Harald Welte
ea3e3d70b8 the wireshark patch for SIM dissection has been merged mainline 2012-02-29 23:30:29 +01:00
Harald Welte
96923e77f1 simadapter: proper naming of components 2012-02-18 16:48:47 +01:00
Harald Welte
5708ca8304 add SAM-to-FPC-adapter 2012-02-18 16:48:06 +01:00
Harald Welte
b14d0ad279 simtrace: Add print-out of PPS (Fi/Di change).
simtrace firmware 4f7ca20bf40b911c035264d86ef0359d20e7ac88 and later
includes an indication of PPS-induced Fi/Di changes.  We now print
the such indications to the user.
2012-02-12 15:37:14 +01:00
Martin Paljak
e1bed6d14b apdu_split: correctly handle Le=00 which means 256. 2012-01-25 18:44:38 +01:00
Holger Hans Peter Freyther
4885038690 usermanual: Update with new packages, v1.1p and v0.4 firmware 2012-01-11 11:48:56 +01:00
Holger Hans Peter Freyther
a83492aac6 manual: Update installation for more recent distributions 2012-01-11 11:48:56 +01:00
Kevin Redon
bf8fda49c8 hw: sheet reorganized 2011-12-29 08:22:08 +01:00
Kevin Redon
4aca2c0ac4 hw: power sources path corrected 2011-12-29 08:11:06 +01:00
Kevin Redon
6db07c8a66 hw: +1.8V output corrected, as it does not exist 2011-12-26 13:45:14 +01:00
Kevin Redon
6a28f23265 hw: input voltage attached to ADC, so to measure max SIM voltage output 2011-12-26 13:39:45 +01:00
Kevin Redon
678029c527 hw: only 2 adjustable LDOs are used. 1x3.3v for CPU, 1 for the SIM 2011-12-26 13:01:44 +01:00
Kevin Redon
c20a5599dc hw: power selector for phone removed. only VCC_PHONE is needed 2011-12-26 12:24:30 +01:00
Kevin Redon
4edfab2e1d hw: Rakefile tries to guess gEDA scheme directory 2011-12-22 09:55:01 +01:00
Kevin Redon
9ab3079cbb Merge branch 'master' of git.osmocom.org:simtrace 2011-12-21 15:54:55 +01:00
Harald Welte
4bd25ce274 FFC: add edges of stiffener to Eco1 layer 2011-12-15 12:02:23 +01:00
Holger Hans Peter Freyther
5f9f38378b main: Move code around to let the SIMtrace keep running...
Re-open the USB device, reset the state... handle reconnects of
the device.
2011-12-14 15:23:27 +01:00
Holger Hans Peter Freyther
54683c7b8f main: Re-initialize the APDU split method when we enter the main_loop
Make sure we forget the current state of the APDU splitter when we
re-enter the mainloop of the application.
2011-12-14 15:23:26 +01:00
Holger Hans Peter Freyther
943d7d28dc main: Move the mainloop into a separate function
Prepare to have the application wait for the USB device to come
back. This will be done by moving the code around and then having
a simple for loop.
2011-12-14 15:23:26 +01:00
Harald Welte
56b8045e67 add nicely rendered schematics for v1.0p and v1.1p 2011-12-14 15:19:41 +01:00
Harald Welte
395633e367 FFC: add "sysmocom" text on copper layer of all four adapters 2011-12-14 15:12:09 +01:00
Kevin Redon
092bc344a5 hw: LDO documented 2011-12-08 14:40:29 +01:00
Kevin Redon
1da28c2c5d hw: pdf removed. use the rakefile to generate it 2011-12-08 14:32:41 +01:00
Kevin Redon
6b07b4c16b hw: 3variables LDOs TC1071 used for 1.8V,3.0V,3.3V 2011-12-07 16:46:55 +01:00
Kevin Redon
cd9c804f1a hw: SIM card is smaller (14.9mm instead of 15mm) to better fit in the slot 2011-12-07 14:40:51 +01:00
Kevin Redon
2b9d0c26a1 hw: fabrication output generated 2011-12-06 00:39:30 +01:00
Kevin Redon
9fb2dd51e8 hw: LDO changed(now using multiple TP1071), PWR lines remaned according to classes 2011-12-01 18:07:00 +01:00
Kevin Redon
945f0daa51 hw: SIM FFC cables gerber exported. only ppa/paxer kicad could open pcb \!\!\! 2011-11-29 09:47:11 +01:00
Kevin Redon
228f825efc hw: part information added 2011-11-22 11:58:16 +01:00
Kevin Redon
941945837f hw: Rakefile can check component properties 2011-11-21 10:38:06 +01:00
Kevin Redon
730ae7b46c hw: components have now part description 2011-11-21 10:14:13 +01:00
Kevin Redon
b1c38515fc hw: kicad schema remove, geda rakefile builds the schema. version set to v1.5 (to go up to v2.0) 2011-11-17 12:18:18 +01:00
Kevin Redon
664c813540 datasheet folder removed: too many new datasheets used for SIMtrace v2, takes to much space in git, is under copyright 2011-11-14 20:52:01 +01:00
Kevin Redon
3d41a14f66 hw: translator added 2011-11-14 11:37:28 +01:00
Kevin Redon
4ce08fe4a9 hw: power selector implemented (demultiplexer + inverer + power switch) 2011-11-13 22:06:01 +01:00
Kevin Redon
923265e4f9 hw: inverted pin name corrected 2011-11-13 17:51:55 +01:00
Kevin Redon
2226f5aaeb hw: power switch replaced: FPF2005 to FPF2300 2011-11-13 17:50:54 +01:00
Kevin Redon
894f957bb0 hw: LDO LP2966 replaces AP7332, +1.8V from LDO is used for AT91SAM3S VDDCORE/VDDPLL instead of VDDOUT 2011-11-13 15:30:14 +01:00
Kevin Redon
1d448c7687 hw: CB3Q3244.sym renamed 2011-11-13 15:09:16 +01:00
Kevin Redon
4434a44e2c hw: VPP connected throug bus switch 2011-11-06 00:18:01 +01:00
Kevin Redon
9eeaa8a507 schema boxes, cb3q3244 redraw more schematic, uSD slot added, rakefile support adding version 2011-11-06 00:14:26 +01:00
Kevin Redon
14fe95fb9d Merge branch 'master' of git.osmocom.org:simtrace 2011-11-05 21:55:17 +01:00
Kevin Redon
88a018b3e2 hw: sysmocom added to copper, gerber rendered 2011-11-05 21:30:26 +01:00
Kevin Redon
e2ae9ddbde hw: solder mask between at91sam7s added 2011-11-05 19:06:28 +01:00
Kevin Redon
e3e4d3a783 VPP connected through bus switch 2011-11-05 18:47:04 +01:00
Kevin Redon
776b703b7e +1.8V line enlarged on C12, C15, C16. not possible on C19 2011-11-03 20:53:43 +01:00
Kevin Redon
2188a0bccb footprint refreched, cap near LDO 2011-11-03 20:38:04 +01:00
Kevin Redon
e27231b676 ftdi 3.3v cut in schema 2011-11-01 10:20:53 +01:00
Harald Welte
5ea4cd2771 simffc: make sure PCB edges really are on the edge, not on Eco2 layer 2011-10-31 22:13:49 +01:00
Kevin Redon
75890af814 cap placed near to CPU, some tracks redrawn 2011-10-26 14:09:34 +02:00
Kevin Redon
85ef0105b9 switched from KiCAD to gEDA (scriptable), SAM3S replaces SAM7S, no PLLRC required, 2.2uF cap replaces 1uF for less different components, uSD slot replaces flash 2011-10-26 14:05:18 +02:00
Holger Hans Peter Freyther
7bb1977810 doc: Use the highlighted picture from Myonium for TEST 2011-10-09 19:40:27 +02:00
Holger Hans Peter Freyther
d568a61aba doc: Comment from Myonium for other modes 2011-10-09 19:33:22 +02:00
Holger Hans Peter Freyther
61dcdc01bc doc: A small note on using DFU to update the firmware 2011-10-09 09:49:19 +02:00
Holger Hans Peter Freyther
e3e2e85a15 doc: Still two (maybe it is the same) firmware bug
Remove the ATR issue as Harald has fixed it, we still have the USB 3.0
and OSX enumeration issue.
2011-10-08 23:51:56 +02:00
Holger Hans Peter Freyther
ec50d509ad doc: Write a bit about programming using the SAM7 Utility 2011-10-08 23:46:34 +02:00
Holger Hans Peter Freyther
81ed5bce33 doc: Introduce a chapter on the firmware
Begin to document how to get the firmware, how to build it, how to
flash it, how to hack on it. Some parts are not there yet.
2011-10-08 15:25:53 +02:00
Holger Hans Peter Freyther
c6310b9281 docs: Move the '.' into the paragraph, fixes a jade error. 2011-10-08 15:02:08 +02:00
Holger Hans Peter Freyther
2daf5ca4cd wireshark: Add one more missing file 2011-08-16 18:11:55 +02:00
Kevin Redon
5c1f1ee9df Merge branch 'master' of git.osmocom.org:simtrace 2011-08-15 18:29:16 +02:00
Holger Hans Peter Freyther
d241286a35 doc: Document the planned but missing modes 2011-08-15 13:23:14 +02:00
Holger Hans Peter Freyther
58285d4e19 doc: Rename using to using_sniff to add more using mode 2011-08-15 13:16:32 +02:00
Holger Hans Peter Freyther
0b05b6bd0d doc: Add ... to indicate omitted output 2011-08-15 13:16:16 +02:00
Holger Hans Peter Freyther
e5a98e5b79 doc: Document building wireshark 2011-08-15 13:12:34 +02:00
Holger Hans Peter Freyther
e3fb596c64 doc: Use the FTDI wording from the wiki 2011-08-15 13:06:02 +02:00
Holger Hans Peter Freyther
7e582473c0 wireshark: Add the sim.c file as well 2011-08-15 12:07:12 +02:00
Holger Hans Peter Freyther
c960a25849 host: Pass all modules to one pkg-config invocation
Invoke pkg-config only once per command, makes the lines a
bit shorter as well.
2011-08-15 11:54:02 +02:00
Holger Hans Peter Freyther
a496d88a79 wireshark: Add a patch that applies to the stable 1.6 branch 2011-08-15 11:53:33 +02:00
Holger Hans Peter Freyther
1bb23171fc doc: Write about the KiCad schematics 2011-08-15 11:32:45 +02:00
Peter Stuge
18ad51fe76 Use libusb-1.0 for USB communication 2011-08-15 10:31:54 +02:00
Peter Stuge
7b76e0ce7c Silence warning: initialization from incompatible pointer type 2011-08-15 10:31:54 +02:00
Peter Stuge
0060806497 Include <stdlib.h> for malloc() and free() 2011-08-15 10:31:54 +02:00
Holger Hans Peter Freyther
a41f102a76 doc: Document the known firmware issues and if they have a workaround 2011-08-14 14:47:21 +02:00
Holger Hans Peter Freyther
2c5d60682f doc: Ask users to disconnect the power at the ftdi connector 2011-08-14 14:37:46 +02:00
Holger Hans Peter Freyther
41cb9903c0 doc: Reformat the text to have a 80 char line limit 2011-08-14 14:36:43 +02:00
Holger Hans Peter Freyther
b230ec61fc doc: Copy Kevin's hardware section into the documentation 2011-08-14 14:36:37 +02:00
Holger Hans Peter Freyther
0c387d5882 doc: Improve wording. Avoid repeating 'This hardware' 2011-08-14 08:21:32 +02:00
Kevin Redon
b3e229729f microSIM footprint added 2011-08-13 15:57:28 +02:00
Kevin Redon
902b6a68f1 microSIM schema created (cpoied from normal SIM) 2011-08-13 15:56:36 +02:00
Kevin Redon
0ce897d341 ftdi vcc disconnected 2011-08-13 13:52:27 +02:00
Kevin Redon
3b942695a9 cap near cpu, routing improved 2011-08-13 13:51:16 +02:00
Harald Welte
9389e50e7a update wireshark patch to work with latest wireshark svn trunk 2011-08-12 14:25:57 +02:00
Harald Welte
29b1190ddc include a copy instead of the symlink 2011-08-12 11:21:24 +02:00
Holger Hans Peter Freyther
d22a14bc29 doc: Document the installation of various things
http://software.opensuse.org/download.html?project=home:zecke23&package=simtrace
comes to rescue to show the binaries and the commands
2011-08-09 18:29:32 +02:00
Holger Hans Peter Freyther
eec6d44a12 doc: Document building from source 2011-08-09 18:16:23 +02:00
Holger Hans Peter Freyther
86323174e2 doc: Add images, add introduction, add usage system 2011-08-09 17:10:38 +02:00
Holger Hans Peter Freyther
ebbc9bef4f usermanual: Start writing some bits about the installation 2011-07-19 23:19:32 +02:00
Holger Hans Peter Freyther
f34b1aa52d simtrace: Add a very simple manpage 2011-07-17 19:17:11 +02:00
Holger Hans Peter Freyther
24ed56588b make: Provide a very simple install target for SIMtrace 2011-07-17 18:07:21 +02:00
Holger Hans Peter Freyther
5953e90599 make: Move the LDFLAGS to the end of the link line for OpenSUSE
The code does not build like this on a OpenSUSE system, it will
not find the libusb and libosmocore library.
2011-07-17 18:05:08 +02:00
Holger Hans Peter Freyther
f1c60623ae misc: Use osmo_hexdump instead of the local variant 2011-07-15 16:09:55 +02:00
Holger Hans Peter Freyther
83e051ce6e main.c: Initialize byte_count with 0. It is never used though. 2011-07-15 15:49:49 +02:00
Holger Hans Peter Freyther
13fdc84500 misc: Ignore some files 2011-07-13 00:10:28 +02:00
Holger Hans Peter Freyther
0729969530 manual: Start with a skeleton of a usermanual
This is a DocBook skeleton that should morph into a proper
usermanual for the SIMtrace.
2011-07-13 00:10:02 +02:00
Holger Hans Peter Freyther
666f9db529 host: Update the symlink, we have one level less 2011-07-13 00:10:02 +02:00
Holger Hans Peter Freyther
b259b72200 host: Use the pkg-config to find libosmocore headers and libs 2011-07-13 00:09:56 +02:00
Kevin Redon
2177808358 connection rounded (2.0mm radius) and copper added 2011-07-08 00:07:17 +02:00
Kevin Redon
0fdd374070 Merge branch 'master' of git.osmocom.org:simtrace 2011-07-07 15:29:17 +02:00
Kevin Redon
c880b85b05 flex board sim cables created (pcb edge are wrong) 2011-07-07 15:28:41 +02:00
Kevin Redon
48cea398d5 button are now harder to press (50gf vs 130gf) 2011-07-07 11:50:40 +02:00
Harald Welte
3e16dd64cf re-structure the directory layout to reflect that that ft232r stuff is old
we have long only been working on the sam7 based system.
2011-07-06 12:32:30 +02:00
Kevin Redon
024bdadddd BOM updated for LED (0805) 2011-07-02 19:06:15 +02:00
Kevin Redon
9c8bb8d6c5 LED now uses 0805 footprint instead of 0603 2011-07-02 18:35:12 +02:00
Kevin Redon
f4ccf46de4 schema/PCB/gerber output for simcable generated 2011-07-02 11:20:59 +02:00
Kevin Redon
b3e31f0d33 simcable is now a set of 4 SIM cards with FFC pads. Schema and PCB done 2011-07-02 11:13:15 +02:00
Kevin Redon
0bb4a762d7 shema/board/gerber generated. v1.1 released (untested) 2011-07-01 23:33:24 +02:00
Kevin Redon
ad17a3b751 component names and comment (pin 1, diode) placed on silk screen 2011-07-01 23:24:58 +02:00
Kevin Redon
0a35394773 board routed 2011-07-01 22:35:41 +02:00
Kevin Redon
80629fb975 components updated (pads are not on both sides); components placed; only the USB+power distribution routing has been done (by hand) 2011-07-01 18:04:14 +02:00
Kevin Redon
e3626efd36 BOM updated. new SAM (FCI 52400-25ALF), USB (molex 54819-0519), Jack 2.5mm (CUI SJ1-2503A) added and linked 2011-07-01 15:37:40 +02:00
Kevin Redon
6c9a1f4f50 new USB and jack 2.5 footprint used in the schema. netlist and component list generated 2011-07-01 13:06:14 +02:00
Kevin Redon
945909a241 footprint for USB mini-B connector MOLEX-54819-0519 created 2011-07-01 12:44:15 +02:00
Kevin Redon
173ce2e41a MOLEX 54819-0519 will replace HIROSE UX60-MB-5ST for USB mini-B connector. it's now throughole for more robustness 2011-07-01 12:15:36 +02:00
Kevin Redon
ea98b5a7b2 footprint for SJ1-2503A created 2011-07-01 12:00:50 +02:00
Kevin Redon
76b04b2281 SJ1-2503A replaces SJ-2523-SMT for the jack 2.5mm connector. it's now throughole for more robustness 2011-07-01 11:42:00 +02:00
Kevin Redon
c2d8d93407 netlist now include the SAM slot 2011-07-01 11:31:58 +02:00
Kevin Redon
106d06ccbe footprint for SAM slot created 2011-07-01 11:29:37 +02:00
Kevin Redon
ee30134bbc ID1 slot (named SAM, even if not entirely correct) added in schema (now v1.1) 2011-07-01 11:00:46 +02:00
Kevin Redon
1eeb56bf34 ID1 slot chosen (fro credit card size smartcards). datasheet added 2011-07-01 10:45:26 +02:00
Kevin Redon
b7dfb8ce63 simcable pcb drawing created. only the footprints have been placed 2011-07-01 10:27:13 +02:00
187 changed files with 199871 additions and 266947 deletions

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*.o
host/simtrace

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README
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Osmocom SIMTRACE
======================================================================
(C) 2010 by Harald Welte <laforge@gnumonks.org>
SIMTRACE is a program that can be used for tracing the communication
betewen a phone and the SIM card. More generally, it can trace any
ISO 7816 based smart card interface.
This repository contains a host program 'simtrace' as well as a patch
for wireshark.
The corresponding device firmware can be found in the openpcd.git
repository on git.gnumonks.org.

56
README.md Normal file
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# Osmocom SIMtrace
(C) 2010-2017 by Harald Welte <laforge@gnumonks.org>
SIMTtraceis a program that can be used for tracing the communication
between a phone and the SIM card. More generally, it can trace any
ISO 7816 based smart card interface.
SIMtrace is part of the [Osmocom](https://osmocom.org/) Open Source
Mobile Communications project.
This repository contains a host program 'simtrace' as well as a patch
for wireshark (which is part of mainline wireshark since February 2012)
The corresponding device firmware source code can be found at
<http://git.osmocom.org/openpcd/>
## Homepage
The official homepage of the project is
<https://osmocom.org/projects/simtrace/wiki/>
GIT Repository
--------------
You can clone from the official simtrace.git repository using
git clone git://git.osmocom.org/simtrace.git
There is a cgit interface at <http://git.osmocom.org/simtrace/>
## Documentation
There is a PDF user manual available from
<https://osmocom.org/attachments/download/2139/usermanual.pdf>
Mailing List
------------
Discussions related to simtrace are happening on the
simtrace@lists.osmocom.org mailing list, please see
<https://lists.osmocom.org/mailman/listinfo/simtrace> for subscription
options and the list archive.
Please observe the [Osmocom Mailing List
Rules](https://osmocom.org/projects/cellular-infrastructure/wiki/Mailing_List_Rules)
when posting.
Contributing
------------
Our coding standards are described at
<https://osmocom.org/projects/cellular-infrastructure/wiki/Coding_standards>
We us a e-mail based patch submission/review process on the
above-mentioned mailing list for contributions.

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LDFLAGS=-lusb -losmocore
all: simtrace
simtrace: main.o usb_helper.o usb.o apdu_split.o
$(CC) $(LDFLAGS) -o $@ $^
%.o: %.c
$(CC) $(CFLAGS) -o $@ -c $^
clean:
@rm -f simtrace *.o

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../../../openpcd/firmware/include/simtrace_usb.h

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#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <errno.h>
#include <usb.h>
#include <sys/ioctl.h>
#include "usb.h"
#include <linux/usbdevice_fs.h>
#define MAX_READ_WRITE 4096
#define USB_ERROR_STR(ret, x, args...) return ret
static int usb_get_fd(usb_dev_handle *uh)
{
return *((int *)uh);
}
int __usb_bulk_write(usb_dev_handle *dev, int ep, char *bytes, int length,
int timeout)
{
struct usbdevfs_bulktransfer bulk;
int ret, sent = 0;
/* Ensure the endpoint address is correct */
ep &= ~USB_ENDPOINT_IN;
do {
bulk.ep = ep;
bulk.len = length - sent;
if (bulk.len > MAX_READ_WRITE)
bulk.len = MAX_READ_WRITE;
bulk.timeout = timeout;
bulk.data = (unsigned char *)bytes + sent;
ret = ioctl(usb_get_fd(dev), USBDEVFS_BULK, &bulk);
if (ret < 0)
USB_ERROR_STR(ret,
"error writing to bulk endpoint %d: %s",
ep, strerror(errno));
sent += ret;
} while (ret > 0 && sent < length);
return sent;
}
int __usb_bulk_read(usb_dev_handle *dev, int ep, char *bytes, int size,
int timeout)
{
struct usbdevfs_bulktransfer bulk;
int ret, retrieved = 0, requested;
/* Ensure the endpoint address is correct */
ep |= USB_ENDPOINT_IN;
do {
bulk.ep = ep;
requested = size - retrieved;
if (requested > MAX_READ_WRITE)
requested = MAX_READ_WRITE;
bulk.len = requested;
bulk.timeout = timeout;
bulk.data = (unsigned char *)bytes + retrieved;
ret = ioctl(usb_get_fd(dev), USBDEVFS_BULK, &bulk);
if (ret < 0)
USB_ERROR_STR(ret,
"error reading from bulk endpoint 0x%x: %s",
ep, strerror(errno));
retrieved += ret;
} while (ret > 0 && retrieved < size && ret == requested);
return retrieved;
}
int __usb_reattach_kernel_driver_np(usb_dev_handle *dev, int interface)
{
struct usbdevfs_ioctl command;
command.ifno = interface;
command.ioctl_code = USBDEVFS_CONNECT;
command.data = NULL;
return ioctl(usb_get_fd(dev), USBDEVFS_IOCTL, &command);
}

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@@ -1,96 +0,0 @@
/* usb_helper - Low-Level USB routines for SimTrace
*
* (C) 2006-2010 by Harald Welte <hwelte@hmw-consulting.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <errno.h>
#include <unistd.h>
#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include <time.h>
#include <sys/time.h>
#include <sys/types.h>
#include <usb.h>
const char *
hexdump(const void *data, unsigned int len)
{
static char string[65535];
unsigned char *d = (unsigned char *) data;
unsigned int i, left, ofs;
string[0] = '\0';
ofs = snprintf(string, sizeof(string)-1, "(%u): ", len);
left = sizeof(string) - ofs;
for (i = 0; len--; i += 3) {
if (i >= sizeof(string) -4)
break;
snprintf(string+ofs+i, 4, " %02x", *d++);
}
string[sizeof(string)-1] = '\0';
return string;
}
static struct usb_device *find_usb_device (uint16_t vendor_id, uint16_t product_id)
{
struct usb_bus *bus;
for (bus = usb_busses; bus; bus = bus->next) {
struct usb_device *dev;
for (dev = bus->devices; dev; dev = dev->next) {
if (dev->descriptor.idVendor == vendor_id &&
dev->descriptor.idProduct == product_id)
return dev;
}
}
return NULL;
}
struct usb_dev_handle *usb_find_open(uint16_t vendor_id, uint16_t product_id)
{
struct usb_device *dev;
struct usb_dev_handle *hdl;
usb_init();
usb_find_busses();
usb_find_devices();
dev = find_usb_device(vendor_id, product_id);
if (!dev) {
fprintf(stderr, "Cannot find matching USB Device. "
"Are you sure it is connected?\n");
exit(1);
}
hdl = usb_open(dev);
if (!hdl) {
fprintf(stderr, "Unable to open usb device: %s\n",
usb_strerror());
exit(1);
}
if (usb_claim_interface(hdl, 0) < 0) {
fprintf(stderr, "Unable to claim usb interface "
"1 of device: %s\n", usb_strerror());
exit(1);
}
return hdl;
}

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@@ -1,28 +0,0 @@
#ifndef _USB_HELPER_H
#define _USB_HELPER_H
/* usb_helper - Low-Level USB routines for SimTrace
*
* (C) 2006-2010 by Harald Welte <hwelte@hmw-consulting.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <stdint.h>
const char *hexdump(const void *data, unsigned int len);
struct usb_dev_handle *usb_find_open(uint16_t vendor_id, uint16_t product_id);
#endif

4
docs/.gitignore vendored Normal file
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@@ -0,0 +1,4 @@
*.texi
usermanual.txt
usermanual.pdf
*.sw?

42
docs/Makefile Normal file
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@@ -0,0 +1,42 @@
# XSL stylesheets downloaded from http://docbook.sourceforge.net/release/xsl/current/html/
# Makefile from BitBake/OpenEmbedded manuals
topdir = .
manual = $(topdir)/usermanual.xml
# types = pdf txt rtf ps xhtml html man tex texi dvi
# types = pdf txt
types = $(docbooktotypes)
docbooktotypes = pdf txt
# htmlcssfile =
# htmlcss =
cleanfiles = $(foreach i,$(types),$(topdir)/$(i))
ifdef DEBUG
define command
$(1)
endef
else
define command
@echo $(2) $(3) $(4)
@$(1)
endef
endif
all: $(types)
lint: $(manual) FORCE
$(call command,xmllint --xinclude --postvalid --noout $(manual),XMLLINT $(manual))
$(types): lint FORCE
$(docbooktotypes): $(manual)
$(call command,docbook2$@ $(manual),DOCBOOK2 $@ $(manual))
clean:
rm -rf $(cleanfiles)
$(foreach i,$(types) $(foreach type,$(htmltypes),$(type)-nochunks),clean-$(i)):
rm -rf $(patsubst clean-%,%,$@)
FORCE:

9
docs/README Normal file
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@@ -0,0 +1,9 @@
This should be our user manual, it is created using docbook and
can be compiled by either. Patches for additional sections are
more than welcome.
$ make
or
$ dblatex usermanual.tex

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@@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<!--
<appendix id="appendix_sql_v09">
<title>SQL Tabellen v0.9</title>
<programlisting>
<inlinemediaobject><imageobject><imagedata format="linespecific" fileref="file" /></imageobject></inlinemediaobject>
</programlisting>
</appendix>
-->

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@@ -0,0 +1,90 @@
<?xml version="1.0" encoding="UTF-8"?>
<chapter id="chapter_building">
<title>Getting and Building the Software</title>
<section id="building_intros">
<title>Building software</title>
<para>There are three parts that can be built. It is the firmware
for the SIMtrace hardware, the SIMtrace software and the modified
version of wireshark. All of these have different source trees and
dependencies.</para>
</section>
<section id="building_simtrace">
<title>Building SIMtrace</title>
<section id="libosmocore">
<title>Building the Osmocom libosmocore library</title>
<screen>
$ <command>git</command> clone git://git.osmocom.org/libosmocore
$ <command>cd</command> libosmocore
$ <command>autoreconf</command> --install --force
$ <command>./configure</command>
$ <command>sudo</command> <command>make</command> install
</screen>
</section>
<section id="libusb">
<title>Installing libusb</title>
<para>You will need to install the libusb header files
to be able to compile <command>simtrace</command>.</para>
</section>
<section id="simtrace">
<title>Building <command>simtrace</command></title>
<screen>
$ wget https://api.opensuse.org/public/source/home:zecke23/simtrace/simtrace_0.0.1.tar.gz
$ tar xzf simtrace_0.0.1.tar.gz
$ cd simtrace-0.0.1
$ PKG_CONFIG_PATH=/usr/local/lib/pkgconfig make
cc `pkg-config --cflags libosmocore` -o main.o -c main.c
cc `pkg-config --cflags libosmocore` -o usb_helper.o -c usb_helper.c
cc `pkg-config --cflags libosmocore` -o usb.o -c usb.c
cc `pkg-config --cflags libosmocore` -o apdu_split.o -c apdu_split.c
cc -o simtrace main.o usb_helper.o usb.o apdu_split.o -lusb `pkg-config --libs libosmocore` -losmocore
</screen>
</section>
</section>
<section id="building_wireshark">
<title>Building Wireshark</title>
<para>SIMtrace provides a patch against <command>wireshark</command>
version 1.6. It is the easiest to checkout a copy using the 1.6 branch
of wireshark and applying the <filename>simcard.patch</filename> on top
of it. And then use the usual way of building wireshark</para>
<section id="getting_wireshark">
<title>Getting Wireshark</title>
<screen>
$ svn co https://anonsvn.wireshark.org/wireshark/trunk-1.6 wireshark-1.6
...
A wireshark-1.6/isprint.h
U wireshark-1.6
Checked out revision 38543.
</screen>
</section>
<section id="getting_simcard.patch">
<title>SIMCard patch</title>
<para>You will need to download and apply the patch.</para>
<screen>
$ cd wireshark-1.6
$ wget http://cgit.osmocom.org/cgit/simtrace/tree/wireshark/simcard-for-wireshark-1.6.patch
$ cat ../simcard-for-wireshark-1.6.patch | patch -p 0
patching file epan/dissectors/packet-gsm_sim.c
patching file epan/dissectors/packet-gsmtap.c
patching file epan/dissectors/Makefile.common
</screen>
</section>
<section id="building_and_installing">
<title>Building and Installing</title>
<screen>
$ autoreconf --install
$ ./configure
$ make
...
$ sudo ./wireshark
</screen>
</section>
</section>
</chapter>

152
docs/chapters/firmware.xml Normal file
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@@ -0,0 +1,152 @@
<?xml version="1.0" encoding="UTF-8"?>
<chapter id="chapter_firmware">
<title>Getting and Building the Firmware</title>
<section id="building_fw_intro">
<title>Introduction</title>
<para>The Firmware is the Software that is running on the
Microcontroller of the SIMtrace hardware. The Firmware itself
consists out of a couple of components for different parts of
the system. Besides the source code for the firmware you will
also need to have an ARM Cross-Compile Toolchain, a copy of the
SAM7 utilities to initially program the device or recover from
a fatal error and dfu-util to update the main part of the firmware
using the Device Firmware Update (DFU) mode.</para>
</section>
<section id="getting_a_toolchain">
<title>Getting a Toolchain</title>
<para>The toolchain needs to include a GCC newer than 3.4
and it may not be an EABI toolchain. EABI toolchains fail to properly
link the SIMtrace binary. You can easily build a toolchain yourself
or use one of the known working pre-built ones. Please see the
<ulink url="http://bb.osmocom.org/trac/wiki/toolchain">SIMtrace wiki</ulink>
for more information about getting a toolchain.
</para>
</section>
<section id="getting_the_firmware">
<title>Getting and Building the Firmware</title>
<para>The SIMtrace firmware is based on the OpenPCD RFID Reader Firmware and the
SIMtrace firmware code is located in the OpenPCD repository. You can use the
<command>git</command> to clone the repository.
<screen>
$ git clone git://git.gnumonks.org/openpcd.git
</screen>
</para>
<para>The firmware consists out of two separate binaries that will be concatted
and flashed into the NOR flash of the microcontroller. The main part is the dfu
program that will handle basic USB functionality and respond to Device Firmware
Update (DFU) requests to allow to update the firmware in the NOR or execute
software in RAM.
<screen>
$ cd openpcd/firmware
$ make -f Makefile.dfu BOARD=SIMTRACE
$ make BOARD=SIMTRACE DEBUG=1 TARGET=main_simtrace
$ cat dfu.bin main_simtrace.bin > main_simtrace.samba
$ cd ../..
</screen></para>
</section>
<section id="firmware_details">
<title>Firmware Details</title>
<para>
The handling for the DFU part can be found in the <filename>src/dfu</filename>
directory, it also provides low-level USB routines to work with USB Device
Port (UDP). These functions will be called from the main payload.
</para>
<para>The operating system part is in <filename>src/os</filename> it provides
basic hardware control and services to be used by the main application, this
includes USB enumeration, Watchdog programming, running the mainloop, interrupt
dispatching. The main application for SIMtrace can be found in
<filename>src/simtrace</filename> and this includes programming the two USART,
configuring the bus switch according to the mode.
</para>
</section>
<section id="firmware_programming_sam_ba">
<title>Initial Firmware Programming</title>
<para>In case the NOR Flash of the SAM7 Microcontroller is either blank or has
become corrupted the Microcontrollers support entering a mode called SAM-BA which
then allows flashing the device using the <filename>sam</filename> application. The
SAM-BA mode can be easily entered by following the below procedure.</para>
<procedure>
<title>Entering SAM-BA Mode</title>
<step><para>Unplug the SIMtrace Hardware from USB.</para></step>
<step><para>Short TEST to VCC (3.3V) pin by using the Jumper. Leave PA0, PA1, PA2 unconnected.</para></step>
<step><para>Power up the SIMtrace Hardware from USB.</para></step>
<step><para>Wait for 20 seconds.</para></step>
<step><para>Unplug the SIMtrace Hardware from USB.</para></step>
<step><para>Open/Remove the Jumper.</para></step>
</procedure>
<figure>
<title>TEST Jumper</title>
<mediaobject><imageobject>
<imagedata fileref="images/shortTEST.jpg" width="12cm"/>
</imageobject></mediaobject>
</figure>
<note><title>v1.0p/v1.1p Hardware Owners</title>
<para>Sometimes the SAM-BA mode is not entered. This is the case when the
two LEDs are on when powering up the SIMtrace Hardware with the Jumper set.
The reason for this is unknown but there are several workarounds:
<itemizedlist>
<listitem><para>Press the RESET button while powering up.</para></listitem>
<listitem><para>In addition, remove the jumper and put it back.</para></listitem>
</itemizedlist>
As soon as the two LEDs go off, the SAM-BA mode is properly entered.
</para>
</note>
<para>The <command>sam</command> application can be compiled to either use libusb or
normal files to program the device, depending on the drivers used you will
need to configure the application one way or another. The programming can then
be done using the below command.
<screen>
$ ./sam7 --exec set_clock --exec unlock_regions --exec "flash ../openpcd/firmware/main_simtrace.samba"
</screen>
<note><title>Silent failures</title>
<para>The <command>sam</command> can silently fail when not finding or being
able to configure the device properly. It is best to enter the interactive mode
by not providing any <command>--exec</command> commands.</para>
</note>
</para>
</section>
<section id="firmware_programming_dfu">
<title>Device Firmware Update</title>
<para>The Device Firmware Update (DFU) part of the firmware will be
booted first, it is checking if a button is active or if the software
reset reason was for DFU and then activates the DFU part or jumps to
the main application. DFU can be activated at any time using
<command>dfu-util</command> on the USB Host.</para>
<para>The <command>dfu-util</command> application might be already
packaged for your distribution, the source code can be found on the
<ulink url="http://dfu-util.gnumonks.org/">dfu-util.gnumonks.org</ulink>
website. To update the main part of the firmware simply do:
<screen>
$ dfu-util -d 16c0:0762 -a0 -D ./main_simtrace.bin -R
</screen></para>
</section>
<section id="firmware_programming_upgrade">
<title>Upgrading to v0.4 Firmware</title>
<para>Upgrading to v0.4 requires flashing both the Bootloader and the
SIMtrace application. The procedure is first to flash the bootloader,
then the SIMtrace application and finally reset the device.
</para>
<screen>
$ dfu-util -d 16c0:0762 -a 1 -D ./dfu.bin
$ dfu-util -d 16c0:0762 -a 0 -D ./main_simtrace.bin
... reset the device
</screen>
</section>
<section id="firmware_serial_console">
<title>Serial Console for debugging</title>
<para>The serial console operates at 115200 bauds with 8n1 and no flow control.</para>
</section>
</chapter>

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@@ -0,0 +1,116 @@
<?xml version="1.0" encoding="UTF-8"?>
<chapter id="chapter_hw">
<title>Hardware Details</title>
<section id="hw_design">
<title>HW Design</title>
<para>The Free Software KiCAD EDA was used to design the
hardware and can be used to look at the schematics and the
PCB routing. The hardware design can be found in the git
repository of the SIMtrace sources. For the v1.0 hardware
you will have to look at the v1.0_production branch.
</para>
</section>
<section id="pcb_populated">
<title>Populated PCB</title>
<para>The version v1.0p is the first production that had an
automatic SMT run. Due some production issues the labeling of
components didn't make it to the PCB but can be found in this
manual. The difference between the v1.0 and v1.0p hardware is
in the footprint of some components to utilize the existing
stock of the factory. This was mostly done for the LED and the
shottky diodes.</para>
<figure><title>SIMtrace v1.0 PCB</title>
<mediaobject>
<imageobject>
<imagedata fileref="images/simtrace_hw.jpg" width="15cm"/>
</imageobject>
<textobject><phrase>SIMtrace v1.0 PCB</phrase></textobject>
</mediaobject>
</figure>
</section>
<section id="pcb_surface">
<title>PCB Surface</title>
<para>
<figure><title>SIMtrace v1.0 Surface</title>
<mediaobjectco>
<imageobjectco>
<areaspec id="surface" units="calspair">
<area linkends="link_usb" coords="8800,0 8800,6100" id="usb"/>
<area linkends="link_serial" coords="8800,7000 8800,8000" id="serial"/>
<area linkends="link_debug" coords="8800,9000 8800,9500" id="debug"/>
<area linkends="link_jtag" coords="5000,8900 5000,9000" id="jtag"/>
<area linkends="link_bt1" coords="8900,0 9100,3500" id="bt1"/>
<area linkends="link_ffc" coords="500,3000 700,9000" id="ffc"/>
<area linkends="link_sim" coords="500,500 700,2000" id="sim"/>
<area linkends="link_reset" coords="200,9000 500,9000" id="reset"/>
<area linkends="link_bootloader" coords="1700,9000 1900,9000" id="bootloader"/>
<area linkends="link_test" coords="6500,8700 7000,8900" id="test"/>
<area linkends="link_erase" coords="7100,8700 7600,8900" id="erase"/>
</areaspec>
<imageobject>
<imagedata fileref="images/simtrace_surface.png" width="15cm" />
</imageobject>
<calloutlist>
<callout arearefs="usb" id="link_usb">
<para>USB: USB mini-B connector. The main connector. The
host software communicates (sniffing,...) through USB with
the board. It can also be used to flash the micro-controller
(using DFU).</para>
</callout>
<callout arearefs="serial" id="link_serial">
<para>serial: 2.5 mm jack serial cable, as used by osmocomBB
port used to debug the device (printf goes there).</para>
</callout>
<callout arearefs="debug" id="link_debug">
<para>debug (P3): same as serial, but using the FTDI
serial cable. It is recommended to cut the voltage wire of
the 6pin FTDI connector before plugging the cable into the
simtrace.
</para>
</callout>
<callout arearefs="jtag" id="link_jtag">
<para>jtag (P1): JTAG 20 pin connector to do hardware
assisted debugging.</para>
</callout>
<callout arearefs="bt1" id="link_bt1">
<para>BT1: battery connector (4.5-6V DC). normally the
USB provides power, but the battery port can be used
for autonomous use of SIMtrace. The sniffing can be saved
in the flash (U1).</para>
</callout>
<callout arearefs="ffc" id="link_ffc">
<para>FFC_SIM (P3): to connect the flat flexible cable with
SIM end for the phone.</para>
</callout>
<callout arearefs="sim" id="link_sim">
<para>SIM (P4): put your SIM in there (instead of in the
phone)</para>
</callout>
<callout arearefs="reset" id="link_reset">
<para>reset (SW1): to reset the board (not erasing the
firmware). If your are too lazy to unplug and re-plug
the USB.</para>
</callout>
<callout arearefs="bootloader" id="link_bootloader">
<para>bootloader (SW2): used to start the bootloader so
to flash the device using DFU. press when plugging in
the USB.</para>
</callout>
<callout arearefs="test" id="link_test">
<para>test (JP1): short circuit using a jumper to flash
using SAM-BA.</para>
</callout>
<callout arearefs="erase" id="link_erase">
<para>erase (JP2): short circuit using a jumper to erase
completely erase the firmware.</para>
</callout>
</calloutlist>
</imageobjectco>
</mediaobjectco>
</figure>
</para>
</section>
</chapter>

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@@ -0,0 +1,164 @@
<?xml version="1.0" encoding="UTF-8"?>
<chapter id="chapter_installation">
<title>Installation</title>
<para><application>SIMtrace</application> will need a patched version of
<application>wireshark</application> and the <command>simtrace</command>
host utility to fully operate. The installation might be possible from
binary packages or will require building from source. The following
sections provide some hints how to achieve this on the various Linux
distributions. All these operations must be executed as root.</para>
<note>
<title>Wireshark Patches</title>
<para>The SIMtrace patch has been upstreamed. Wireshark 1.7.1 was released
on April the 6th 2012 and is the first development release to support SIMtrace
out of the box. Wireshark 1.8 will be the first stable version.
</para>
</note>
<section id="install_ubuntu_natty">
<title>Installation Ubuntu Natty, Ubuntu Oneiric</title>
<para>Ubuntu Natty and Oneiric users can use the holger+lp/osmocom PPA to install
<application>SIMtrace</application> and upgrade wireshark. The PPA needs to
be added to the system, the package database needs to be refreshed
and the applications can be installed afterwards.</para>
<screen>
$ <command>sudo</command> <command>add-apt-repository</command> ppa:holger+lp/osmocom
[sudo] password for username:
Executing: gpg --ignore-time-conflict --no-options --no-default-keyring --secret-keyring /etc/apt/secring.gpg --trustdb-name /etc/apt/trustdb.gpg --keyring /etc/apt/trusted.gpg --primary-keyring /etc/apt/trusted.gpg --keyserver hkp://keyserver.ubuntu.com:80/ --recv 84C86214C00BAF820F43585CCABF944FA2AD19FA
gpg: requesting key A2AD19FA from hkp server keyserver.ubuntu.com
gpg: Total number processed: 1
gpg: unchanged: 1
</screen>
<para>The next step is to update the package database and install or upgrade
the <application>wireshark</application> application.</para>
<screen>
$ <command>sudo</command> <command>apt-get</command> update
...
$ <command>sudo</command> <command>apt-get</command> install wireshark simtrace
...
</screen>
<note><para>The wireshark will only be installed if it is newer than the version
provided by Ubuntu. Please verify that the above command installed a version
coming from the PPA.</para>
</note>
</section>
<section id="install_opensuse">
<title>Installation OpenSUSE</title>
<para>The installation on OpenSUSE uses zypper. The repository must be added
via the <command>zypper</command> application and then the binary packages
can be installed.</para>
<section>
<title>openSUSE 11.3</title>
<screen>
$ <command>zypper</command> addrepo http://download.opensuse.org/repositories/home:/zecke23/openSUSE_11.3/home:zecke23.repo
$ <command>zypper</command> refresh
$ <command>zypper</command> install wireshark simtrace
</screen>
</section>
<section>
<title>openSUSE 11.4</title>
<screen>
$ <command>zypper</command> addrepo http://download.opensuse.org/repositories/home:/zecke23/openSUSE_11.4/home:zecke23.repo
$ <command>zypper</command> refresh
$ <command>zypper</command> install wireshark simtrace
</screen>
</section>
<section>
<title>openSUSE 12.1</title>
<screen>
$ <command>zypper</command> addrepo http://download.opensuse.org/repositories/home:/zecke23/openSUSE_11.4/home:zecke23.repo
$ <command>zypper</command> refresh
$ <command>zypper</command> install wireshark simtrace
</screen>
</section>
</section>
<section id="install_fedora">
<title>Installation Fedora</title>
<section>
<title>Fedora 14</title>
<screen>
$ cd /etc/yum/repos.d/
$ wget http://download.opensuse.org/repositories/home:zecke23/Fedora_14/home:zecke23.repo
$ yum install wireshark simtrace
</screen>
</section>
<section>
<title>Fedora 15</title>
<screen>
$ cd /etc/yum/repos.d/
$ wget http://download.opensuse.org/repositories/home:zecke23/Fedora_15/home:zecke23.repo
$ yum install wireshark simtrace
</screen>
</section>
<section>
<title>Fedora 16</title>
<screen>
$ cd /etc/yum/repos.d/
$ wget http://download.opensuse.org/repositories/home:zecke23/Fedora_16/home:zecke23.repo
$ yum install wireshark simtrace
</screen>
</section>
</section>
<section id="install_centos">
<title>Installation CentOS</title>
<section>
<title>CentOS 5</title>
<screen>
$ cd /etc/yum/repos.d/
$ wget http://download.opensuse.org/repositories/home:zecke23/CentOS_CentOS-5/home:zecke23.repo
$ yum install wireshark simtrace
</screen>
</section>
<section>
<title>CentOS 6</title>
<screen>
$ cd /etc/yum/repos.d/
$ wget http://download.opensuse.org/repositories/home:zecke23/CentOS_CentOS-6/home:zecke23.repo
$ yum install wireshark simtrace
</screen>
</section>
</section>
<section id="install_mandriva">
<title>Mandriva</title>
<section>
<title>Mandriva 2010.1</title>
<screen>
$ urpmi.addmedia home:zecke23 http://download.opensuse.org/repositories/home:zecke23/Mandriva_2010.1/
$ urpmi.update -a
$ urpmi wireshark simtrace
</screen>
</section>
<section>
<title>Mandriva 2011</title>
<screen>
$ urpmi.addmedia home:zecke23 http://download.opensuse.org/repositories/home:zecke23/Mandriva_2011/
$ urpmi.update -a
$ urpmi wireshark simtrace
</screen>
</section>
</section>
<section id="installation_from_source">
<title>Installation from Source</title>
<para>Please see the <xref linkend="chapter_building"/></para>
</section>
</chapter>

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<?xml version="1.0" encoding="UTF-8"?>
<chapter id="chapter_introduction">
<title>Introduction</title>
<section id="intro_overview">
<title>History</title>
<para>SIMtrace was created out of necessity. Harald Welte wanted
to see the communication between a GSM Mobile Station (or
what we call a cellphone) and the SIM. He was not able to
find an existing solution, or the existing ones had mayor
drawbacks that made using them very time consuming and slow.
The Atmel AT91SAM7 came to the rescue. This microcontroller
has hardware support for the ISO7816 T0/T1 Smart Card
specification. We can connect the external clock to the UART
and are able to read bytes coming and going to the SIM.
The next step in the project was taken by Kevin Redon
that started to modify an existing AT91SAM7 design, started
to use the Free Software KiCAD CAD Software. In 2011 the project
went from having Schematics to having routed circuits, prototypes
and the final product. The first production run was in August.</para>
</section>
<section id="intro_picture">
<title>Overview</title>
<para>The setup of SIMtrace consists out of a Hardware and a
Software part. The SIM card needs to be put into the SIMtrace
Hardware, the flex cable needs to be connected to the SIMtrace
Hardware and the SIM end needs to be placed in the SIM socket
of the phone. The SIMtrace hardware can be seen as a USB device
from the host, the SIMtrace software will try to find this device
and claim it. The SIMtrace software will receive packets from the
SIMtrace hardware and can forward them using the GSMTAP protocol
to the IANA assigned GSMTAP port (4729). A modified version of Wireshark
can be used to analyze the data.</para>
<figure><title>Schematic Overview</title>
<mediaobject>
<imageobject>
<imagedata fileref="images/setup_overview.png" width="6cm"/>
</imageobject>
<textobject><phrase>SIMtrace being connected</phrase></textobject>
</mediaobject>
</figure>
</section>
</chapter>

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<?xml version="1.0" encoding="UTF-8"?>
<chapter id="chapter_sniff">
<title>Sniffing your SIM</title>
<section id="hw_setup">
<title>Connecting your device</title>
<para>You will need to put your SIM into the SIMtrace hardware, connect
one of the four flex cables to the SIMtrace hardware, put the other side
into the SIM socket of your phone. Use USB to connect the SIMtrace hardware
to the PC. On your PC you should be able to see the USB device now.</para>
<figure><title>Connecting the SIMtrace Hardware</title>
<mediaobject>
<imageobject>
<imagedata fileref="images/simtrace_hw_setup.png" width="15cm"/>
</imageobject>
<textobject><phrase>SIMtrace being connected</phrase></textobject>
</mediaobject>
</figure>
</section>
<section id="launching_simtrace">
<title>Launching SIMtrace</title>
<screen>
$ <command>./simtrace</command>
simtrace - GSM SIM and smartcard tracing
(C) 2010 by Harald Welte &lt;laforge@gnumonks.org&gt;
</screen>
<para>Launching the <command>simtrace</command> will try to find
the SIMtrace hardware and then try to claim the USB device. The
application will send the received data encapsulated in the GSMTAP
format on localhost and the IANA assigned GSMTAP port.</para>
</section>
<section id="launching_wireshark">
<title>Launching Wireshark</title>
<para>The <command>wireshark</command> application will start a GUI
and given the right permissions you should be able listen to the
localhost interface and filter for the GSMTAP port on 4729. You should
be able to see the decoded messages like in the figure below.</para>
<figure><title>GSMTAP in Wireshark</title>
<mediaobject>
<imageobject>
<imagedata fileref="images/wireshark-sim.png" width="16cm"/>
</imageobject>
<textobject><phrase>SIMtrace sending data</phrase></textobject>
</mediaobject>
</figure>
</section>
<section id="known_firmware_issues">
<title>Known Firmware Issues</title>
<section>
<title>Combined ATR/APDU message</title>
<para>For some cards the firmware does not send an USB message at
the end of the ATR. The ATR and first APDU will be send in one message
and the host utility fails to split APDUs and nothing will be traced.
A band-aid for the firmware exists and can be found on the mailinglist.
</para>
</section>
<section>
<title>Lost bytes</title>
<para>For some new high speed cards the firmware can lose bytes. The
issue appears to be when the received bytes will be copied to the memory
of the USB controller. The workaround is to reduce the size of the buffer.
</para>
</section>
</section>
<section id="other_modes">
<title>Other modes</title>
<para>The hardware is capable to be used as an ordinary card reader,
provide Man-In-The-Middle (MITM) attacks, or operate as a SIM. The
firmware currently does not have support for these modes.</para>
<para>The SIMtrace hardware supports ISO7816 Part 3 T=0/T=1 protocols,
it basically can be used to intercept and analyze any traffic from (ISO7816)
smart cards. This includes SIM cards, Pay TV cards (smart card for CAM),
ATM cards, chip credit card, PKI smart cards, e-passport etc. etc. However
watch out: You have to make your chip card fitting in the "SIM card size"
ID-000 reader or build another adapter.</para>
</section>
</chapter>

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docs/usermanual.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!--
ex:ts=4:sw=4:sts=4:et
-*- tab-width: 4; c-basic-offset: 4; indent-tabs-mode: nil -*-
-->
<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.2//EN"
"http://www.oasis-open.org/docbook/xml/4.2/docbookx.dtd" [
<!ENTITY chapter-introduction SYSTEM "chapters/introduction.xml">
<!ENTITY chapter-installation SYSTEM "chapters/installation.xml">
<!ENTITY chapter-hw-details SYSTEM "chapters/hardware_details.xml">
<!ENTITY chapter-using-sniff SYSTEM "chapters/using_sniff.xml">
<!ENTITY chapter-building SYSTEM "chapters/building.xml">
<!ENTITY chapter-firmware SYSTEM "chapters/firmware.xml">
<!ENTITY chapter-appendix SYSTEM "chapters/appendix.xml">
]>
<book>
<bookinfo>
<revhistory>
<revision>
<revnumber>0.0.1</revnumber>
<date>12 July 2011</date>
<authorinitials>z</authorinitials>
<revremark>Initial</revremark>
</revision>
<revision>
<revnumber>0.0.2</revnumber>
<date>14 August 2011</date>
<authorinitials>z</authorinitials>
<revremark>Copy HW Info from the Wiki</revremark>
</revision>
<revision>
<revnumber>0.0.3</revnumber>
<date>15 August 2011</date>
<authorinitials>z</authorinitials>
<revremark>Document building wireshark</revremark>
</revision>
<revision>
<revnumber>0.0.4</revnumber>
<date>8 October 2011</date>
<authorinitials>z</authorinitials>
<revremark>Document Firmware</revremark>
</revision>
<revision>
<revnumber>0.0.5</revnumber>
<date>10 January 2012</date>
<authorinitials>z</authorinitials>
<revremark>Add additional distro packages, mention the v0.4 firmware
update procedure, add some notes of the SAM-BA mode</revremark>
</revision>
</revhistory>
<title>SIMtrace Usermanual</title>
<copyright>
<year>2011-2012</year>
</copyright>
<legalnotice>
<para>This work is licensed under a Creative Commons Attribution 3.0
Unported License. To view a copy of this license, visit <ulink
url="http://creativecommons.org/licenses/by-sa/3.0/">http://creativecommons.org/licenses/by-sa/3.0/</ulink>
or send a letter to Creative Commons, 559 Nathan Abbott Way, Stanford,
California 94305, USA.</para>
</legalnotice>
</bookinfo>
<!-- Main chapters-->
&chapter-introduction;
&chapter-installation;
&chapter-hw-details;
&chapter-using-sniff;
&chapter-building;
&chapter-firmware;
&chapter-appendix;
</book>

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hardware/geda/Rakefile Normal file
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require 'rake/clean'
# ==============
# important info
# ==============
target = "simtrace"
version = IO.read("version").chomp
date = Time.now.strftime("%Y-%m-%d")
revision = `git log --pretty=oneline "#{target}.sch" | wc -l`.chomp.to_i
# symbol library for gschem
LIB = "lib/symbols/"
# gEDA scheme
GEDA_SCHEME_DIRS=["/usr/share/gEDA/scheme","/usr/local/gEDA/scheme"].collect{|path| File.directory?(path) ? path : nil}.compact
unless GEDA_SCHEME_DIRS.size==0 then
GEDA_SCHEME_DIR=GEDA_SCHEME_DIRS[0]
else
GEDA_SCHEME_DIR=nil
puts "warning: could not find gEDA scheme directory. can not print schematic"
end
# schema
sch = "#{target}.sch"
# schema with version
vsch = "#{target}_v#{version}.#{revision.to_s.rjust(3,'0')}.sch"
# ================
# helper functions
# ================
# read schema
# return a list of components
def read_sch(path)
# get all symbols
symbols = read_symbols(LIB)
# read schema
text = IO.read(path)
# parse all elements
elements = []
element = {}
block = false
text.each_line do |line|
l = line.chomp
if l=="{" then
block = true
element[:block] = {} unless element[:block]
elsif l=="}" then
block = false
elsif block then
# only take attributes
if l.include?("=") then
k,v = l.split("=")
element[:block][k] = v
end
elsif !block then
elements << element unless element.empty?
element = {}
element[:line] = l
element[:type] = l[0,1]
if element[:type]=="C" then
element[:symbol] = l.split(" ")[-1]
# get the default attributes (if any)
element[:block] = symbols[element[:symbol]].dup if symbols[element[:symbol]]
end
else
raise "don't know how to handle line: #{l}"
end
end
return elements
end
# read the attributes from a symbol
# return { name => value }
# warning: it only get uniq attributes (not multiple slots, ...)
def read_symbol(file)
text = IO.read(file)
symbol = {}
block = false
text.each_line do |line|
l = line.chomp
if l=="{" then
block = true
elsif l=="}" then
block = false
elsif block then
next
elsif l.include?("=") then
name = l.split("=")[0]
value = l.split("=")[1..-1]*"="
symbol[name] = value
else
next
end
end
return symbol
end
# read all symbols
# return a list fo symbols { name => symbol } (see read_symbol)
def read_symbols(folder)
symbols = {}
Dir.entries(folder).each do |file|
next unless file =~ /\.sym$/
symbols[file.split("/")[-1]] = read_symbol(folder+"/"+file)
end
return symbols
end
# =========
# the tasks
# =========
task :default => [:version,:print,:pdf,:install,:check]
desc "set version in schema"
task :version => vsch
CLEAN.include(vsch)
CLOBBER.include("#{target}_*.sch")
desc "print schema (into ps)"
task :print => "#{target}.ps"
CLEAN.include("#{target}.ps")
desc "get printed schema in pdf"
task :pdf => "#{target}.pdf"
CLEAN.include("#{target}.pdf")
desc "put printed schema in output folder"
task :install => "#{target}.pdf" do
mkdir "../pcb/schema" unless File.directory? "../pcb/schema"
cp "#{target}.pdf","../pcb/schema/#{target}.pdf"
end
CLOBBER.include("../pcb/schema/#{target}.pdf")
# every component should have: refdes without ?, device, value,
# footprint, manufacturer, documentation, digikey
task :check => sch do
elements = read_sch(sch)
elements.each do |element|
if element[:type]=="C" then
if element[:block] and element[:block]["refdes"] then
name = element[:block]["refdes"]
name += " (#{element[:block]['device']})" if element[:block]["device"]
puts name+" has no ID" if element[:block]["refdes"].include? "?"
["device","value","footprint","manufacturer","manufacturer-part","documentation","digikey-part"].each do |attribute|
puts name+" has no "+attribute unless element[:block][attribute]
break if element[:block]["footprint"] =~ /^HEADER/ or element[:block]["footprint"] =~ /^JUMPER/
end
end
end
end
end
# ===============
# file processing
# ===============
file vsch => sch do
sh "cp #{sch} #{vsch}"
# on \ is to prevent ruby interpreting it, th other is for sed
# the version
sh "sed -i 's/\\(version=\\)\\$Version\\$/\\1#{version}/' #{vsch}"
# the date
sh "sed -i 's/\\(date=\\)\\$Date\\$/\\1#{date}/' #{vsch}"
# the revision
sh "sed -i 's/\\(revision=\\)\\$Revision\\$/\\1#{revision}/' #{vsch}"
end
file "#{target}.ps" => vsch do
if GEDA_SCHEME_DIR then
sh "gschem -p -o #{target}.ps -s #{GEDA_SCHEME_DIR}/print.scm #{vsch} > /dev/null 2>&1"
else
puts "can not print schematic. gEDA scheme directory missing"
end
end
file "#{target}.pdf" => "#{target}.ps" do
sh "ps2pdf -sPAPERSIZE=a4 #{target}.ps"
end

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hardware/geda/gafrc Normal file
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; .sch gEDA configuration file
(define gedasymbols "lib")
(component-library (build-path gedasymbols "symbols"))

3
hardware/geda/gschemrc Normal file
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; gschem configuration file
(paper-size 11.69 8.27) ; A4
;(output-color "enabled") ; for color postscript output (black background)

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T 4345 2395 5 10 1 1 0 6 1
pinlabel=PA27/PGMD15
T 4495 2445 5 10 1 1 0 0 1
pinnumber=37
T 4700 2400 5 10 0 0 0 0 1
pinseq=37
}
P 4700 2200 4400 2200 1 0 0
{
T 4700 2200 5 10 0 0 0 0 1
pintype=unknown
T 4345 2195 5 10 1 1 0 6 1
pinlabel=PA28
T 4495 2245 5 10 1 1 0 0 1
pinnumber=38
T 4700 2200 5 10 0 0 0 0 1
pinseq=38
}
P 0 7800 300 7800 1 0 0
{
T 0 7800 5 10 0 0 180 0 1
pintype=unknown
T 355 7795 5 10 1 1 0 0 1
pinlabel=NRST
T 205 7845 5 10 1 1 0 6 1
pinnumber=39
T 0 7800 5 10 0 0 180 0 1
pinseq=39
}
P 0 7600 300 7600 1 0 0
{
T 0 7600 5 10 0 0 180 0 1
pintype=unknown
T 355 7595 5 10 1 1 0 0 1
pinlabel=TST
T 205 7645 5 10 1 1 0 6 1
pinnumber=40
T 0 7600 5 10 0 0 180 0 1
pinseq=40
}
P 4700 2000 4400 2000 1 0 0
{
T 4700 2000 5 10 0 0 0 0 1
pintype=unknown
T 4345 1995 5 10 1 1 0 6 1
pinlabel=PA29
T 4495 2045 5 10 1 1 0 0 1
pinnumber=41
T 4700 2000 5 10 0 0 0 0 1
pinseq=41
}
P 4700 1800 4400 1800 1 0 0
{
T 4700 1800 5 10 0 0 0 0 1
pintype=unknown
T 4345 1795 5 10 1 1 0 6 1
pinlabel=PA30
T 4495 1845 5 10 1 1 0 0 1
pinnumber=42
T 4700 1800 5 10 0 0 0 0 1
pinseq=42
}
P 4700 7200 4400 7200 1 0 0
{
T 4700 7200 5 10 0 0 0 0 1
pintype=unknown
T 4345 7195 5 10 1 1 0 6 1
pinlabel=PA3
T 4495 7245 5 10 1 1 0 0 1
pinnumber=43
T 4700 7200 5 10 0 0 0 0 1
pinseq=43
}
P 4700 7400 4400 7400 1 0 0
{
T 4700 7400 5 10 0 0 0 0 1
pintype=unknown
T 4345 7395 5 10 1 1 0 6 1
pinlabel=PA2/PGMEN2
T 4495 7445 5 10 1 1 0 0 1
pinnumber=44
T 4700 7400 5 10 0 0 0 0 1
pinseq=44
}
P 0 4000 300 4000 1 0 0
{
T 0 4000 5 10 0 0 180 0 1
pintype=unknown
T 355 3995 5 10 1 1 0 0 1
pinlabel=VDDIO
T 205 4045 5 10 1 1 0 6 1
pinnumber=45
T 0 4000 5 10 0 0 180 0 1
pinseq=45
}
P 0 1400 300 1400 1 0 0
{
T 0 1400 5 10 0 0 180 0 1
pintype=unknown
T 355 1395 5 10 1 1 0 0 1
pinlabel=GND
T 205 1445 5 10 1 1 0 6 1
pinnumber=46
T 0 1400 5 10 0 0 180 0 1
pinseq=46
}
P 4700 7600 4400 7600 1 0 0
{
T 4700 7600 5 10 0 0 0 0 1
pintype=unknown
T 4345 7595 5 10 1 1 0 6 1
pinlabel=PA1/PGMEN1
T 4495 7645 5 10 1 1 0 0 1
pinnumber=47
T 4700 7600 5 10 0 0 0 0 1
pinseq=47
}
P 4700 7800 4400 7800 1 0 0
{
T 4700 7800 5 10 0 0 0 0 1
pintype=unknown
T 4345 7795 5 10 1 1 0 6 1
pinlabel=PA0/PGMEN0
T 4495 7845 5 10 1 1 0 0 1
pinnumber=48
T 4700 7800 5 10 0 0 0 0 1
pinseq=48
}
P 0 6800 300 6800 1 0 0
{
T 0 6800 5 10 0 0 180 0 1
pintype=unknown
T 355 6795 5 10 1 1 0 0 1
pinlabel=TDO/TRACESWO/PB5
T 205 6845 5 10 1 1 0 6 1
pinnumber=49
T 0 6800 5 10 0 0 180 0 1
pinseq=49
}
P 0 6200 300 6200 1 0 0
{
T 0 6200 5 10 0 0 180 0 1
pintype=unknown
T 355 6195 5 10 1 1 0 0 1
pinlabel=JTAGSEL
T 205 6245 5 10 1 1 0 6 1
pinnumber=50
T 0 6200 5 10 0 0 180 0 1
pinseq=50
}
P 0 6600 300 6600 1 0 0
{
T 0 6600 5 10 0 0 180 0 1
pintype=unknown
T 355 6595 5 10 1 1 0 0 1
pinlabel=TMS/SWDIO/PB6
T 205 6645 5 10 1 1 0 6 1
pinnumber=51
T 0 6600 5 10 0 0 180 0 1
pinseq=51
}
P 4700 1600 4400 1600 1 0 0
{
T 4700 1600 5 10 0 0 0 0 1
pintype=unknown
T 4345 1595 5 10 1 1 0 6 1
pinlabel=PA31
T 4495 1645 5 10 1 1 0 0 1
pinnumber=52
T 4700 1600 5 10 0 0 0 0 1
pinseq=52
}
P 0 6400 300 6400 1 0 0
{
T 0 6400 5 10 0 0 180 0 1
pintype=unknown
T 355 6395 5 10 1 1 0 0 1
pinlabel=TCK/SWCLK/PB7
T 205 6445 5 10 1 1 0 6 1
pinnumber=53
T 0 6400 5 10 0 0 180 0 1
pinseq=53
}
P 0 2200 300 2200 1 0 0
{
T 0 2200 5 10 0 0 180 0 1
pintype=unknown
T 355 2195 5 10 1 1 0 0 1
pinlabel=VDDCORE
T 205 2245 5 10 1 1 0 6 1
pinnumber=54
T 0 2200 5 10 0 0 180 0 1
pinseq=54
}
P 0 7400 300 7400 1 0 0
{
T 0 7400 5 10 0 0 180 0 1
pintype=unknown
T 355 7395 5 10 1 1 0 0 1
pinlabel=ERASE/PB12
T 205 7445 5 10 1 1 0 6 1
pinnumber=55
T 0 7400 5 10 0 0 180 0 1
pinseq=55
}
P 0 5800 300 5800 1 0 0
{
T 0 5800 5 10 0 0 180 0 1
pintype=unknown
T 355 5795 5 10 1 1 0 0 1
pinlabel=DDM/PB10
T 205 5845 5 10 1 1 0 6 1
pinnumber=56
T 0 5800 5 10 0 0 180 0 1
pinseq=56
}
P 0 5600 300 5600 1 0 0
{
T 0 5600 5 10 0 0 180 0 1
pintype=unknown
T 355 5595 5 10 1 1 0 0 1
pinlabel=DDP/PB11
T 205 5645 5 10 1 1 0 6 1
pinnumber=57
T 0 5600 5 10 0 0 180 0 1
pinseq=57
}
P 0 3800 300 3800 1 0 0
{
T 0 3800 5 10 0 0 180 0 1
pintype=unknown
T 355 3795 5 10 1 1 0 0 1
pinlabel=VDDIO
T 205 3845 5 10 1 1 0 6 1
pinnumber=58
T 0 3800 5 10 0 0 180 0 1
pinseq=58
}
P 0 800 300 800 1 0 0
{
T 0 800 5 10 0 0 180 0 1
pintype=unknown
T 355 795 5 10 1 1 0 0 1
pinlabel=PB13/DAC0
T 205 845 5 10 1 1 0 6 1
pinnumber=59
T 0 800 5 10 0 0 180 0 1
pinseq=59
}
P 0 1200 300 1200 1 0 0
{
T 0 1200 5 10 0 0 180 0 1
pintype=unknown
T 355 1195 5 10 1 1 0 0 1
pinlabel=GND
T 205 1245 5 10 1 1 0 6 1
pinnumber=60
T 0 1200 5 10 0 0 180 0 1
pinseq=60
}
P 0 5200 300 5200 1 0 0
{
T 0 5200 5 10 0 0 180 0 1
pintype=unknown
T 355 5195 5 10 1 1 0 0 1
pinlabel=XOUT/PB8
T 205 5245 5 10 1 1 0 6 1
pinnumber=61
T 0 5200 5 10 0 0 180 0 1
pinseq=61
}
P 0 5000 300 5000 1 0 0
{
T 0 5000 5 10 0 0 180 0 1
pintype=unknown
T 355 4995 5 10 1 1 0 0 1
pinlabel=XIN/PGMCK/PB9
T 205 5045 5 10 1 1 0 6 1
pinnumber=62
T 0 5000 5 10 0 0 180 0 1
pinseq=62
}
P 0 600 300 600 1 0 0
{
T 0 600 5 10 0 0 180 0 1
pintype=unknown
T 355 595 5 10 1 1 0 0 1
pinlabel=PB14/DAC1
T 205 645 5 10 1 1 0 6 1
pinnumber=63
T 0 600 5 10 0 0 180 0 1
pinseq=63
}
P 0 3000 300 3000 1 0 0
{
T 0 3000 5 10 0 0 180 0 1
pintype=unknown
T 355 2995 5 10 1 1 0 0 1
pinlabel=VDDPLL
T 205 3045 5 10 1 1 0 6 1
pinnumber=64
T 0 3000 5 10 0 0 180 0 1
pinseq=64
}
P 4700 1000 4400 1000 1 0 0
{
T 4700 1000 5 10 0 0 180 0 1
pintype=unknown
T 4345 995 5 10 1 1 0 6 1
pinlabel=PB1/AD5
T 4495 1045 5 10 1 1 0 0 1
pinnumber=4
T 4700 1000 5 10 0 0 180 0 1
pinseq=4
}
P 4700 800 4400 800 1 0 0
{
T 4700 800 5 10 0 0 180 0 1
pintype=unknown
T 4345 795 5 10 1 1 0 6 1
pinlabel=PB2/AD6
T 4495 845 5 10 1 1 0 0 1
pinnumber=5
T 4700 800 5 10 0 0 180 0 1
pinseq=5
}
P 4700 600 4400 600 1 0 0
{
T 4700 600 5 10 0 0 180 0 1
pintype=unknown
T 4345 595 5 10 1 1 0 6 1
pinlabel=PB3/AD7
T 4495 645 5 10 1 1 0 0 1
pinnumber=6
T 4700 600 5 10 0 0 180 0 1
pinseq=6
}
P 0 4600 300 4600 1 0 0
{
T 0 4600 5 10 0 0 0 0 1
pintype=unknown
T 355 4595 5 10 1 1 0 0 1
pinlabel=VDDIN
T 205 4645 5 10 1 1 0 6 1
pinnumber=7
T 0 4600 5 10 0 0 0 0 1
pinseq=7
}
P 0 3400 300 3400 1 0 0
{
T 0 3400 5 10 0 0 0 0 1
pintype=unknown
T 355 3395 5 10 1 1 0 0 1
pinlabel=VDDOUT
T 205 3445 5 10 1 1 0 6 1
pinnumber=8
T 0 3400 5 10 0 0 0 0 1
pinseq=8
}
P 4700 4400 4400 4400 1 0 0
{
T 4700 4400 5 10 0 0 180 0 1
pintype=unknown
T 4345 4395 5 10 1 1 0 6 1
pinlabel=PA17/PGMD5/AD0
T 4495 4445 5 10 1 1 0 0 1
pinnumber=9
T 4700 4400 5 10 0 0 180 0 1
pinseq=9
}
P 4700 4200 4400 4200 1 0 0
{
T 4700 4200 5 10 0 0 180 0 1
pintype=unknown
T 4345 4195 5 10 1 1 0 6 1
pinlabel=PA18/PGMD6/AD1
T 4495 4245 5 10 1 1 0 0 1
pinnumber=10
T 4700 4200 5 10 0 0 180 0 1
pinseq=10
}
P 4700 3600 4400 3600 1 0 0
{
T 4700 3600 5 10 0 0 180 0 1
pintype=unknown
T 4345 3595 5 10 1 1 0 6 1
pinlabel=PA21/PGMD9/AD8
T 4495 3645 5 10 1 1 0 0 1
pinnumber=11
T 4700 3600 5 10 0 0 180 0 1
pinseq=11
}
P 0 2600 300 2600 1 0 0
{
T 0 2600 5 10 0 0 0 0 1
pintype=unknown
T 355 2595 5 10 1 1 0 0 1
pinlabel=VDDCORE
T 205 2645 5 10 1 1 0 6 1
pinnumber=12
T 0 2600 5 10 0 0 0 0 1
pinseq=12
}
P 4700 4000 4400 4000 1 0 0
{
T 4700 4000 5 10 0 0 180 0 1
pintype=unknown
T 4345 3995 5 10 1 1 0 6 1
pinlabel=PA19/PGMD7/AD2
T 4495 4045 5 10 1 1 0 0 1
pinnumber=13
T 4700 4000 5 10 0 0 180 0 1
pinseq=13
}
P 4700 3400 4400 3400 1 0 0
{
T 4700 3400 5 10 0 0 180 0 1
pintype=unknown
T 4345 3395 5 10 1 1 0 6 1
pinlabel=PA22/PGMD11/AD9
T 4495 3445 5 10 1 1 0 0 1
pinnumber=14
T 4700 3400 5 10 0 0 180 0 1
pinseq=14
}
P 4700 3200 4400 3200 1 0 0
{
T 4700 3200 5 10 0 0 180 0 1
pintype=unknown
T 4345 3195 5 10 1 1 0 6 1
pinlabel=PA23/PGMD11
T 4495 3245 5 10 1 1 0 0 1
pinnumber=15
T 4700 3200 5 10 0 0 180 0 1
pinseq=15
}
P 4700 3800 4400 3800 1 0 0
{
T 4700 3800 5 10 0 0 180 0 1
pintype=unknown
T 4345 3795 5 10 1 1 0 6 1
pinlabel=PA20/PGMD8/AD3
T 4495 3845 5 10 1 1 0 0 1
pinnumber=16
T 4700 3800 5 10 0 0 180 0 1
pinseq=16
}
P 0 1600 300 1600 1 0 0
{
T 0 1600 5 10 0 0 0 0 1
pintype=unknown
T 355 1595 5 10 1 1 0 0 1
pinlabel=GND
T 205 1645 5 10 1 1 0 6 1
pinnumber=17
T 0 1600 5 10 0 0 0 0 1
pinseq=17
}
P 0 4200 300 4200 1 0 0
{
T 0 4200 5 10 0 0 0 0 1
pintype=unknown
T 355 4195 5 10 1 1 0 0 1
pinlabel=VDDIO
T 205 4245 5 10 1 1 0 6 1
pinnumber=18
T 0 4200 5 10 0 0 0 0 1
pinseq=18
}
P 4700 4600 4400 4600 1 0 0
{
T 4700 4600 5 10 0 0 180 0 1
pintype=unknown
T 4345 4595 5 10 1 1 0 6 1
pinlabel=PA16/PGMD4
T 4495 4645 5 10 1 1 0 0 1
pinnumber=19
T 4700 4600 5 10 0 0 180 0 1
pinseq=19
}
P 4700 4800 4400 4800 1 0 0
{
T 4700 4800 5 10 0 0 180 0 1
pintype=unknown
T 4345 4795 5 10 1 1 0 6 1
pinlabel=PA15/PGMD3
T 4495 4845 5 10 1 1 0 0 1
pinnumber=20
T 4700 4800 5 10 0 0 180 0 1
pinseq=20
}
P 4700 5000 4400 5000 1 0 0
{
T 4700 5000 5 10 0 0 180 0 1
pintype=unknown
T 4345 4995 5 10 1 1 0 6 1
pinlabel=PA14/PGMD2
T 4495 5045 5 10 1 1 0 0 1
pinnumber=21
T 4700 5000 5 10 0 0 180 0 1
pinseq=21
}
P 4700 5200 4400 5200 1 0 0
{
T 4700 5200 5 10 0 0 180 0 1
pintype=unknown
T 4345 5195 5 10 1 1 0 6 1
pinlabel=PA13/PGMD1
T 4495 5245 5 10 1 1 0 0 1
pinnumber=22
T 4700 5200 5 10 0 0 180 0 1
pinseq=22
}
P 4700 3000 4400 3000 1 0 0
{
T 4700 3000 5 10 0 0 180 0 1
pintype=unknown
T 4345 2995 5 10 1 1 0 6 1
pinlabel=PA24/PGMD12
T 4495 3045 5 10 1 1 0 0 1
pinnumber=23
T 4700 3000 5 10 0 0 180 0 1
pinseq=23
}
P 0 2400 300 2400 1 0 0
{
T 0 2400 5 10 0 0 0 0 1
pintype=unknown
T 355 2395 5 10 1 1 0 0 1
pinlabel=VDDCORE
T 205 2445 5 10 1 1 0 6 1
pinnumber=24
T 0 2400 5 10 0 0 0 0 1
pinseq=24
}
P 4700 2800 4400 2800 1 0 0
{
T 4700 2800 5 10 0 0 180 0 1
pintype=unknown
T 4345 2795 5 10 1 1 0 6 1
pinlabel=PA25/PGMD13
T 4495 2845 5 10 1 1 0 0 1
pinnumber=25
T 4700 2800 5 10 0 0 180 0 1
pinseq=25
}
P 4700 2600 4400 2600 1 0 0
{
T 4700 2600 5 10 0 0 180 0 1
pintype=unknown
T 4345 2595 5 10 1 1 0 6 1
pinlabel=PA26/PGMD14
T 4495 2645 5 10 1 1 0 0 1
pinnumber=26
T 4700 2600 5 10 0 0 180 0 1
pinseq=26
}
P 4700 5400 4400 5400 1 0 0
{
T 4700 5400 5 10 0 0 180 0 1
pintype=unknown
T 4345 5395 5 10 1 1 0 6 1
pinlabel=PA12/PGMD0
T 4495 5445 5 10 1 1 0 0 1
pinnumber=27
T 4700 5400 5 10 0 0 180 0 1
pinseq=27
}
P 4700 5600 4400 5600 1 0 0
{
T 4700 5600 5 10 0 0 180 0 1
pintype=unknown
T 4345 5595 5 10 1 1 0 6 1
pinlabel=PA11/PGMM3
T 4495 5645 5 10 1 1 0 0 1
pinnumber=28
T 4700 5600 5 10 0 0 180 0 1
pinseq=28
}
P 4700 5800 4400 5800 1 0 0
{
T 4700 5800 5 10 0 0 180 0 1
pintype=unknown
T 4345 5795 5 10 1 1 0 6 1
pinlabel=PA10/PGMM2
T 4495 5845 5 10 1 1 0 0 1
pinnumber=29
T 4700 5800 5 10 0 0 180 0 1
pinseq=29
}
P 4700 6200 4400 6200 1 0 0
{
T 4700 6200 5 10 0 0 180 0 1
pintype=unknown
T 4345 6195 5 10 1 1 0 6 1
pinlabel=PA8/XOUT32/PGMM0
T 4495 6245 5 10 1 1 0 0 1
pinnumber=31
T 4700 6200 5 10 0 0 180 0 1
pinseq=31
}
P 4700 6400 4400 6400 1 0 0
{
T 4700 6400 5 10 0 0 180 0 1
pintype=unknown
T 4345 6395 5 10 1 1 0 6 1
pinlabel=PA7/XIN32/PGMNVALID
T 4495 6445 5 10 1 1 0 0 1
pinnumber=32
T 4700 6400 5 10 0 0 180 0 1
pinseq=32
}
P 4700 6000 4400 6000 1 0 0
{
T 4700 6000 5 10 0 0 180 0 1
pintype=unknown
T 4345 5995 5 10 1 1 0 6 1
pinlabel=PA9/PGMM1
T 4495 6045 5 10 1 1 0 0 1
pinnumber=30
T 4700 6000 5 10 0 0 180 0 1
pinseq=30
}
B 300 0 4100 8000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 8100 8 10 1 1 0 0 1
refdes=IC?
T 300 8500 8 10 0 0 0 0 1
device=AT91SAM3SXB
T 300 8700 8 10 0 0 0 0 1
description=Atmel AT91SAM3S1/2/4B microprocessor
T 300 9100 8 10 0 0 0 0 1
footprint=LQFP64
T 300 9300 8 10 0 0 0 0 1
alt-footprint=QFN64
T 300 8300 8 10 0 0 0 0 1
documentation=http://www.atmel.com/dyn/resources/prod_documents/doc6500.pdf
T 300 8900 8 10 0 0 0 0 1
manufacturer=Atmel

View File

@@ -0,0 +1,78 @@
v 20110115 2
P 0 1000 400 1000 1 0 0
{
T 0 1000 5 10 0 0 0 0 1
pintype=pwr
T 455 995 5 10 1 1 0 0 1
pinlabel=VIN
T 305 1045 5 10 1 1 0 6 1
pinnumber=5
T 0 1000 5 10 0 0 0 0 1
pinseq=5
}
P 0 700 400 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=in
T 455 695 5 10 1 1 0 0 1
pinlabel=EN1
T 305 745 5 10 1 1 0 6 1
pinnumber=4
T 0 700 5 10 0 0 0 0 1
pinseq=4
}
P 0 400 400 400 1 0 0
{
T 0 400 5 10 0 0 0 0 1
pintype=in
T 455 395 5 10 1 1 0 0 1
pinlabel=EN2
T 305 445 5 10 1 1 0 6 1
pinnumber=3
T 0 400 5 10 0 0 0 0 1
pinseq=3
}
P 2000 1000 1600 1000 1 0 0
{
T 2000 1000 5 10 0 0 0 0 1
pintype=pwr
T 1545 995 5 10 1 1 0 6 1
pinlabel=VOUT1
T 1695 1045 5 10 1 1 0 0 1
pinnumber=6
T 2000 1000 5 10 0 0 0 0 1
pinseq=6
}
P 2000 700 1600 700 1 0 0
{
T 2000 700 5 10 0 0 0 0 1
pintype=pwr
T 1545 695 5 10 1 1 0 6 1
pinlabel=VOUT2
T 1695 745 5 10 1 1 0 0 1
pinnumber=1
T 2000 700 5 10 0 0 0 0 1
pinseq=1
}
P 2000 400 1600 400 1 0 0
{
T 2000 400 5 10 0 0 0 0 1
pintype=pwr
T 1545 395 5 10 1 1 0 6 1
pinlabel=GND
T 1695 445 5 10 1 1 0 0 1
pinnumber=2
T 2000 400 5 10 0 0 0 0 1
pinseq=2
}
B 400 200 1200 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1300 8 10 1 1 0 0 1
refdes=IC?
T 400 1900 8 10 0 0 0 0 1
device=AP7332-SOT26
T 400 1700 8 10 0 0 0 0 1
description=dual 300mA LDO voltage regulator
T 400 1500 8 10 0 0 0 0 1
footprint=SOT26
T 500 0 9 10 1 0 0 0 1
LDO AP7332

View File

@@ -0,0 +1,234 @@
v 20091004 2
P 300 900 0 900 1 0 1
{
T 275 925 5 10 1 1 0 6 1
pinnumber=2
T 300 900 5 10 0 1 0 6 1
pinseq=2
T 325 900 3 10 1 1 0 1 1
pinlabel=VDD
T 300 900 2 10 0 1 0 5 1
pintype=pwr
}
P 300 1200 0 1200 1 0 1
{
T 275 1225 5 10 1 1 0 6 1
pinnumber=4
T 300 1200 5 10 0 1 0 6 1
pinseq=4
T 325 1200 3 10 1 1 0 1 1
pinlabel=GND
T 300 1200 2 10 0 1 0 5 1
pintype=pwr
}
P 300 1500 0 1500 1 0 1
{
T 275 1525 5 10 1 1 0 6 1
pinnumber=6
T 300 1500 5 10 0 1 0 6 1
pinseq=6
T 325 1500 3 10 1 1 0 1 1
pinlabel=GND
T 300 1500 2 10 0 1 0 5 1
pintype=pwr
}
P 300 1800 0 1800 1 0 1
{
T 275 1825 5 10 1 1 0 6 1
pinnumber=8
T 300 1800 5 10 0 1 0 6 1
pinseq=8
T 325 1800 3 10 1 1 0 1 1
pinlabel=GND
T 300 1800 2 10 0 1 0 5 1
pintype=pwr
}
P 300 2100 0 2100 1 0 1
{
T 275 2125 5 10 1 1 0 6 1
pinnumber=10
T 300 2100 5 10 0 1 0 6 1
pinseq=10
T 325 2100 3 10 1 1 0 1 1
pinlabel=GND
T 300 2100 2 10 0 1 0 5 1
pintype=pwr
}
P 300 2400 0 2400 1 0 1
{
T 275 2425 5 10 1 1 0 6 1
pinnumber=12
T 300 2400 5 10 0 1 0 6 1
pinseq=12
T 325 2400 3 10 1 1 0 1 1
pinlabel=GND
T 300 2400 2 10 0 1 0 5 1
pintype=pwr
}
P 300 2700 0 2700 1 0 1
{
T 275 2725 5 10 1 1 0 6 1
pinnumber=14
T 300 2700 5 10 0 1 0 6 1
pinseq=14
T 325 2700 3 10 1 1 0 1 1
pinlabel=GND
T 300 2700 2 10 0 1 0 5 1
pintype=pwr
}
P 300 3000 0 3000 1 0 1
{
T 275 3025 5 10 1 1 0 6 1
pinnumber=16
T 300 3000 5 10 0 1 0 6 1
pinseq=16
T 325 3000 3 10 1 1 0 1 1
pinlabel=GND
T 300 3000 2 10 0 1 0 5 1
pintype=pwr
}
P 300 3300 0 3300 1 0 1
{
T 275 3325 5 10 1 1 0 6 1
pinnumber=18
T 300 3300 5 10 0 1 0 6 1
pinseq=18
T 325 3300 3 10 1 1 0 1 1
pinlabel=GND
T 300 3300 2 10 0 1 0 5 1
pintype=pwr
}
P 300 3600 0 3600 1 0 1
{
T 275 3625 5 10 1 1 0 6 1
pinnumber=20
T 300 3600 5 10 0 1 0 6 1
pinseq=20
T 325 3600 3 10 1 1 0 1 1
pinlabel=GND
T 300 3600 2 10 0 1 0 5 1
pintype=pwr
}
P 2300 900 2600 900 1 0 1
{
T 2325 925 5 10 1 1 0 0 1
pinnumber=1
T 2300 900 5 10 0 1 0 6 1
pinseq=1
T 2275 900 3 10 1 1 0 7 1
pinlabel=VTREF
T 2300 900 2 10 0 1 0 5 1
pintype=io
}
P 2300 1200 2600 1200 1 0 1
{
T 2325 1225 5 10 1 1 0 0 1
pinnumber=3
T 2300 1200 5 10 0 1 0 6 1
pinseq=3
T 2275 1200 3 10 1 1 0 7 1
pinlabel=NTRST
T 2300 1200 2 10 0 1 0 5 1
pintype=io
}
P 2300 1500 2600 1500 1 0 1
{
T 2325 1525 5 10 1 1 0 0 1
pinnumber=5
T 2300 1500 5 10 0 1 0 6 1
pinseq=5
T 2275 1500 3 10 1 1 0 7 1
pinlabel=TDI
T 2300 1500 2 10 0 1 0 5 1
pintype=in
}
P 2300 1800 2600 1800 1 0 1
{
T 2325 1825 5 10 1 1 0 0 1
pinnumber=7
T 2300 1800 5 10 0 1 0 6 1
pinseq=7
T 2275 1800 3 10 1 1 0 7 1
pinlabel=TMS
T 2300 1800 2 10 0 1 0 5 1
pintype=io
}
P 2300 2100 2600 2100 1 0 1
{
T 2325 2125 5 10 1 1 0 0 1
pinnumber=9
T 2300 2100 5 10 0 1 0 6 1
pinseq=9
T 2275 2100 3 10 1 1 0 7 1
pinlabel=TCK
T 2300 2100 2 10 0 1 0 5 1
pintype=out
}
P 2300 2400 2600 2400 1 0 1
{
T 2325 2425 5 10 1 1 0 0 1
pinnumber=11
T 2300 2400 5 10 0 1 0 6 1
pinseq=11
T 2275 2400 3 10 1 1 0 7 1
pinlabel=RTCK
T 2300 2400 2 10 0 1 0 5 1
pintype=io
}
P 2300 2700 2600 2700 1 0 1
{
T 2325 2725 5 10 1 1 0 0 1
pinnumber=13
T 2300 2700 5 10 0 1 0 6 1
pinseq=13
T 2275 2700 3 10 1 1 0 7 1
pinlabel=TDO
T 2300 2700 2 10 0 1 0 5 1
pintype=out
}
P 2300 3000 2600 3000 1 0 1
{
T 2325 3025 5 10 1 1 0 0 1
pinnumber=15
T 2300 3000 5 10 0 1 0 6 1
pinseq=15
T 2275 3000 3 10 1 1 0 7 1
pinlabel=NSRST
T 2300 3000 2 10 0 1 0 5 1
pintype=io
}
P 2300 3300 2600 3300 1 0 1
{
T 2325 3325 5 10 1 1 0 0 1
pinnumber=17
T 2300 3300 5 10 0 1 0 6 1
pinseq=17
T 2275 3300 3 10 1 1 0 7 1
pinlabel=DBGRQ
T 2300 3300 2 10 0 1 0 5 1
pintype=io
}
P 2300 3600 2600 3600 1 0 1
{
T 2325 3625 5 10 1 1 0 0 1
pinnumber=19
T 2300 3600 5 10 0 1 0 6 1
pinseq=19
T 2275 3600 3 10 1 1 0 7 1
pinlabel=DBGACK
T 2300 3600 2 10 0 1 0 5 1
pintype=io
}
B 300 300 2000 3900 3 10 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1300 2250 2 10 1 1 0 4 1
JTAG
T 0 0 0 1 0 0 0 0 1
device=ARMJTAGCONN
T 2350 4250 5 10 1 1 0 0 1
refdes=J?
T 0 0 0 1 0 0 0 0 1
footprint=
T 0 0 0 1 0 0 0 0 1
description=ARM JTAG Connectro (20 pins)
T 0 0 0 1 0 0 0 0 1
numslots=0

View File

@@ -0,0 +1,76 @@
v 20110115 2
L 600 800 500 600 3 0 0 0 -1 -1
L 500 600 400 800 3 0 0 0 -1 -1
L 400 800 600 800 3 0 0 0 -1 -1
L 600 350 400 350 3 0 0 0 -1 -1
L 600 300 400 300 3 0 0 0 -1 -1
V 500 550 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 500 500 500 350 3 0 0 0 -1 -1
L 550 200 550 300 3 0 0 0 -1 -1
L 450 300 450 200 3 0 0 0 -1 -1
L 700 200 550 200 3 0 0 0 -1 -1
L 450 200 300 200 3 0 0 0 -1 -1
L 500 800 500 1000 3 0 0 0 -1 -1
P 1000 200 700 200 1 0 0
{
T 1000 200 5 10 0 0 180 0 1
pintype=io
T 605 -5 5 10 1 1 0 0 1
pinlabel=B
T 800 0 5 10 0 1 0 0 1
pinseq=3
T 800 300 5 10 1 1 0 0 1
pinnumber=3
}
P 500 1300 500 1000 1 0 0
{
T 900 1000 5 10 0 0 180 0 1
pintype=in
T 605 1102 5 10 1 1 0 0 1
pinlabel=\_OE\_
T 1000 1100 5 10 0 1 0 0 1
pinseq=1
T 300 1100 5 10 1 1 0 0 1
pinnumber=1
}
T 0 1300 8 10 1 1 0 0 1
netname=IC?
T 100 1600 8 10 0 0 0 0 1
device=CB3Q3244
T 100 1800 8 10 0 0 0 0 1
description=2x4-bit FET bus switch
P 0 200 300 200 1 0 0
{
T 0 200 5 10 0 0 180 0 1
pintype=io
T 300 -5 5 10 1 1 0 0 1
pinlabel=A
T 100 0 5 10 0 1 0 0 1
pinseq=2
T 100 300 5 10 1 1 0 0 1
pinnumber=2
}
T 100 2000 8 10 0 0 0 0 1
net=GND:10
T 100 2200 8 10 0 0 0 0 1
net=VCC:20
T 100 2400 8 10 0 0 0 0 1
slotdef=1:1,2,18
T 100 2600 8 10 0 0 0 0 1
slotdef=2:1,4,16
T 100 2800 8 10 0 0 0 0 1
slotdef=3:1,6,14
T 100 3000 8 10 0 0 0 0 1
slotdef=4:1,8,12
T 100 3200 8 10 0 0 0 0 1
slotdef=5:19,11,9
T 100 3400 8 10 0 0 0 0 1
slotdef=6:19,13,7
T 100 3600 8 10 0 0 0 0 1
slotdef=7:19,15,5
T 100 3800 8 10 0 0 0 0 1
slotdef=8:19,17,3
T 100 4000 8 10 0 0 0 0 1
numslots=8
T 700 500 8 10 1 0 0 0 1
slot=1

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@@ -0,0 +1,67 @@
v 20110115 2
P 0 900 300 900 1 0 0
{
T 0 900 5 10 0 0 0 0 1
pintype=pwr
T 355 895 5 10 1 1 0 0 1
pinlabel=VIN
T 205 945 5 10 1 1 0 6 1
pinnumber=5
T 0 900 5 10 0 0 0 0 1
pinseq=5
}
P 0 600 300 600 1 0 0
{
T 0 600 5 10 0 0 0 0 1
pintype=in
T 355 595 5 10 1 1 0 0 1
pinlabel=ON
T 205 645 5 10 1 1 0 6 1
pinnumber=4
T 0 600 5 10 0 0 0 0 1
pinseq=4
}
P 1000 0 1000 300 1 0 0
{
T 1000 0 5 10 0 0 0 0 1
pintype=pwr
T 1145 500 5 10 1 1 180 0 1
pinlabel=GND
T 950 205 5 10 1 1 90 6 1
pinnumber=2
T 1000 0 5 10 0 0 0 0 1
pinseq=2
}
P 2000 600 1700 600 1 0 0
{
T 2000 600 5 10 0 0 0 0 1
pintype=out
T 1645 595 5 10 1 1 0 6 1
pinlabel=FLAGB
T 1795 645 5 10 1 1 0 0 1
pinnumber=3
T 2000 600 5 10 0 0 0 0 1
pinseq=3
}
P 2000 900 1700 900 1 0 0
{
T 2000 900 5 10 0 0 0 0 1
pintype=pwr
T 1645 895 5 10 1 1 0 6 1
pinlabel=VOUT
T 1795 945 5 10 1 1 0 0 1
pinnumber=1
T 2000 900 5 10 0 0 0 0 1
pinseq=1
}
B 300 300 1400 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 295 1795 8 10 0 0 0 0 1
device=FPF2005
T 300 1600 8 10 0 0 0 0 1
description=load switch
T 300 1200 8 10 1 1 0 0 1
refdes=IC?
T 300 1400 8 10 0 0 0 0 1
footprint=SC70-5
T 1000 1200 9 10 1 0 0 0 1
FPF2005

View File

@@ -0,0 +1,100 @@
v 20110115 2
P 0 1300 300 1300 1 0 0
{
T 0 1300 5 10 0 0 0 0 1
pintype=pwr
T 355 1295 5 10 1 1 0 0 1
pinlabel=IN
T 205 1345 5 10 1 1 0 6 1
pinnumber=2
T 0 1300 5 10 0 0 0 0 1
pinseq=2
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=in
T 355 695 5 10 1 1 0 0 1
pinlabel=\_ONA\_
T 205 745 5 10 1 1 0 6 1
pinnumber=3
T 0 700 5 10 0 0 0 0 1
pinseq=3
}
P 0 400 300 400 1 0 0
{
T 0 400 5 10 0 0 0 0 1
pintype=in
T 355 395 5 10 1 1 0 0 1
pinlabel=\_ONB\_
T 205 445 5 10 1 1 0 6 1
pinnumber=4
T 0 400 5 10 0 0 0 0 1
pinseq=4
}
P 2200 1300 1900 1300 1 0 0
{
T 2200 1300 5 10 0 0 0 0 1
pintype=out
T 1845 1295 5 10 1 1 0 6 1
pinlabel=\_FLAGA\_
T 1995 1345 5 10 1 1 0 0 1
pinnumber=8
T 2200 1300 5 10 0 0 0 0 1
pinseq=8
}
P 2200 1000 1900 1000 1 0 0
{
T 2200 1000 5 10 0 0 0 0 1
pintype=out
T 1845 995 5 10 1 1 0 6 1
pinlabel=\_FLAGB\_
T 1995 1045 5 10 1 1 0 0 1
pinnumber=5
T 2200 1000 5 10 0 0 0 0 1
pinseq=5
}
P 2200 700 1900 700 1 0 0
{
T 2200 700 5 10 0 0 0 0 1
pintype=pwr
T 1845 695 5 10 1 1 0 6 1
pinlabel=OUTA
T 1995 745 5 10 1 1 0 0 1
pinnumber=7
T 2200 700 5 10 0 0 0 0 1
pinseq=7
}
P 1200 0 1200 300 1 0 0
{
T 1200 0 5 10 0 0 0 0 1
pintype=pwr
T 1200 355 5 10 1 1 90 0 1
pinlabel=GND
T 1150 205 5 10 1 1 90 6 1
pinnumber=1
T 1200 0 5 10 0 0 0 0 1
pinseq=1
}
P 2200 400 1900 400 1 0 0
{
T 2200 400 5 10 0 0 0 0 1
pintype=pwr
T 1845 395 5 10 1 1 0 6 1
pinlabel=OUTB
T 1995 445 5 10 1 1 0 0 1
pinnumber=6
T 2200 400 5 10 0 0 0 0 1
pinseq=6
}
B 300 300 1600 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1600 8 10 1 1 0 0 1
refdes=IC?
T 1100 1600 8 10 1 1 0 0 1
device=FPF230X
T 300 1800 8 10 0 0 0 0 1
description=Dual-Output Current Limit Switch
T 300 2000 8 10 0 0 0 0 1
footprint=SO8
T 300 2200 8 10 0 0 0 0 1
alt-footprint=MLP8

View File

@@ -0,0 +1,74 @@
v 20110115 2
P 0 1100 300 1100 1 0 0
{
T 0 1100 5 10 0 0 0 0 1
pintype=pwr
T 355 1095 5 10 1 1 0 0 1
pinlabel=GND
T 205 1145 5 10 1 1 0 6 1
pinnumber=1
T 0 1100 5 10 0 0 0 0 1
pinseq=1
}
P 0 900 300 900 1 0 0
{
T 0 900 5 10 0 0 0 0 1
pintype=out
T 355 895 5 10 1 1 0 0 1
pinlabel=CTS
T 205 945 5 10 1 1 0 6 1
pinnumber=2
T 0 900 5 10 0 0 0 0 1
pinseq=2
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=pwr
T 355 695 5 10 1 1 0 0 1
pinlabel=VCC
T 205 745 5 10 1 1 0 6 1
pinnumber=3
T 0 700 5 10 0 0 0 0 1
pinseq=3
}
P 0 500 300 500 1 0 0
{
T 0 500 5 10 0 0 0 0 1
pintype=out
T 355 495 5 10 1 1 0 0 1
pinlabel=TXD
T 205 545 5 10 1 1 0 6 1
pinnumber=4
T 0 500 5 10 0 0 0 0 1
pinseq=4
}
P 0 300 300 300 1 0 0
{
T 0 300 5 10 0 0 0 0 1
pintype=in
T 355 295 5 10 1 1 0 0 1
pinlabel=RXD
T 205 345 5 10 1 1 0 6 1
pinnumber=5
T 0 300 5 10 0 0 0 0 1
pinseq=5
}
P 0 100 300 100 1 0 0
{
T 0 100 5 10 0 0 0 0 1
pintype=in
T 355 95 5 10 1 1 0 0 1
pinlabel=RTS
T 205 145 5 10 1 1 0 6 1
pinnumber=6
T 0 100 5 10 0 0 0 0 1
pinseq=6
}
B 300 0 500 1300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1400 8 10 1 1 0 0 1
refdes=J?
T 300 1800 8 10 0 0 0 0 1
device=FTDI
T 300 1600 8 10 0 0 0 0 1
description=FTDI UART interface

View File

@@ -0,0 +1,34 @@
v 20110115 2
L 3700 900 3700 0 15 0 0 0 -1 -1
B 0 0 7600 1400 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 0 900 7600 900 15 0 0 0 -1 -1
T 1000 700 9 10 1 1 0 0 1
date=$Date$
T 5100 700 9 10 1 1 0 0 1
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T 5100 400 9 10 1 1 0 0 1
authors=$Authors$
T 3500 1200 9 14 1 1 0 4 1
title=TITLE
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AUTHORS:
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LICENCE:
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REVISION:
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TITLE:
T 100 400 15 8 1 0 0 0 1
VERSION:
T 900 1900 8 10 0 0 0 0 1
graphical=1
T 3900 700 15 8 1 0 0 0 1
ORGANISATION:
T 100 700 15 8 1 0 0 0 1
DATE:
T 1000 400 9 10 1 1 0 0 1
v=$Version$
T 1000 100 9 10 1 1 0 0 1
rev=$Revision$
T 5100 100 9 10 1 1 0 0 1
licence=$Licence$

View File

@@ -0,0 +1,43 @@
v 20110115 2
L 1600 0 1600 700 3 0 0 0 -1 -1
L 1600 700 1500 700 3 0 0 0 -1 -1
L 1500 0 1500 700 3 0 0 0 -1 -1
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L 1200 100 1100 0 3 0 0 0 -1 -1
L 1100 0 500 0 3 0 0 0 -1 -1
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L 1500 700 500 700 3 0 0 0 -1 -1
P 0 0 500 0 1 0 0
{
T 200 45 5 10 1 1 0 6 1
pinnumber=3
T 900 100 5 10 0 0 180 0 1
pinseq=3
T 300 0 5 10 1 1 0 0 1
pinlabel=RING
}
P 0 400 500 400 1 0 0
{
T 200 445 5 10 1 1 0 6 1
pinnumber=2
T 900 500 5 10 0 0 180 0 1
pinseq=2
T 300 400 5 10 1 1 0 0 1
pinlabel=TIP
}
P 0 700 500 700 1 0 0
{
T 200 745 5 10 1 1 0 6 1
pinnumber=1
T 900 800 5 10 0 0 180 0 1
pinseq=1
T 300 700 5 10 1 1 0 0 1
pinlabel=SLEEVE
}
T 1300 800 8 10 1 1 0 0 1
refdes=P?
T 0 1200 8 10 0 0 0 0 1
description=stereo jack

View File

@@ -0,0 +1,100 @@
v 20110115 2
P 0 1000 300 1000 1 0 0
{
T 0 1000 5 10 0 0 0 0 1
pintype=pwr
T 355 995 5 10 1 1 0 0 1
pinlabel=VIN
T 205 1045 5 10 1 1 0 6 1
pinnumber=1
T 0 1000 5 10 0 0 0 0 1
pinseq=1
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=in
T 355 695 5 10 1 1 0 0 1
pinlabel=\_SD1\_
T 205 745 5 10 1 1 0 6 1
pinnumber=2
T 0 700 5 10 0 0 0 0 1
pinseq=2
}
P 0 400 300 400 1 0 0
{
T 0 400 5 10 0 0 0 0 1
pintype=in
T 355 395 5 10 1 1 0 0 1
pinlabel=\_SD2\_
T 205 445 5 10 1 1 0 6 1
pinnumber=3
T 0 400 5 10 0 0 0 0 1
pinseq=3
}
P 0 100 300 100 1 0 0
{
T 0 100 5 10 0 0 0 0 1
pintype=pwr
T 355 95 5 10 1 1 0 0 1
pinlabel=GND
T 205 145 5 10 1 1 0 6 1
pinnumber=4
T 0 100 5 10 0 0 0 0 1
pinseq=4
}
P 2100 1000 1800 1000 1 0 0
{
T 2100 1000 5 10 0 0 0 0 1
pintype=pwr
T 1745 995 5 10 1 1 0 6 1
pinlabel=VOUT1
T 1895 1045 5 10 1 1 0 0 1
pinnumber=8
T 2100 1000 5 10 0 0 0 0 1
pinseq=8
}
P 2100 700 1800 700 1 0 0
{
T 2100 700 5 10 0 0 0 0 1
pintype=pwr
T 1745 695 5 10 1 1 0 6 1
pinlabel=VOUT2
T 1895 745 5 10 1 1 0 0 1
pinnumber=7
T 2100 700 5 10 0 0 0 0 1
pinseq=7
}
P 2100 400 1800 400 1 0 0
{
T 2100 400 5 10 0 0 0 0 1
pintype=out
T 1745 395 5 10 1 1 0 6 1
pinlabel=\_ERROR1\_
T 1895 445 5 10 1 1 0 0 1
pinnumber=6
T 2100 400 5 10 0 0 0 0 1
pinseq=6
}
P 2100 100 1800 100 1 0 0
{
T 2100 100 5 10 0 0 0 0 1
pintype=out
T 1745 95 5 10 1 1 0 6 1
pinlabel=\_ERROR2\_
T 1895 145 5 10 1 1 0 0 1
pinnumber=5
T 2100 100 5 10 0 0 0 0 1
pinseq=5
}
B 300 0 1500 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1300 8 10 1 1 0 0 1
refdes=IC?
T 1200 1300 8 10 1 1 0 0 1
device=LP2966
T 300 1500 8 10 0 0 0 0 1
description=Dual 150mA Ultra Low-Dropout Regulator
T 300 1700 8 10 0 0 0 0 1
footprint=MSOP8
T 300 1900 8 10 0 0 0 0 1
manufacturer=National Semiconductor

View File

@@ -0,0 +1,122 @@
v 20110115 2
P 0 1900 300 1900 1 0 0
{
T 0 1900 5 10 0 0 0 0 1
pintype=io
T 355 1895 5 10 1 1 0 0 1
pinlabel=DAT2
T 205 1945 5 10 1 1 0 6 1
pinnumber=1
T 0 1900 5 10 0 0 0 0 1
pinseq=1
}
P 0 1700 300 1700 1 0 0
{
T 0 1700 5 10 0 0 0 0 1
pintype=io
T 355 1695 5 10 1 1 0 0 1
pinlabel=CD/DAT3
T 205 1745 5 10 1 1 0 6 1
pinnumber=2
T 0 1700 5 10 0 0 0 0 1
pinseq=2
}
P 0 1500 300 1500 1 0 0
{
T 0 1500 5 10 0 0 0 0 1
pintype=in
T 355 1495 5 10 1 1 0 0 1
pinlabel=CMD
T 205 1545 5 10 1 1 0 6 1
pinnumber=3
T 0 1500 5 10 0 0 0 0 1
pinseq=3
}
P 0 1300 300 1300 1 0 0
{
T 0 1300 5 10 0 0 0 0 1
pintype=pwr
T 355 1295 5 10 1 1 0 0 1
pinlabel=VDD
T 205 1345 5 10 1 1 0 6 1
pinnumber=4
T 0 1300 5 10 0 0 0 0 1
pinseq=4
}
P 0 1100 300 1100 1 0 0
{
T 0 1100 5 10 0 0 0 0 1
pintype=in
T 355 1095 5 10 1 1 0 0 1
pinlabel=CLK
T 205 1145 5 10 1 1 0 6 1
pinnumber=5
T 0 1100 5 10 0 0 0 0 1
pinseq=5
}
P 0 900 300 900 1 0 0
{
T 0 900 5 10 0 0 0 0 1
pintype=pwr
T 355 895 5 10 1 1 0 0 1
pinlabel=VSS
T 205 945 5 10 1 1 0 6 1
pinnumber=6
T 0 900 5 10 0 0 0 0 1
pinseq=6
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=io
T 355 695 5 10 1 1 0 0 1
pinlabel=DAT0
T 205 745 5 10 1 1 0 6 1
pinnumber=7
T 0 700 5 10 0 0 0 0 1
pinseq=7
}
P 0 500 300 500 1 0 0
{
T 0 500 5 10 0 0 0 0 1
pintype=io
T 355 495 5 10 1 1 0 0 1
pinlabel=DAT1
T 205 545 5 10 1 1 0 6 1
pinnumber=8
T 0 500 5 10 0 0 0 0 1
pinseq=8
}
P 0 300 300 300 1 0 0
{
T 0 300 5 10 0 0 0 0 1
pintype=pas
T 355 295 5 10 1 1 0 0 1
pinlabel=SW_A
T 205 345 5 10 1 1 0 6 1
pinnumber=9
T 0 300 5 10 0 0 0 0 1
pinseq=9
}
P 0 100 300 100 1 0 0
{
T 0 100 5 10 0 0 0 0 1
pintype=pas
T 355 95 5 10 1 1 0 0 1
pinlabel=SW_B
T 205 145 5 10 1 1 0 6 1
pinnumber=10
T 0 100 5 10 0 0 0 0 1
pinseq=10
}
V 950 100 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 300 300 900 300 3 0 0 0 -1 -1
L 900 300 1050 150 3 0 0 0 -1 -1
L 300 100 900 100 3 0 0 0 -1 -1
B 300 0 900 2100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 2200 8 10 1 1 0 0 1
refdes=J?
T 300 2600 8 10 0 0 0 0 1
device=microSD
T 300 2400 8 10 0 0 0 0 1
description=microSD slot with normally open presence switch

View File

@@ -0,0 +1,49 @@
v 20110115 2
P 600 1000 600 800 1 0 0
{
T 500 850 5 6 1 1 0 0 1
pinnumber=3
T 500 850 5 6 0 0 0 0 1
pinseq=3
T 600 850 5 6 1 1 0 0 1
pinlabel=C
T 500 850 5 6 0 1 0 0 1
pintype=pas
}
P 600 200 600 0 1 0 1
{
T 500 50 5 6 1 1 0 0 1
pinnumber=2
T 500 50 5 6 0 0 0 0 1
pinseq=2
T 600 50 5 6 1 1 0 0 1
pinlabel=E
T 500 50 5 6 0 1 0 0 1
pintype=pas
}
V 500 501 316 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 900 500 5 10 0 0 0 0 1
device=NPN_TRANSISTOR
L 600 200 400 400 3 0 0 0 -1 -1
L 600 800 400 600 3 0 0 0 -1 -1
L 400 700 400 300 3 0 0 0 -1 -1
P 0 500 184 500 1 0 0
{
T 0 550 5 6 1 1 0 0 1
pinnumber=1
T 100 550 5 6 0 0 0 0 1
pinseq=1
T 100 550 5 6 1 1 0 0 1
pinlabel=B
T 100 550 5 6 0 1 0 0 1
pintype=pas
}
L 400 500 184 500 3 0 0 0 -1 -1
T 900 500 8 10 1 1 0 0 1
refdes=Q?
H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5
M 510,240
L 601,200
L 555,295
L 535,265
z

View File

@@ -0,0 +1,122 @@
v 20110115 2
P 0 1000 300 1000 1 0 0
{
T 0 1000 5 10 0 0 0 0 1
pintype=io
T 355 995 5 10 1 1 0 0 1
pinlabel=A1
T 205 1045 5 10 1 1 0 6 1
pinnumber=3
T 0 1000 5 10 0 0 0 0 1
pinseq=3
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=io
T 355 695 5 10 1 1 0 0 1
pinlabel=A2
T 205 745 5 10 1 1 0 6 1
pinnumber=4
T 0 700 5 10 0 0 0 0 1
pinseq=4
}
P 0 400 300 400 1 0 0
{
T 0 400 5 10 0 0 0 0 1
pintype=io
T 355 395 5 10 1 1 0 0 1
pinlabel=A3
T 205 445 5 10 1 1 0 6 1
pinnumber=5
T 0 400 5 10 0 0 0 0 1
pinseq=5
}
P 800 1800 800 1500 1 0 0
{
T 800 1800 5 10 0 0 0 0 1
pintype=pwr
T 800 1445 5 10 1 1 90 6 1
pinlabel=VREFA
T 750 1595 5 10 1 1 90 0 1
pinnumber=2
T 800 1800 5 10 0 0 0 0 1
pinseq=2
}
P 1200 1800 1200 1500 1 0 0
{
T 1200 1800 5 10 0 0 0 0 1
pintype=pwr
T 1200 1445 5 10 1 1 90 6 1
pinlabel=VREFB
T 1150 1595 5 10 1 1 90 0 1
pinnumber=9
T 1200 1800 5 10 0 0 0 0 1
pinseq=9
}
P 1000 0 1000 300 1 0 0
{
T 1000 0 5 10 0 0 0 0 1
pintype=pwr
T 1000 355 5 10 1 1 90 0 1
pinlabel=GND
T 950 205 5 10 1 1 90 6 1
pinnumber=1
T 1000 0 5 10 0 0 0 0 1
pinseq=1
}
P 1900 1300 1600 1300 1 0 0
{
T 1900 1300 5 10 0 0 0 0 1
pintype=in
T 1545 1295 5 10 1 1 0 6 1
pinlabel=EN
T 1695 1345 5 10 1 1 0 0 1
pinnumber=10
T 1900 1300 5 10 0 0 0 0 1
pinseq=10
}
P 1900 1000 1600 1000 1 0 0
{
T 1900 1000 5 10 0 0 0 0 1
pintype=io
T 1545 995 5 10 1 1 0 6 1
pinlabel=B1
T 1695 1045 5 10 1 1 0 0 1
pinnumber=8
T 1900 1000 5 10 0 0 0 0 1
pinseq=8
}
P 1900 700 1600 700 1 0 0
{
T 1900 700 5 10 0 0 0 0 1
pintype=io
T 1545 695 5 10 1 1 0 6 1
pinlabel=B2
T 1695 745 5 10 1 1 0 0 1
pinnumber=7
T 1900 700 5 10 0 0 0 0 1
pinseq=7
}
P 1900 400 1600 400 1 0 0
{
T 1900 400 5 10 0 0 0 0 1
pintype=io
T 1545 395 5 10 1 1 0 6 1
pinlabel=B3
T 1695 445 5 10 1 1 0 0 1
pinnumber=6
T 1900 400 5 10 0 0 0 0 1
pinseq=6
}
B 300 300 1300 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1900 8 10 1 1 0 0 1
refdes=U?
T 300 2100 8 10 0 0 0 0 1
device=NVT2003
T 300 2300 8 10 0 0 0 0 1
description=Bidirectional voltage-level translator
T 300 2500 8 10 0 0 0 0 1
manufacturer=NXP
T 300 2700 8 10 0 0 0 0 1
footprint=TSSOP10

View File

@@ -0,0 +1,74 @@
v 20110115 2
P 0 1100 300 1100 1 0 0
{
T 0 1100 5 10 0 0 0 0 1
pintype=pwr
T 355 1095 5 10 1 1 0 0 1
pinlabel=VCC
T 205 1145 5 10 1 1 0 6 1
pinnumber=1
T 0 1100 5 10 0 0 0 0 1
pinseq=1
}
P 0 900 300 900 1 0 0
{
T 0 900 5 10 0 0 0 0 1
pintype=in
T 355 895 5 10 1 1 0 0 1
pinlabel=RST
T 205 945 5 10 1 1 0 6 1
pinnumber=2
T 0 900 5 10 0 0 0 0 1
pinseq=2
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=in
T 355 695 5 10 1 1 0 0 1
pinlabel=CLK
T 205 745 5 10 1 1 0 6 1
pinnumber=3
T 0 700 5 10 0 0 0 0 1
pinseq=3
}
P 0 500 300 500 1 0 0
{
T 0 500 5 10 0 0 0 0 1
pintype=io
T 355 495 5 10 1 1 0 0 1
pinlabel=I/O
T 205 545 5 10 1 1 0 6 1
pinnumber=4
T 0 500 5 10 0 0 0 0 1
pinseq=4
}
P 0 300 300 300 1 0 0
{
T 0 300 5 10 0 0 0 0 1
pintype=pas
T 355 295 5 10 1 1 0 0 1
pinlabel=VPP
T 205 345 5 10 1 1 0 6 1
pinnumber=5
T 0 300 5 10 0 0 0 0 1
pinseq=5
}
P 0 100 300 100 1 0 0
{
T 0 100 5 10 0 0 0 0 1
pintype=pwr
T 355 95 5 10 1 1 0 0 1
pinlabel=GND
T 205 145 5 10 1 1 0 6 1
pinnumber=6
T 0 100 5 10 0 0 0 0 1
pinseq=6
}
B 300 0 500 1300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1400 8 10 1 1 0 0 1
refdes=J?
T 300 1800 8 10 0 0 0 0 1
device=REBELSIM
T 300 1600 8 10 0 0 0 0 1
description=RebelSim FFC connector

View File

@@ -0,0 +1,129 @@
v 20110115 2
P 0 1700 300 1700 1 0 0
{
T 0 1700 5 10 0 0 0 0 1
pintype=pwr
T 355 1695 5 10 1 1 0 0 1
pinlabel=VCC
T 205 1745 5 10 1 1 0 6 1
pinnumber=C1
T 0 1700 5 10 0 0 0 0 1
pinseq=1
}
P 0 1400 300 1400 1 0 0
{
T 0 1400 5 10 0 0 0 0 1
pintype=io
T 355 1395 5 10 1 1 0 0 1
pinlabel=RST
T 205 1445 5 10 1 1 0 6 1
pinnumber=C2
T 0 1400 5 10 0 0 0 0 1
pinseq=2
}
P 0 1100 300 1100 1 0 0
{
T 0 1100 5 10 0 0 0 0 1
pintype=io
T 355 1095 5 10 1 1 0 0 1
pinlabel=CLK
T 205 1145 5 10 1 1 0 6 1
pinnumber=C3
T 0 1100 5 10 0 0 0 0 1
pinseq=3
}
P 0 800 300 800 1 0 0
{
T 0 800 5 10 0 0 0 0 1
pintype=pas
T 355 795 5 10 1 1 0 0 1
pinlabel=RFU
T 205 845 5 10 1 1 0 6 1
pinnumber=C4
T 0 800 5 10 0 0 0 0 1
pinseq=4
}
P 1600 1700 1300 1700 1 0 0
{
T 1600 1700 5 10 0 0 0 0 1
pintype=pwr
T 1245 1695 5 10 1 1 0 6 1
pinlabel=GND
T 1395 1745 5 10 1 1 0 0 1
pinnumber=C5
T 1600 1700 5 10 0 0 0 0 1
pinseq=5
}
P 1600 1400 1300 1400 1 0 0
{
T 1600 1400 5 10 0 0 0 0 1
pintype=pas
T 1245 1395 5 10 1 1 0 6 1
pinlabel=VPP
T 1395 1445 5 10 1 1 0 0 1
pinnumber=C6
T 1600 1400 5 10 0 0 0 0 1
pinseq=6
}
P 1600 1100 1300 1100 1 0 0
{
T 1600 1100 5 10 0 0 0 0 1
pintype=io
T 1245 1095 5 10 1 1 0 6 1
pinlabel=I/O
T 1395 1145 5 10 1 1 0 0 1
pinnumber=C7
T 1600 1100 5 10 0 0 0 0 1
pinseq=7
}
P 1600 800 1300 800 1 0 0
{
T 1600 800 5 10 0 0 0 0 1
pintype=pas
T 1245 795 5 10 1 1 0 6 1
pinlabel=RFU
T 1395 845 5 10 1 1 0 0 1
pinnumber=C8
T 1600 800 5 10 0 0 0 0 1
pinseq=8
}
P 0 300 300 300 1 0 0
{
T 0 300 5 10 0 0 0 0 1
pintype=pas
T 255 -5 5 10 1 1 0 0 1
pinlabel=SW1
T 205 345 5 10 1 1 0 6 1
pinnumber=9
T 0 300 5 10 0 0 0 0 1
pinseq=9
}
P 1700 300 1400 300 1 0 0
{
T 1700 300 5 10 0 0 0 0 1
pintype=pas
T 1445 -5 5 10 1 1 0 6 1
pinlabel=SW2
T 1495 345 5 10 1 1 0 0 1
pinnumber=10
T 1700 300 5 10 0 0 0 0 1
pinseq=10
}
V 1300 300 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 300 300 1300 500 3 0 0 0 -1 -1
B 300 1600 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 300 1300 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 300 1000 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 300 700 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 800 1600 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 800 1300 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 800 1000 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 800 700 500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 2000 8 10 1 1 0 0 1
refdes=J?
T 300 2400 8 10 0 0 0 0 1
device=SC
T 300 2200 8 10 0 0 0 0 1
description=smart card interface with normally open presence switch
T 1000 2000 9 10 1 0 0 0 1
SC

View File

@@ -0,0 +1,79 @@
v 20110115 2
P 0 200 300 200 1 0 0
{
T 0 200 5 10 0 0 0 0 1
pintype=in
T 105 -5 5 10 1 1 0 0 1
pinlabel=A
T 205 245 5 10 1 1 0 6 1
pinnumber=2
T 0 200 5 10 0 0 0 0 1
pinseq=2
}
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=in
T 5 495 5 10 1 1 0 0 1
pinlabel=\_OE\_
T 205 745 5 10 1 1 0 6 1
pinnumber=1
T 0 700 5 10 0 0 0 0 1
pinseq=1
}
P 1200 200 900 200 1 0 0
{
T 1200 200 5 10 0 0 0 0 1
pintype=out
T 1005 -5 5 10 1 1 0 0 1
pinlabel=Y
T 995 245 5 10 1 1 0 0 1
pinnumber=3
T 1200 200 5 10 0 0 0 0 1
pinseq=3
}
L 400 500 400 900 3 0 0 0 -1 -1
L 400 500 700 700 3 0 0 0 -1 -1
L 400 900 700 700 3 0 0 0 -1 -1
L 300 400 300 0 3 0 0 0 -1 -1
L 600 200 300 0 3 0 0 0 -1 -1
L 300 400 600 200 3 0 0 0 -1 -1
V 350 700 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 650 200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 700 200 900 200 3 0 0 0 -1 -1
L 450 300 450 400 3 0 0 0 -1 -1
L 450 400 800 400 3 0 0 0 -1 -1
L 800 400 800 700 3 0 0 0 -1 -1
L 800 700 700 700 3 0 0 0 -1 -1
T 0 950 8 10 1 1 0 0 1
refdes=U?
T 700 900 8 10 1 0 0 0 1
slot=1
T 0 1200 8 10 0 0 0 0 1
device=SN74LVC240A
T 0 1400 8 10 0 0 0 0 1
description=2x4 inverter
T 0 1600 8 10 0 0 0 0 1
numslots=8
T 0 1800 8 10 0 0 0 0 1
documentation=http://www.ti.com/lit/ds/symlink/sn74lvc240a.pdf
T 0 2000 8 10 0 0 0 0 1
net=Vcc:20
T 0 2200 8 10 0 0 0 0 1
net=GND:10
T 0 2400 8 10 0 0 0 0 1
slotdef=1:1,2,18
T 0 2600 8 10 0 0 0 0 1
slotdef=2:1,4,16
T 0 2800 8 10 0 0 0 0 1
slotdef=3:1,6,14
T 0 3000 8 10 0 0 0 0 1
slotdef=4:1,8,12
T 0 3200 8 10 0 0 0 0 1
slotdef=5:19,11,9
T 0 3400 8 10 0 0 0 0 1
slotdef=6:19,13,7
T 0 3600 8 10 0 0 0 0 1
slotdef=7:19,15,5
T 0 3800 8 10 0 0 0 0 1
slotdef=8:19,17,3

View File

@@ -0,0 +1,65 @@
v 20110115 2
P 0 700 300 700 1 0 0
{
T 0 700 5 10 0 0 0 0 1
pintype=pwr
T 355 695 5 10 1 1 0 0 1
pinlabel=Vin
T 205 745 5 10 1 1 0 6 1
pinnumber=1
T 0 700 5 10 0 0 0 0 1
pinseq=1
}
P 0 400 300 400 1 0 0
{
T 0 400 5 10 0 0 0 0 1
pintype=pwr
T 355 395 5 10 1 1 0 0 1
pinlabel=GND
T 205 445 5 10 1 1 0 6 1
pinnumber=2
T 0 400 5 10 0 0 0 0 1
pinseq=2
}
P 0 100 300 100 1 0 0
{
T 0 100 5 10 0 0 0 0 1
pintype=in
T 355 95 5 10 1 1 0 0 1
pinlabel=\_SHDN\_
T 205 145 5 10 1 1 0 6 1
pinnumber=3
T 0 100 5 10 0 0 0 0 1
pinseq=3
}
P 1700 700 1400 700 1 0 0
{
T 1700 700 5 10 0 0 0 0 1
pintype=pwr
T 1345 695 5 10 1 1 0 6 1
pinlabel=Vout
T 1495 745 5 10 1 1 0 0 1
pinnumber=5
T 1700 700 5 10 0 0 0 0 1
pinseq=5
}
P 1700 100 1400 100 1 0 0
{
T 1700 100 5 10 0 0 0 0 1
pintype=passive
T 1345 95 5 10 1 1 0 6 1
pinlabel=ADJ
T 1495 145 5 10 1 1 0 0 1
pinnumber=4
T 1700 100 5 10 0 0 0 0 1
pinseq=4
}
B 300 0 1100 900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1000 8 10 1 1 0 0 1
refdes=U?
T 300 1200 8 10 0 0 0 0 1
device=TC1071
T 300 1400 8 10 0 0 0 0 1
manufacturer=Microchip
T 300 1600 8 10 0 0 0 0 1
documentation=http://ww1.microchip.com/downloads/en/DeviceDoc/21353E.pdf

View File

@@ -0,0 +1,107 @@
v 20070818 1
P 1900 1700 2200 1700 1 0 1
{
T 1550 1650 5 8 1 1 0 0 1
pinnumber=2
T 750 1650 5 8 0 0 0 0 1
pinseq=2
T 750 1650 5 8 0 1 0 0 1
pinlabel=2
T 750 1650 5 8 0 1 0 0 1
pintype=pas
}
P 1900 1100 2200 1100 1 0 1
{
T 1550 1050 5 8 1 1 0 0 1
pinnumber=4
T 750 1050 5 8 0 0 0 0 1
pinseq=4
T 750 1050 5 8 0 1 0 0 1
pinlabel=4
T 750 1050 5 8 0 1 0 0 1
pintype=pas
}
P 1900 2000 2200 2000 1 0 1
{
T 1550 1950 5 8 1 1 0 0 1
pinnumber=1
T 750 1950 5 8 0 0 0 0 1
pinseq=1
T 750 1950 5 8 0 1 0 0 1
pinlabel=1
T 750 1950 5 8 0 1 0 0 1
pintype=pas
}
P 1900 1400 2200 1400 1 0 1
{
T 1550 1350 5 8 1 1 0 0 1
pinnumber=3
T 750 1350 5 8 0 0 0 0 1
pinseq=3
T 750 1350 5 8 0 1 0 0 1
pinlabel=3
T 750 1350 5 8 0 1 0 0 1
pintype=pas
}
P 900 300 900 0 1 0 1
{
T 900 850 5 8 1 1 180 6 1
pinnumber=G
T 850 1450 5 8 0 0 270 0 1
pinseq=6
T 900 350 5 8 0 1 90 0 1
pinlabel=G
T 850 1450 5 8 0 1 270 0 1
pintype=pas
}
L 1900 2000 1700 2000 3 0 0 0 -1 -1
L 1900 1700 1700 1700 3 0 0 0 -1 -1
L 1900 1400 1700 1400 3 0 0 0 -1 -1
L 1900 1100 1700 1100 3 0 0 0 -1 -1
L 900 500 900 300 3 0 0 0 -1 -1
T 100 2200 5 10 0 0 0 0 1
author=andrewmATthehacktoryDOTcom
T 100 2300 8 10 1 1 0 0 1
refdes=CONN?
V 900 600 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 1000 600 1700 600 3 0 0 0 -1 -1
L 1700 2200 0 2200 3 0 0 0 -1 -1
L 1700 2200 1700 600 3 0 0 0 -1 -1
L 800 600 0 600 3 0 0 0 -1 -1
L 0 2200 0 600 3 0 0 0 -1 -1
L 100 2200 100 600 3 0 0 0 -1 -1
T 100 2400 5 10 0 0 0 0 1
dist-license=GPL
T 100 2600 5 10 0 0 0 0 1
use-license=unlimited
T 1450 2000 9 10 1 0 0 7 1
5V
T 1450 1700 9 10 1 0 0 7 1
D-
T 1450 1400 9 10 1 0 0 7 1
D+
T 1450 1100 9 10 1 0 0 7 1
ID
P 1900 800 2200 800 1 0 1
{
T 1550 750 5 8 1 1 0 0 1
pinnumber=5
T 750 750 5 8 0 0 0 0 1
pinseq=5
T 750 750 5 8 0 1 0 0 1
pinlabel=5
T 750 750 5 8 0 1 0 0 1
pintype=pas
}
L 1900 800 1700 800 3 0 0 0 -1 -1
T 1450 800 9 10 1 0 0 7 1
GND
L 200 1900 200 900 3 0 0 0 -1 -1
L 200 900 400 900 3 0 0 0 -1 -1
L 400 900 600 700 3 0 0 0 -1 -1
L 600 700 800 700 3 0 0 0 -1 -1
L 800 700 800 2100 3 0 0 0 -1 -1
L 800 2100 600 2100 3 0 0 0 -1 -1
L 600 2100 400 1900 3 0 0 0 -1 -1
L 400 1900 200 1900 3 0 0 0 -1 -1
L 500 2100 400 2100 3 0 0 0 -1 -1

2371
hardware/geda/simtrace.sch Normal file

File diff suppressed because it is too large Load Diff

1
hardware/geda/version Normal file
View File

@@ -0,0 +1 @@
1.5

File diff suppressed because it is too large Load Diff

View File

@@ -1,4 +1,4 @@
Cmp-Mod V01 Created by CvPCB (2011-06-08)-testing date = Sa 02 Jul 2011 19:41:58 CEST
Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Thu 03 Nov 2011 11:55:14 CET
BeginCmp
TimeStamp = /4DC804A6;
@@ -270,7 +270,7 @@ BeginCmp
TimeStamp = /4CFCD6C9;
Reference = P1;
ValeurCmp = JTAG;
IdModule = pin_array_10x2;
IdModule = PIN_ARRAY_10X2;
EndCmp
BeginCmp

File diff suppressed because it is too large Load Diff

View File

@@ -74,17 +74,16 @@ LibName33=lib/smartcard
[pcbnew]
version=1
PadDrlX=0
PadDimH=157
PadDimV=197
PadDimH=472
PadDimV=2165
BoardThickness=630
SgPcb45=1
TxtPcbV=800
TxtPcbH=600
TxtPcbV=299
TxtPcbH=299
TxtModV=600
TxtModH=600
TxtModW=120
VEgarde=100
DrawLar=150
DrawLar=60
EdgeLar=80
TxtLar=120
MSegLar=100

File diff suppressed because it is too large Load Diff

View File

@@ -1,21 +1,24 @@
PCBNEW-LibModule-V1 Mo 20 Jun 2011 21:34:10 CEST
PCBNEW-LibModule-V1 Thu 03 Nov 2011 11:53:58 CET
# encoding utf-8
$INDEX
CAP_AVE_E
FFC_REBELSIM
JACK2.5_SJ-2523-SMT
JACK2.5_SJ1-2503A
PUSH_BUTTON
SC_ID0
SC_ID000
SOD123
SOT223-6
USB_MINI-B
JACK_2.5
pin_array_10x2
FFC_REBELSIM
PUSH_BUTTON
SOIC8
SOT223-6
SOT23_BC847
USB-MINI-B_UX60
SSOP20_BDQ
SOT26
SOT353
SSOP20_BDQ
USB-MINI-B_54819-0519
USB-MINI-B_UX60
USB_MINI-B
pin_array_10x2
$EndINDEX
$MODULE CAP_AVE_E
Po 0 0 0 15 4CFCEE9A 00000000 ~~
@@ -370,167 +373,6 @@ Ne 0 ""
Po 1181 0
$EndPAD
$EndMODULE JACK_2.5
$MODULE pin_array_10x2
Po 0 0 0 15 4DCBEF17 00000000 ~~
Li pin_array_10x2
Cd Double rangee de contacts 2 x 12 pins
Kw CONN
Sc 00000000
AR
Op 0 0 0
T0 0 -1500 400 400 0 100 N V 21 N"PIN_ARRAY_10X2"
T1 0 1500 400 400 0 80 N V 21 N"Val**"
DS 4000 1000 -6000 1000 150 21
DS 4000 -1000 -6000 -1000 150 21
DS -6000 -1000 -6000 1000 150 21
DS 4002 1000 4002 -1000 150 21
$PAD
Sh "1" R 600 600 0 0 0
Dr 320 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -5500 500
$EndPAD
$PAD
Sh "2" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -5500 -500
$EndPAD
$PAD
Sh "3" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -4500 500
$EndPAD
$PAD
Sh "4" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -4500 -500
$EndPAD
$PAD
Sh "5" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -3500 500
$EndPAD
$PAD
Sh "6" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -3500 -500
$EndPAD
$PAD
Sh "7" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -2500 500
$EndPAD
$PAD
Sh "8" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -2500 -500
$EndPAD
$PAD
Sh "9" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -1500 500
$EndPAD
$PAD
Sh "10" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -1500 -500
$EndPAD
$PAD
Sh "11" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -500 500
$EndPAD
$PAD
Sh "12" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -500 -500
$EndPAD
$PAD
Sh "13" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 500 500
$EndPAD
$PAD
Sh "14" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 500 -500
$EndPAD
$PAD
Sh "15" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 1500 500
$EndPAD
$PAD
Sh "16" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 1500 -500
$EndPAD
$PAD
Sh "17" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2500 500
$EndPAD
$PAD
Sh "18" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2500 -500
$EndPAD
$PAD
Sh "19" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 3500 500
$EndPAD
$PAD
Sh "20" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 3500 -500
$EndPAD
$SHAPE3D
Na "pin_array/pins_array_12x2.wrl"
Sc 1.000000 1.000000 1.000000
Of 0.000000 0.000000 0.000000
Ro 0.000000 0.000000 0.000000
$EndSHAPE3D
$EndMODULE pin_array_10x2
$MODULE FFC_REBELSIM
Po 0 0 0 15 4DCBF7BC 00000000 ~~
Li FFC_REBELSIM
@@ -1152,7 +994,7 @@ $MODULE SOT353
Po 0 0 0 15 4DFFA09C 00000000 ~~
Li SOT353
Sc 00000000
AR
AR
Op 0 0 0
T0 0 846 299 299 0 59 N V 21 N"SOT353"
T1 0 -768 299 299 0 59 N V 21 N"VAL**"
@@ -1196,4 +1038,165 @@ Ne 0 ""
Po 256 -374
$EndPAD
$EndMODULE SOT353
$MODULE PIN_ARRAY_10X2
Po 0 0 0 15 4DCBEF17 00000000 ~~
Li PIN_ARRAY_10X2
Cd Double rangee de contacts 2 x 12 pins
Kw CONN
Sc 00000000
AR
Op 0 0 0
T0 0 -1500 400 400 0 100 N V 21 N "PIN_ARRAY_10X2"
T1 0 1500 400 400 0 80 N V 21 N "Val**"
DS 4000 1000 -6000 1000 150 21
DS 4000 -1000 -6000 -1000 150 21
DS -6000 -1000 -6000 1000 150 21
DS 4002 1000 4002 -1000 150 21
$PAD
Sh "1" R 600 600 0 0 0
Dr 320 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -5500 500
$EndPAD
$PAD
Sh "2" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -5500 -500
$EndPAD
$PAD
Sh "3" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -4500 500
$EndPAD
$PAD
Sh "4" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -4500 -500
$EndPAD
$PAD
Sh "5" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -3500 500
$EndPAD
$PAD
Sh "6" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -3500 -500
$EndPAD
$PAD
Sh "7" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -2500 500
$EndPAD
$PAD
Sh "8" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -2500 -500
$EndPAD
$PAD
Sh "9" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -1500 500
$EndPAD
$PAD
Sh "10" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -1500 -500
$EndPAD
$PAD
Sh "11" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -500 500
$EndPAD
$PAD
Sh "12" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -500 -500
$EndPAD
$PAD
Sh "13" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 500 500
$EndPAD
$PAD
Sh "14" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 500 -500
$EndPAD
$PAD
Sh "15" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 1500 500
$EndPAD
$PAD
Sh "16" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 1500 -500
$EndPAD
$PAD
Sh "17" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2500 500
$EndPAD
$PAD
Sh "18" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2500 -500
$EndPAD
$PAD
Sh "19" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 3500 500
$EndPAD
$PAD
Sh "20" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 3500 -500
$EndPAD
$SHAPE3D
Na "pin_array/pins_array_12x2.wrl"
Sc 1.000000 1.000000 1.000000
Of 0.000000 0.000000 0.000000
Ro 0.000000 0.000000 0.000000
$EndSHAPE3D
$EndMODULE PIN_ARRAY_10X2
$EndLIBRARY

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View File

@@ -1,119 +1,13 @@
PCBNEW-LibModule-V1 Di 21 Jun 2011 22:35:07 CEST
PCBNEW-LibModule-V1 Sa 13 Aug 2011 15:51:03 CEST
# encoding utf-8
$INDEX
smartcard-CARDSOCKET
SIM_AMPHENOL
SIM
FFC
SAM_FCI
SIM
SIM_AMPHENOL
SIM_LIGHT
microSIM_card
$EndINDEX
$MODULE smartcard-CARDSOCKET
Po 0 0 0 15 00200000 00000000 ~~
Li smartcard-CARDSOCKET
Cd ISO 7816 CARD SOCKET
Kw ISO 7816 CARD SOCKET
Sc 00000000
Op 0 0 0
At VIRTUAL
DS -11000 -1000 -11000 -1500 50 21
DS -11000 -1500 -11000 -14500 50 21
DS -11000 -14500 6000 -14500 50 21
DS 6000 -14500 6000 10500 50 21
DS 6000 10500 -11000 10500 50 21
DS -11000 10500 -11000 -1500 50 21
DC 1500 -13500 1750 -13750 50 21
DS 1000 -13500 2000 -13500 50 21
DS 1500 -13000 1500 -14000 50 21
DC -6500 -13500 -6750 -13750 50 21
DS -7000 -13500 -6000 -13500 50 21
DS -6500 -13000 -6500 -14000 50 21
DC 1500 9500 1750 9750 50 21
DS 1000 9500 2000 9500 50 21
DS 1500 10000 1500 9000 50 21
DC -6500 9500 -6750 9750 50 21
DS -7000 9500 -6000 9500 50 21
DS -6500 10000 -6500 9000 50 21
T0 -3250 -5250 500 500 900 35 N V "Card Socket"
T1 -10000 -4250 500 500 0 35 N V "S1"
T2 -8500 -4250 500 500 0 35 N V "S2"
T3 -8500 1250 500 500 0 35 N V "C1"
T4 -8500 250 500 500 0 35 N V "C2"
T5 -8500 -750 500 500 0 35 N V "C3"
T6 -8500 -1750 500 500 0 35 N V "C4"
T7 4000 1250 500 500 0 35 N V "C5"
T8 4000 250 500 500 0 35 N V "C6"
T9 4000 -750 500 500 0 35 N V "C7"
T10 4000 -1750 500 500 0 35 N V "C8"
$PAD
Sh "CLK" R 760 0 0 0 0
Dr 320 0 0
At STD N 00A88001
Ne 0 ""
Po -10000 -1000
$EndPAD
$PAD
Sh "GND" R 760 0 0 0 0
Dr 320 0 0
At STD N 00A88001
Ne 0 ""
Po 5000 1000
$EndPAD
$PAD
Sh "I/O" R 760 0 0 0 0
Dr 320 0 0
At STD N 00A88001
Ne 0 ""
Po 5000 -1000
$EndPAD
$PAD
Sh "PIN4" R 760 0 0 0 0
Dr 320 0 0
At STD N 00A88001
Ne 0 ""
Po -10000 -2000
$EndPAD
$PAD
Sh "PIN6" R 760 0 0 0 0
Dr 320 0 0
At STD N 00A88001
Ne 0 ""
Po 5000 0
$EndPAD
$PAD
Sh "PIN8" R 760 0 0 0 0
Dr 320 0 0
At STD N 00A88001
Ne 0 ""
Po 5000 -2000
$EndPAD
$PAD
Sh "RST" R 760 0 0 0 0
Dr 320 0 0
At STD N 00A88001
Ne 0 ""
Po -10000 0
$EndPAD
$PAD
Sh "SW1" R 760 0 0 0 0
Dr 320 0 0
At STD N 00A88001
Ne 0 ""
Po -10000 -3500
$EndPAD
$PAD
Sh "SW2" R 760 0 0 0 0
Dr 320 0 0
At STD N 00A88001
Ne 0 ""
Po -9000 -3500
$EndPAD
$PAD
Sh "VCC" R 760 0 0 0 0
Dr 320 0 0
At STD N 00A88001
Ne 0 ""
Po -10000 1000
$EndPAD
$EndMODULE CARDSOCKET
$MODULE SIM_AMPHENOL
Po 0 0 0 15 4DFF4BD6 00000000 ~~
Li SIM_AMPHENOL
@@ -281,82 +175,151 @@ Ne 0 ""
Po 8996 -3878
$EndPAD
$EndMODULE SIM_AMPHENOL
$MODULE FFC
Po 0 0 0 15 4E00FFB1 00000000 ~~
Li FFC
$MODULE SAM_FCI
Po 0 0 0 15 4E0DAC7D 00000000 ~~
Li SAM_FCI
Sc 00000000
AR /4E0084DD
AR SAM_FCI
Op 0 0 0
T0 0 1850 600 600 0 120 N I 21 N "P2"
T1 0 -1752 600 600 0 120 N I 21 N "FFC"
T0 0 1102 600 600 0 120 N V 21 N "SAM_FCI"
T1 0 -984 600 600 0 120 N V 21 N "VAL**"
DS -12205 -7874 12205 -7874 100 21
DS 12205 -7874 12205 7874 100 21
DS 12205 7874 -12205 7874 100 21
DS -12205 7874 -12205 -7874 100 21
$PAD
Sh "1" R 1181 315 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 5 "/VCC"
Po 0 -984
.LocalClearance 79
Sh "" C 866 866 0 0 0
Dr 866 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -11417 0
$EndPAD
$PAD
Sh "2" R 1181 315 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 4 "/RST"
Po 0 -591
.LocalClearance 79
Sh "" C 866 866 0 0 0
Dr 866 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 11417 0
$EndPAD
$PAD
Sh "3" R 1181 315 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 1 "/CLK"
Po 0 -197
.LocalClearance 79
Sh "" C 1299 1299 0 0 0
Dr 1299 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -11417 -3937
$EndPAD
$PAD
Sh "4" R 1181 315 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 3 "/I/O"
Po 0 197
.LocalClearance 79
Sh "" C 1299 1299 0 0 0
Dr 1299 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -11417 3937
$EndPAD
$PAD
Sh "5" R 1181 315 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 6 "/VPP"
Po 0 591
.LocalClearance 79
Sh "" C 1299 1299 0 0 0
Dr 1299 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 11417 -3937
$EndPAD
$PAD
Sh "6" R 1181 315 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 2 "/GND"
Po 0 984
.LocalClearance 79
Sh "" C 1299 1299 0 0 0
Dr 1299 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 11417 3937
$EndPAD
$EndMODULE FFC
$PAD
Sh "C5" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po 2709 -7500
$EndPAD
$PAD
Sh "C6" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po 1709 -7500
$EndPAD
$PAD
Sh "C7" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po 709 -7500
$EndPAD
$PAD
Sh "C8" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po -291 -7500
$EndPAD
$PAD
Sh "C1" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po 2709 7500
$EndPAD
$PAD
Sh "C2" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po 1709 7500
$EndPAD
$PAD
Sh "C3" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po 709 7500
$EndPAD
$PAD
Sh "C4" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po -291 7500
$EndPAD
$PAD
Sh "SW1" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po -1791 7500
$EndPAD
$PAD
Sh "SW2" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po -1791 6500
$EndPAD
$EndMODULE SAM_FCI
$MODULE SIM
Po 0 0 0 15 4E010072 00000000 ~~
Po 0 0 0 15 4E0EDB0B 00000000 ~~
Li SIM
Sc 00000000
AR /4E0085A5
Op 0 0 0
T0 8583 2953 600 600 0 120 N I 21 N "SIM1"
T1 6890 2913 600 600 900 120 N I 21 N "SIM_CARD"
DS 9843 0 9843 4724 150 21
DS 9843 4724 8661 5906 150 21
DS 0 5906 0 0 150 21
DS 8661 5906 0 5906 150 21
DS 0 0 9843 0 150 21
DS 9843 0 9843 4724 59 28
DS 9843 4724 8661 5906 59 28
DS 0 5906 0 0 59 28
DS 8661 5906 0 5906 59 28
DS 0 0 9843 0 59 28
$PAD
Sh "C1" R 1969 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 2165 1417
Le 33130128
$EndPAD
$PAD
Sh "C2" R 1575 787 0 0 0
@@ -364,6 +327,7 @@ Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1969 2417
Le 4096
$EndPAD
$PAD
Sh "C3" R 1575 787 0 0 0
@@ -371,6 +335,7 @@ Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1969 3417
Le 1213220172
$EndPAD
$PAD
Sh "C4" R 1575 787 0 0 0
@@ -378,6 +343,7 @@ Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1969 4417
Le 114
$EndPAD
$PAD
Sh "C5" R 1969 787 0 0 0
@@ -385,6 +351,7 @@ Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 4764 1417
Le 33077792
$EndPAD
$PAD
Sh "C6" R 1575 787 0 0 0
@@ -392,6 +359,7 @@ Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 4969 2417
Le 97
$EndPAD
$PAD
Sh "C7" R 1575 787 0 0 0
@@ -399,6 +367,7 @@ Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 4969 3417
Le 48
$EndPAD
$PAD
Sh "C8" R 1575 787 0 0 0
@@ -406,6 +375,198 @@ Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 4969 4417
Le 129
$EndPAD
$EndMODULE SIM
$MODULE FFC
Po 0 0 0 15 4E0EE015 00000000 ~~
Li FFC
Sc 00000000
AR /4E0084D4
Op 0 0 0
.SolderMask 20
.SolderPaste -20
.LocalClearance 59
T0 1250 1800 600 600 0 120 N I 21 N "LEFT"
T1 -600 1800 600 600 0 120 N I 21 N "FFC"
$PAD
Sh "1" R 1181 315 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 1 "N-000011"
Po 0 -984
$EndPAD
$PAD
Sh "2" R 1181 315 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 2 "N-000023"
Po 0 -591
Le 28352768
$EndPAD
$PAD
Sh "3" R 1181 315 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 3 "N-000024"
Po 0 -197
Le 109
$EndPAD
$PAD
Sh "4" R 1181 315 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 4 "N-000025"
Po 0 197
Le 613999128
$EndPAD
$PAD
Sh "5" R 1181 315 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 6 "N-000028"
Po 0 591
Le 31022232
$EndPAD
$PAD
Sh "6" R 1181 315 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 5 "N-000026"
Po 0 984
Le 31692672
$EndPAD
$EndMODULE FFC
$MODULE SIM_LIGHT
Po 0 0 0 15 4E162214 00000000 ~~
Li SIM_LIGHT
Sc 00000000
AR /4E158AC1
Op 0 0 0
T0 1065 -643 600 600 0 120 N I 21 N "SIM1"
T1 6615 -593 600 600 0 120 N I 21 N "ISO7816_CARD"
DS 9843 0 9843 4724 59 21
DS 9843 4724 8661 5906 59 21
DS 0 5906 0 0 59 21
DS 8661 5906 0 5906 59 21
DS 0 0 9843 0 59 21
$PAD
Sh "C1" R 1575 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 5 "/VCC1"
Po 1969 1417
Le 33130128
$EndPAD
$PAD
Sh "C2" R 1575 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 4 "/RST1"
Po 1969 2417
Le 4096
$EndPAD
$PAD
Sh "C3" R 1575 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 1 "/CLK1"
Po 1969 3417
Le 1213220172
$EndPAD
$PAD
Sh "C5" R 1575 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 2 "/GND1"
Po 4969 1417
Le 33077792
$EndPAD
$PAD
Sh "C6" R 1575 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 6 "/VPP1"
Po 4969 2417
Le 97
$EndPAD
$PAD
Sh "C7" R 1575 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 3 "/I-O1"
Po 4969 3417
Le 48
$EndPAD
$EndMODULE SIM_LIGHT
$MODULE microSIM_card
Po 0 0 0 15 4E468144 00000000 ~~
Li microSIM_card
Sc 00000000
AR
Op 0 0 0
T0 0 3150 600 600 0 120 N V 21 N "microSIM_card"
T1 0 -3051 600 600 0 120 N V 21 N "VAL**"
DS -2953 -2362 2953 -2362 100 28
DS 2953 -2362 2953 1378 100 28
DS 2953 1378 1969 2362 100 28
DS 1969 2362 -2953 2362 100 28
DS -2953 2362 -2953 -2362 100 28
$PAD
Sh "C1" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -1713 -1500
$EndPAD
$PAD
Sh "C2" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -1713 -500
$EndPAD
$PAD
Sh "C3" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -1713 500
$EndPAD
$PAD
Sh "C4" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -1713 1500
$EndPAD
$PAD
Sh "C5" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1287 -1500
$EndPAD
$PAD
Sh "C6" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1287 -500
$EndPAD
$PAD
Sh "C7" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1287 500
$EndPAD
$PAD
Sh "C8" R 787 669 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1287 1500
$EndPAD
$EndMODULE microSIM_card
$EndLIBRARY

View File

@@ -0,0 +1,59 @@
Cmp-Mod V01 Created by CvPCB (2011-07-19)-testing date = Sa 13 Aug 2011 15:54:00 CEST
BeginCmp
TimeStamp = /4E158ACC;
Reference = FFC1;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E159114;
Reference = FFC2;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E15911B;
Reference = FFC3;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E159134;
Reference = FFC4;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E158AC1;
Reference = SIM1;
ValeurCmp = ISO7816_CARD;
IdModule = microSIM_card;
EndCmp
BeginCmp
TimeStamp = /4E159115;
Reference = SIM2;
ValeurCmp = ISO7816_CARD;
IdModule = microSIM_card;
EndCmp
BeginCmp
TimeStamp = /4E15911A;
Reference = SIM3;
ValeurCmp = ISO7816_CARD;
IdModule = microSIM_card;
EndCmp
BeginCmp
TimeStamp = /4E159135;
Reference = SIM4;
ValeurCmp = ISO7816_CARD;
IdModule = microSIM_card;
EndCmp
EndListe

View File

@@ -0,0 +1,76 @@
# EESchema Netlist Version 1.1 created Sa 13 Aug 2011 15:54:00 CEST
(
( /4E158ACC FFC FFC1 FFC
( 1 /VCC1 )
( 2 /RST1 )
( 3 /CLK1 )
( 4 /I-O1 )
( 5 /VPP1 )
( 6 /GND1 )
)
( /4E159114 FFC FFC2 FFC
( 1 /VCC2 )
( 2 /RST2 )
( 3 /CLK2 )
( 4 /I-O2 )
( 5 /VPP2 )
( 6 /GND2 )
)
( /4E15911B FFC FFC3 FFC
( 1 /VCC3 )
( 2 /RST3 )
( 3 /CLK3 )
( 4 /I-O3 )
( 5 /VPP3 )
( 6 /GND3 )
)
( /4E159134 FFC FFC4 FFC
( 1 /VCC4 )
( 2 /RST4 )
( 3 /CLK4 )
( 4 /I-O4 )
( 5 /VPP4 )
( 6 /GND4 )
)
( /4E158AC1 microSIM_card SIM1 ISO7816_CARD
( C1 /VCC1 )
( C2 /RST1 )
( C3 /CLK1 )
( C4 ? )
( C5 /GND1 )
( C6 /VPP1 )
( C7 /I-O1 )
( C8 ? )
)
( /4E159115 microSIM_card SIM2 ISO7816_CARD
( C1 /VCC2 )
( C2 /RST2 )
( C3 /CLK2 )
( C4 ? )
( C5 /GND2 )
( C6 /VPP2 )
( C7 /I-O2 )
( C8 ? )
)
( /4E15911A microSIM_card SIM3 ISO7816_CARD
( C1 /VCC3 )
( C2 /RST3 )
( C3 /CLK3 )
( C4 ? )
( C5 /GND3 )
( C6 /VPP3 )
( C7 /I-O3 )
( C8 ? )
)
( /4E159135 microSIM_card SIM4 ISO7816_CARD
( C1 /VCC4 )
( C2 /RST4 )
( C3 /CLK4 )
( C4 ? )
( C5 /GND4 )
( C6 /VPP4 )
( C7 /I-O4 )
( C8 ? )
)
)
*

View File

@@ -0,0 +1,86 @@
update=Sa 13 Aug 2011 15:53:03 CEST
last_client=cvpcb
[eeschema]
version=1
LibDir=
NetFmt=1
HPGLSpd=20
HPGLDm=15
HPGLNum=1
offX_A4=0
offY_A4=0
offX_A3=0
offY_A3=0
offX_A2=0
offY_A2=0
offX_A1=0
offY_A1=0
offX_A0=0
offY_A0=0
offX_A=0
offY_A=0
offX_B=0
offY_B=0
offX_C=0
offY_C=0
offX_D=0
offY_D=0
offX_E=0
offY_E=0
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=lib/SIMtrace
LibName32=lib/smartcard
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew]
[pcbnew/libraries]
LibName1=sockets
LibName2=connect
LibName3=discret
LibName4=pin_array
LibName5=divers
LibName6=libcms
LibName7=display
LibName8=valves
LibName9=led
LibName10=dip_sockets
LibName11=lib/SIMtrace
LibName12=lib/smartcard
LibDir=

View File

@@ -0,0 +1,367 @@
EESchema Schematic File Version 2 date Do 07 Jul 2011 13:03:38 CEST
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:smartcard
EELAYER 25 0
EELAYER END
$Descr A4 11700 8267
encoding utf-8
Sheet 1 1
Title "noname.sch"
Date "7 jul 2011"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Label 4450 1850 0 60 ~ 0
I-O2
Text Label 4450 1950 0 60 ~ 0
VPP2
Text Label 4450 2050 0 60 ~ 0
GND2
Text Label 3450 1850 0 60 ~ 0
CLK2
Text Label 3450 1950 0 60 ~ 0
RST2
Text Label 3450 2050 0 60 ~ 0
VCC2
Text Label 2550 1850 0 60 ~ 0
I-O1
Text Label 2550 1950 0 60 ~ 0
VPP1
Text Label 2550 2050 0 60 ~ 0
GND1
$Comp
L ISO7816_CARD SIM4
U 1 1 4E159135
P 7850 1250
F 0 "SIM4" H 7850 1500 60 0000 C CNN
F 1 "ISO7816_CARD" H 7850 1000 60 0000 C CNN
1 7850 1250
1 0 0 -1
$EndComp
$Comp
L FFC FFC4
U 1 1 4E159134
P 7850 2450
F 0 "FFC4" H 7900 2800 60 0000 C CNN
F 1 "FFC" V 8050 2450 60 0000 C CNN
1 7850 2450
0 -1 1 0
$EndComp
Text Label 7250 1850 0 60 ~ 0
CLK4
Text Label 7250 1950 0 60 ~ 0
RST4
Text Label 7250 2050 0 60 ~ 0
VCC4
Wire Wire Line
8650 1200 8650 1950
Wire Wire Line
7900 1850 8600 1850
Wire Wire Line
7900 1850 7900 2100
Wire Wire Line
7700 2100 7700 1950
Wire Wire Line
7700 1950 7050 1950
Wire Wire Line
7100 1300 7100 1850
Wire Wire Line
8400 1300 8600 1300
Wire Wire Line
8100 2100 8100 2050
Wire Wire Line
8100 2050 8700 2050
Wire Wire Line
8700 2050 8700 1100
Wire Wire Line
8700 1100 8400 1100
Wire Wire Line
7300 1200 7050 1200
Wire Wire Line
7300 1100 7000 1100
Wire Wire Line
7000 1100 7000 2050
Wire Wire Line
7000 2050 7600 2050
Wire Wire Line
7600 2050 7600 2100
Wire Wire Line
7100 1300 7300 1300
Wire Wire Line
8650 1200 8400 1200
Wire Wire Line
7100 1850 7800 1850
Wire Wire Line
7800 1850 7800 2100
Wire Wire Line
7050 1200 7050 1950
Wire Wire Line
8600 1300 8600 1850
Wire Wire Line
8000 2100 8000 1950
Wire Wire Line
8000 1950 8650 1950
Text Label 8250 1850 0 60 ~ 0
I-O4
Text Label 8250 1950 0 60 ~ 0
VPP4
Text Label 8250 2050 0 60 ~ 0
GND4
NoConn ~ 8400 1400
NoConn ~ 7300 1400
NoConn ~ 5400 1400
NoConn ~ 6500 1400
Text Label 6350 2050 0 60 ~ 0
GND3
Text Label 6350 1950 0 60 ~ 0
VPP3
Text Label 6350 1850 0 60 ~ 0
I-O3
Wire Wire Line
6100 1950 6750 1950
Wire Wire Line
6100 1950 6100 2100
Wire Wire Line
6700 1300 6700 1850
Wire Wire Line
5150 1200 5150 1950
Wire Wire Line
5900 2100 5900 1850
Wire Wire Line
5900 1850 5200 1850
Wire Wire Line
6500 1200 6750 1200
Wire Wire Line
5400 1300 5200 1300
Wire Wire Line
5700 2100 5700 2050
Wire Wire Line
5700 2050 5100 2050
Wire Wire Line
5100 2050 5100 1100
Wire Wire Line
5100 1100 5400 1100
Wire Wire Line
5150 1200 5400 1200
Wire Wire Line
6500 1100 6800 1100
Wire Wire Line
6800 1100 6800 2050
Wire Wire Line
6800 2050 6200 2050
Wire Wire Line
6200 2050 6200 2100
Wire Wire Line
6700 1300 6500 1300
Wire Wire Line
5200 1300 5200 1850
Wire Wire Line
5150 1950 5800 1950
Wire Wire Line
5800 1950 5800 2100
Wire Wire Line
6000 2100 6000 1850
Wire Wire Line
6000 1850 6700 1850
Wire Wire Line
6750 1200 6750 1950
Text Label 5350 2050 0 60 ~ 0
VCC3
Text Label 5350 1950 0 60 ~ 0
RST3
Text Label 5350 1850 0 60 ~ 0
CLK3
$Comp
L FFC FFC3
U 1 1 4E15911B
P 5950 2450
F 0 "FFC3" H 6000 2800 60 0000 C CNN
F 1 "FFC" V 6150 2450 60 0000 C CNN
1 5950 2450
0 -1 1 0
$EndComp
$Comp
L ISO7816_CARD SIM3
U 1 1 4E15911A
P 5950 1250
F 0 "SIM3" H 5950 1500 60 0000 C CNN
F 1 "ISO7816_CARD" H 5950 1000 60 0000 C CNN
1 5950 1250
1 0 0 -1
$EndComp
$Comp
L ISO7816_CARD SIM2
U 1 1 4E159115
P 4050 1250
F 0 "SIM2" H 4050 1500 60 0000 C CNN
F 1 "ISO7816_CARD" H 4050 1000 60 0000 C CNN
1 4050 1250
1 0 0 -1
$EndComp
$Comp
L FFC FFC2
U 1 1 4E159114
P 4050 2450
F 0 "FFC2" H 4100 2800 60 0000 C CNN
F 1 "FFC" V 4250 2450 60 0000 C CNN
1 4050 2450
0 -1 1 0
$EndComp
Wire Wire Line
4850 1200 4850 1950
Wire Wire Line
4100 1850 4800 1850
Wire Wire Line
4100 1850 4100 2100
Wire Wire Line
3900 2100 3900 1950
Wire Wire Line
3900 1950 3250 1950
Wire Wire Line
3300 1300 3300 1850
Wire Wire Line
4600 1300 4800 1300
Wire Wire Line
4300 2100 4300 2050
Wire Wire Line
4300 2050 4900 2050
Wire Wire Line
4900 2050 4900 1100
Wire Wire Line
4900 1100 4600 1100
Wire Wire Line
3500 1200 3250 1200
Wire Wire Line
3500 1100 3200 1100
Wire Wire Line
3200 1100 3200 2050
Wire Wire Line
3200 2050 3800 2050
Wire Wire Line
3800 2050 3800 2100
Wire Wire Line
3300 1300 3500 1300
Wire Wire Line
4850 1200 4600 1200
Wire Wire Line
3300 1850 4000 1850
Wire Wire Line
4000 1850 4000 2100
Wire Wire Line
3250 1200 3250 1950
Wire Wire Line
4800 1300 4800 1850
Wire Wire Line
4200 2100 4200 1950
Wire Wire Line
4200 1950 4850 1950
NoConn ~ 4600 1400
NoConn ~ 3500 1400
NoConn ~ 1600 1400
NoConn ~ 2700 1400
Wire Wire Line
2300 1950 2950 1950
Wire Wire Line
2300 1950 2300 2100
Wire Wire Line
2900 1300 2900 1850
Wire Wire Line
1350 1200 1350 1950
Wire Wire Line
2100 2100 2100 1850
Wire Wire Line
2100 1850 1400 1850
Wire Wire Line
2700 1200 2950 1200
Wire Wire Line
1600 1300 1400 1300
Wire Wire Line
1900 2100 1900 2050
Wire Wire Line
1900 2050 1300 2050
Wire Wire Line
1300 2050 1300 1100
Wire Wire Line
1300 1100 1600 1100
Wire Wire Line
1350 1200 1600 1200
Wire Wire Line
2700 1100 3000 1100
Wire Wire Line
3000 1100 3000 2050
Wire Wire Line
3000 2050 2400 2050
Wire Wire Line
2400 2050 2400 2100
Wire Wire Line
2900 1300 2700 1300
Wire Wire Line
1400 1300 1400 1850
Wire Wire Line
1350 1950 2000 1950
Wire Wire Line
2000 1950 2000 2100
Wire Wire Line
2200 2100 2200 1850
Wire Wire Line
2200 1850 2900 1850
Wire Wire Line
2950 1200 2950 1950
Text Label 1550 2050 0 60 ~ 0
VCC1
Text Label 1550 1950 0 60 ~ 0
RST1
Text Label 1550 1850 0 60 ~ 0
CLK1
$Comp
L FFC FFC1
U 1 1 4E158ACC
P 2150 2450
F 0 "FFC1" H 2200 2800 60 0000 C CNN
F 1 "FFC" V 2350 2450 60 0000 C CNN
1 2150 2450
0 -1 1 0
$EndComp
$Comp
L ISO7816_CARD SIM1
U 1 1 4E158AC1
P 2150 1250
F 0 "SIM1" H 2150 1500 60 0000 C CNN
F 1 "ISO7816_CARD" H 2150 1000 60 0000 C CNN
1 2150 1250
1 0 0 -1
$EndComp
$EndSCHEMATC

View File

@@ -0,0 +1,461 @@
PCBNEW-BOARD Version 1 date Sat 25 Feb 2012 03:47:15 PM CET
# Created by Pcbnew(2011-07-02 BZR 3034)-testing
$GENERAL
encoding utf-8
LayerCount 2
Ly 1FFF8001
EnabledLayers 1FFF8001
Links 6
NoConn 0
Di 23724 20224 48876 37216
Ndraw 8
Ntrack 44
Nzone 0
BoardThickness 630
Nmodule 2
Nnets 7
$EndGENERAL
$SHEETDESCR
Sheet A4 11700 8267
Title ""
Date "25 feb 2012"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndSHEETDESCR
$SETUP
InternalUnit 0.000100 INCH
Layers 2
Layer[0] Back signal
Layer[15] Front signal
TrackWidth 236
TrackClearence 100
ZoneClearence 200
TrackMinWidth 80
DrawSegmWidth 150
EdgeSegmWidth 150
ViaSize 350
ViaDrill 236
ViaMinSize 350
ViaMinDrill 200
MicroViaSize 200
MicroViaDrill 50
MicroViasAllowed 0
MicroViaMinSize 200
MicroViaMinDrill 50
TextPcbWidth 120
TextPcbSize 600 800
EdgeModWidth 150
TextModSize 600 600
TextModWidth 120
PadSize 600 600
PadDrill 320
Pad2MaskClearance 100
AuxiliaryAxisOrg 23800 36600
PcbPlotParams (pcbplotparams (layerselection 15761409) (usegerberextensions true) (excludeedgelayer false) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk true) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory /sunbeam/home/laforge/projects/git/simtrace/hardware/pcb/gerber/))
$EndSETUP
$EQUIPOT
Na 0 ""
St ~
$EndEQUIPOT
$EQUIPOT
Na 1 "N-000001"
St ~
$EndEQUIPOT
$EQUIPOT
Na 2 "N-000002"
St ~
$EndEQUIPOT
$EQUIPOT
Na 3 "N-000003"
St ~
$EndEQUIPOT
$EQUIPOT
Na 4 "N-000005"
St ~
$EndEQUIPOT
$EQUIPOT
Na 5 "N-000007"
St ~
$EndEQUIPOT
$EQUIPOT
Na 6 "N-000008"
St ~
$EndEQUIPOT
$NCLASS
Name "Default"
Desc "This is the default net class."
Clearance 100
TrackWidth 236
ViaDia 350
ViaDrill 236
uViaDia 200
uViaDrill 50
AddNet ""
AddNet "N-000001"
AddNet "N-000002"
AddNet "N-000003"
AddNet "N-000005"
AddNet "N-000007"
AddNet "N-000008"
$EndNCLASS
$MODULE SAM_FCI
Po 36300 28400 0 15 4E0DAC7D 4F3FC169 ~~
Li SAM_FCI
Sc 4F3FC169
AR /4F3FBFC0
Op 0 0 0
T0 0 1102 600 600 0 120 N V 21 N "P2"
T1 0 -984 600 600 0 120 N V 21 N "ISO7816_NO"
DS -12205 -7874 12205 -7874 100 21
DS 12205 -7874 12205 7874 100 21
DS 12205 7874 -12205 7874 100 21
DS -12205 7874 -12205 -7874 100 21
$PAD
Sh "" C 866 866 0 0 0
Dr 866 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -11417 0
Le 95
$EndPAD
$PAD
Sh "" C 866 866 0 0 0
Dr 866 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 11417 0
Le 111
$EndPAD
$PAD
Sh "" C 1299 1299 0 0 0
Dr 1299 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -11417 -3937
Le 400128
$EndPAD
$PAD
Sh "" C 1299 1299 0 0 0
Dr 1299 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -11417 3937
Le 373504
$EndPAD
$PAD
Sh "" C 1299 1299 0 0 0
Dr 1299 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 11417 -3937
Le 373760
$EndPAD
$PAD
Sh "" C 1299 1299 0 0 0
Dr 1299 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 11417 3937
Le 397568
$EndPAD
$PAD
Sh "C5" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 4 "N-000005"
Po 2709 -7500
Le 400128
$EndPAD
$PAD
Sh "C6" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 1 "N-000001"
Po 1709 -7500
Le 373760
$EndPAD
$PAD
Sh "C7" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 6 "N-000008"
Po 709 -7500
Le 379136
$EndPAD
$PAD
Sh "C8" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po -291 -7500
Le 373030
$EndPAD
$PAD
Sh "C1" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 2 "N-000002"
Po 2709 7500
Le 372787
$EndPAD
$PAD
Sh "C2" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 3 "N-000003"
Po 1709 7500
Le 32
$EndPAD
$PAD
Sh "C3" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 5 "N-000007"
Po 709 7500
Le 20
$EndPAD
$PAD
Sh "C4" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po -291 7500
Le 23
$EndPAD
$PAD
Sh "SW1" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po -1791 7500
Le 20
$EndPAD
$PAD
Sh "SW2" C 600 600 0 0 0
Dr 394 0 0
At STD N 00E00001
Ne 0 ""
Po -1791 6500
Le 23
$EndPAD
$EndMODULE SAM_FCI
$MODULE FFC_REBELSIM
Po 30900 34000 1800 0 4DCBF7BC 4F3FC16A ~~
Li FFC_REBELSIM
Sc 4F3FC16A
AR /4F3FBFB5
Op 0 0 0
T0 0 -2756 600 600 1800 120 M V 20 N "P1"
T1 0 1614 600 600 1800 120 M V 20 N "REBELSIM"
DS -2087 -1693 -2087 0 150 20
DS -2087 0 2087 0 150 20
DS 2087 0 2087 -1693 150 20
DS -2717 -2165 -2717 -1693 150 20
DS 2717 -2165 2717 -1693 150 20
DS -2717 -2165 2717 -2165 150 20
DS 2717 -1693 -2717 -1693 150 20
$PAD
Sh "1" R 236 787 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 2 "N-000002"
Po -984 197
Le 1
$EndPAD
$PAD
Sh "2" R 236 787 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 3 "N-000003"
Po -591 197
Le 3
$EndPAD
$PAD
Sh "3" R 236 787 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 5 "N-000007"
Po -197 197
Le 72
$EndPAD
$PAD
Sh "4" R 236 787 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 6 "N-000008"
Po 197 197
Le 6
$EndPAD
$PAD
Sh "5" R 236 787 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 1 "N-000001"
Po 591 197
Le 76
$EndPAD
$PAD
Sh "6" R 236 787 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 4 "N-000005"
Po 984 197
Le 90
$EndPAD
$PAD
Sh "" R 276 1654 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 0 ""
Po -1378 -630
Le 76
$EndPAD
$PAD
Sh "" R 276 1654 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 0 ""
Po 1378 -630
Le 80
$EndPAD
$EndMODULE FFC_REBELSIM
$TEXTPCB
Te "D45197"
Po 45800 35200 600 800 120 0
De 20 0 0 Normal
$EndTEXTPCB
$TEXTPCB
Te "D45197"
Po 45800 35200 600 800 120 0
De 21 1 0 Normal
$EndTEXTPCB
$TEXTPCB
Te "sysmocom"
nl "SAM-FPC-Adapter"
Po 30900 22100 600 800 120 0
De 15 1 0 Normal
$EndTEXTPCB
$TEXTPCB
Te "sysmocom"
nl "SAM-FPC-Adapter"
Po 30800 22100 600 800 120 0
De 0 0 0 Normal
$EndTEXTPCB
$DRAWSEGMENT
Po 0 23800 20300 23800 36600 150
De 28 0 900 0 0
$EndDRAWSEGMENT
$DRAWSEGMENT
Po 0 48800 20300 23800 20300 150
De 28 0 900 0 0
$EndDRAWSEGMENT
$DRAWSEGMENT
Po 0 48800 36600 48800 20300 150
De 28 0 900 0 0
$EndDRAWSEGMENT
$DRAWSEGMENT
Po 0 23800 36600 48800 36600 150
De 28 0 900 0 0
$EndDRAWSEGMENT
$TRACK
Po 0 30309 33803 30309 32091 236 -1
De 0 0 1 0 400000
Po 0 38000 20900 38009 20900 236 -1
De 0 0 1 0 800000
Po 0 38000 30800 38000 20900 236 -1
De 0 0 1 0 0
Po 3 38000 30800 38000 30800 350 -1
De 15 1 1 0 0
Po 0 35500 30800 38000 30800 236 -1
De 15 0 1 0 0
Po 3 35500 30800 35500 30800 350 -1
De 15 1 1 0 0
Po 0 31600 30800 35500 30800 236 -1
De 0 0 1 0 0
Po 0 30309 32091 31600 30800 236 -1
De 0 0 1 0 0
Po 0 31884 33803 31884 33116 236 -1
De 0 0 2 0 400000
Po 0 39000 35900 39009 35900 236 -1
De 0 0 2 0 800000
Po 0 39000 33700 39000 35900 236 -1
De 0 0 2 0 0
Po 0 38200 32900 39000 33700 236 -1
De 0 0 2 0 0
Po 0 32100 32900 38200 32900 236 -1
De 0 0 2 0 0
Po 0 31884 33116 32100 32900 236 -1
De 0 0 2 0 0
Po 0 31491 33803 31491 32909 236 -1
De 0 0 3 0 400000
Po 0 38000 35900 38009 35900 236 -1
De 0 0 3 0 800000
Po 0 38000 33500 38000 35900 236 -1
De 0 0 3 0 0
Po 3 38000 33500 38000 33500 350 -1
De 15 1 3 0 0
Po 0 38000 32400 38000 33500 236 -1
De 15 0 3 0 0
Po 3 38000 32400 38000 32400 350 -1
De 15 1 3 0 0
Po 0 32000 32400 38000 32400 236 -1
De 0 0 3 0 0
Po 0 31491 32909 32000 32400 236 -1
De 0 0 3 0 0
Po 0 29916 33803 29916 31784 236 -1
De 0 0 4 0 400000
Po 0 39000 20800 39009 20900 236 -1
De 0 0 4 0 800000
Po 0 39000 30200 39000 20800 236 -1
De 0 0 4 0 0
Po 3 39000 30200 39000 30200 350 -1
De 15 1 4 0 0
Po 0 36000 30200 39000 30200 236 -1
De 15 0 4 0 0
Po 3 36000 30200 36000 30200 350 -1
De 15 1 4 0 0
Po 0 31500 30200 36000 30200 236 -1
De 0 0 4 0 0
Po 0 29916 31784 31500 30200 236 -1
De 0 0 4 0 0
Po 0 31097 33803 31097 32703 236 -1
De 0 0 5 0 400000
Po 0 37000 35800 37009 35900 236 -1
De 0 0 5 0 800000
Po 0 37000 33500 37000 35800 236 -1
De 0 0 5 0 0
Po 3 37000 33500 37000 33500 350 -1
De 15 1 5 0 0
Po 0 37000 31900 37000 33500 236 -1
De 15 0 5 0 0
Po 3 37000 31900 37000 31900 350 -1
De 15 1 5 0 0
Po 0 31900 31900 37000 31900 236 -1
De 0 0 5 0 0
Po 0 31097 32703 31900 31900 236 -1
De 0 0 5 0 0
Po 0 30703 33803 30703 32397 236 -1
De 0 0 6 0 400000
Po 0 37000 20800 37009 20900 236 -1
De 0 0 6 0 800000
Po 0 37000 30100 37000 20800 236 -1
De 0 0 6 0 0
Po 0 35700 31400 37000 30100 236 -1
De 0 0 6 0 0
Po 0 31700 31400 35700 31400 236 -1
De 0 0 6 0 0
Po 0 30703 32397 31700 31400 236 -1
De 0 0 6 0 0
$EndTRACK
$ZONE
$EndZONE
$EndBOARD

View File

@@ -0,0 +1,17 @@
Cmp-Mod V01 Created by CvPCB (2011-07-02 BZR 3034)-testing date = Sat 18 Feb 2012 04:35:11 PM CET
BeginCmp
TimeStamp = /4F3FBFB5;
Reference = P1;
ValeurCmp = REBELSIM;
IdModule = FFC_REBELSIM;
EndCmp
BeginCmp
TimeStamp = /4F3FBFC0;
Reference = P2;
ValeurCmp = ISO7816_NO;
IdModule = SAM_FCI;
EndCmp
EndListe

View File

@@ -0,0 +1,22 @@
# EESchema Netlist Version 1.1 created Sat 18 Feb 2012 04:35:11 PM CET
(
( /4F3FBFB5 FFC_REBELSIM P1 REBELSIM
( 1 N-000002 )
( 2 N-000003 )
( 3 N-000007 )
( 4 N-000008 )
( 5 N-000001 )
( 6 N-000005 )
)
( /4F3FBFC0 SAM_FCI P2 ISO7816_NO
( C1 N-000002 )
( C2 N-000003 )
( C3 N-000007 )
( C4 ? )
( C5 N-000005 )
( C6 N-000001 )
( C7 N-000008 )
( C8 ? )
)
)
*

View File

@@ -0,0 +1,105 @@
update=Sat 18 Feb 2012 04:35:01 PM CET
version=1
last_client=cvpcb
[general]
version=1
[eeschema]
version=1
LibDir=/sunbeam/home/laforge/projects/git/simtrace/hardware/kicad/lib
NetFmt=1
HPGLSpd=20
HPGLDm=15
HPGLNum=1
offX_A4=0
offY_A4=0
offX_A3=0
offY_A3=0
offX_A2=0
offY_A2=0
offX_A1=0
offY_A1=0
offX_A0=0
offY_A0=0
offX_A=0
offY_A=0
offX_B=0
offY_B=0
offX_C=0
offY_C=0
offX_D=0
offY_D=0
offX_E=0
offY_E=0
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=smartcard
[pcbnew]
version=1
PadDrlX=320
PadDimH=600
PadDimV=600
BoardThickness=630
TxtPcbV=800
TxtPcbH=600
TxtModV=600
TxtModH=600
TxtModW=120
VEgarde=100
DrawLar=150
EdgeLar=150
TxtLar=120
MSegLar=150
LastNetListRead=simadapter1.net
[pcbnew/libraries]
LibName1=sockets
LibName2=connect
LibName3=discret
LibName4=pin_array
LibName5=divers
LibName6=libcms
LibName7=display
LibName8=valves
LibName9=led
LibName10=dip_sockets
LibName11=FPC_6PIN
LibName12=smartcard
LibName13=SIMtrace
LibDir=/sunbeam/home/laforge/projects/git/simtrace/hardware/kicad/lib
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms

View File

@@ -0,0 +1,113 @@
EESchema Schematic File Version 2 date Sat 18 Feb 2012 04:48:32 PM CET
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:smartcard
EELAYER 43 0
EELAYER END
$Descr A4 11700 8267
encoding utf-8
Sheet 1 1
Title ""
Date "18 feb 2012"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
5750 2450 6100 2450
Wire Wire Line
6100 2450 6100 1900
Wire Wire Line
6100 1900 5200 1900
Wire Wire Line
5200 1900 5200 1650
Wire Wire Line
5750 2250 5900 2250
Wire Wire Line
5900 2250 5900 1700
Wire Wire Line
5900 1700 5400 1700
Wire Wire Line
5400 1700 5400 1650
Wire Wire Line
4650 2350 4400 2350
Wire Wire Line
4400 2350 4400 1800
Wire Wire Line
4400 1800 5000 1800
Wire Wire Line
5000 1800 5000 1650
Wire Wire Line
4650 2250 4500 2250
Wire Wire Line
4500 2250 4500 1700
Wire Wire Line
4500 1700 4900 1700
Wire Wire Line
4900 1700 4900 1650
Wire Wire Line
5100 1650 5100 1900
Wire Wire Line
5100 1900 4300 1900
Wire Wire Line
4300 1900 4300 2450
Wire Wire Line
4300 2450 4650 2450
Wire Wire Line
5300 1650 5300 1800
Wire Wire Line
5300 1800 6000 1800
Wire Wire Line
6000 1800 6000 2350
Wire Wire Line
6000 2350 5750 2350
$Comp
L ISO7816_NO P2
U 1 1 4F3FBFC0
P 5200 2400
F 0 "P2" H 5200 2650 60 0000 C CNN
F 1 "ISO7816_NO" H 5200 2150 60 0000 C CNN
1 5200 2400
1 0 0 -1
$EndComp
$Comp
L REBELSIM P1
U 1 1 4F3FBFB5
P 5150 1300
F 0 "P1" H 5200 1650 60 0000 C CNN
F 1 "REBELSIM" V 5350 1300 60 0000 C CNN
1 5150 1300
0 -1 -1 0
$EndComp
$EndSCHEMATC

1104
hardware/kicad/simcable.brd Normal file

File diff suppressed because it is too large Load Diff

View File

@@ -1,36 +1,57 @@
Cmp-Mod V01 Created by CvPCB (2011-06-08)-testing date = Di 21 Jun 2011 22:38:14 CEST
BeginCmp
TimeStamp = /4E0084D9;
Reference = P1;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E0084DD;
Reference = P2;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
Cmp-Mod V01 Created by CvPCB (2011-06-08)-testing date = Sa 02 Jul 2011 10:33:03 CEST
BeginCmp
TimeStamp = /4E0084E2;
Reference = P3;
Reference = P_DOWN2;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E0084D4;
Reference = P4;
Reference = P_LEFT3;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E0084DD;
Reference = P_RIGHT4;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E0084D9;
Reference = P_UP1;
ValeurCmp = FFC;
IdModule = FFC;
EndCmp
BeginCmp
TimeStamp = /4E0ED4A7;
Reference = SIM_DOWN2;
ValeurCmp = ISO7816_CARD;
IdModule = SIM;
EndCmp
BeginCmp
TimeStamp = /4E0ED4DA;
Reference = SIM_LEFT3;
ValeurCmp = ISO7816_CARD;
IdModule = SIM;
EndCmp
BeginCmp
TimeStamp = /4E0ED4DB;
Reference = SIM_RIGHT4;
ValeurCmp = ISO7816_CARD;
IdModule = SIM;
EndCmp
BeginCmp
TimeStamp = /4E0085A5;
Reference = SIM1;
Reference = SIM_UP1;
ValeurCmp = ISO7816_CARD;
IdModule = SIM;
EndCmp

View File

@@ -1,45 +1,75 @@
# EESchema Netlist Version 1.1 created Di 21 Jun 2011 22:38:14 CEST
# EESchema Netlist Version 1.1 created Sa 02 Jul 2011 10:33:03 CEST
(
( /4E0084D9 FFC P1 FFC
( 1 /VCC )
( 2 /RST )
( 3 /CLK )
( 4 /I/O )
( 5 /VPP )
( 6 /GND )
( /4E0084E2 FFC P_DOWN2 FFC
( 1 N-000032 )
( 2 N-000029 )
( 3 N-000002 )
( 4 N-000003 )
( 5 N-000027 )
( 6 N-000004 )
)
( /4E0084DD FFC P2 FFC
( 1 /VCC )
( 2 /RST )
( 3 /CLK )
( 4 /I/O )
( 5 /VPP )
( 6 /GND )
( /4E0084D4 FFC P_LEFT3 FFC
( 1 N-000011 )
( 2 N-000023 )
( 3 N-000024 )
( 4 N-000025 )
( 5 N-000028 )
( 6 N-000026 )
)
( /4E0084E2 FFC P3 FFC
( 1 /VCC )
( 2 /RST )
( 3 /CLK )
( 4 /I/O )
( 5 /VPP )
( 6 /GND )
( /4E0084DD FFC P_RIGHT4 FFC
( 1 N-000012 )
( 2 N-000001 )
( 3 N-000013 )
( 4 N-000018 )
( 5 N-000009 )
( 6 N-000019 )
)
( /4E0084D4 FFC P4 FFC
( 1 /VCC )
( 2 /RST )
( 3 /CLK )
( 4 /I/O )
( 5 /VPP )
( 6 /GND )
( /4E0084D9 FFC P_UP1 FFC
( 1 N-000020 )
( 2 N-000030 )
( 3 N-000017 )
( 4 N-000021 )
( 5 N-000022 )
( 6 N-000031 )
)
( /4E0085A5 SIM SIM1 ISO7816_CARD
( C1 /VCC )
( C2 /RST )
( C3 /CLK )
( /4E0ED4A7 SIM SIM_DOWN2 ISO7816_CARD
( C1 N-000032 )
( C2 N-000029 )
( C3 N-000002 )
( C4 ? )
( C5 /GND )
( C6 /VPP )
( C7 /I/O )
( C5 N-000004 )
( C6 N-000027 )
( C7 N-000003 )
( C8 ? )
)
( /4E0ED4DA SIM SIM_LEFT3 ISO7816_CARD
( C1 N-000011 )
( C2 N-000023 )
( C3 N-000024 )
( C4 ? )
( C5 N-000026 )
( C6 N-000028 )
( C7 N-000025 )
( C8 ? )
)
( /4E0ED4DB SIM SIM_RIGHT4 ISO7816_CARD
( C1 N-000012 )
( C2 N-000001 )
( C3 N-000013 )
( C4 ? )
( C5 N-000019 )
( C6 N-000009 )
( C7 N-000018 )
( C8 ? )
)
( /4E0085A5 SIM SIM_UP1 ISO7816_CARD
( C1 N-000020 )
( C2 N-000030 )
( C3 N-000017 )
( C4 ? )
( C5 N-000031 )
( C6 N-000022 )
( C7 N-000021 )
( C8 ? )
)
)

View File

@@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Di 21 Jun 2011 14:36:44 CEST
EESchema Schematic File Version 2 date Sa 02 Jul 2011 10:31:49 CEST
LIBS:power
LIBS:device
LIBS:transistors
@@ -30,14 +30,13 @@ LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:smartcard
LIBS:SIMtrace-cache
EELAYER 25 0
EELAYER END
$Descr A4 11700 8267
encoding utf-8
Sheet 1 1
Title "SIM card for FFC"
Date "21 jun 2011"
Date "2 jul 2011"
Rev "v1.0"
Comp ""
Comment1 ""
@@ -45,171 +44,268 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
NoConn ~ 9500 2850
NoConn ~ 8400 2850
Wire Wire Line
9500 2750 10000 2750
Wire Wire Line
10000 2950 9600 2950
Wire Wire Line
9600 2950 9600 2550
Wire Wire Line
9600 2550 9500 2550
Wire Wire Line
8400 2650 8150 2650
Wire Wire Line
8150 2650 8150 2200
Wire Wire Line
8150 2200 9850 2200
Wire Wire Line
9850 2200 9850 2550
Wire Wire Line
9850 2550 10000 2550
Wire Wire Line
6350 2550 6050 2550
Wire Wire Line
6050 2550 6050 2950
Wire Wire Line
6050 2950 5800 2950
Wire Wire Line
5800 2750 6350 2750
Wire Wire Line
7450 2650 7600 2650
Wire Wire Line
7600 2650 7600 2200
Wire Wire Line
7600 2200 5900 2200
Wire Wire Line
5900 2200 5900 2550
Wire Wire Line
5900 2550 5800 2550
Wire Wire Line
3600 2700 3600 2550
Wire Wire Line
3600 2550 4600 2550
Wire Wire Line
4600 2550 4600 1800
Wire Wire Line
4600 1800 4400 1800
Wire Wire Line
3800 2700 3800 2450
Wire Wire Line
3800 2450 4500 2450
Wire Wire Line
4500 2450 4500 2000
Wire Wire Line
4500 2000 4400 2000
Wire Wire Line
3100 2400 4100 2400
Wire Wire Line
3100 2400 3100 1800
Wire Wire Line
3100 1800 3300 1800
Wire Wire Line
3900 2700 3900 2300
Wire Wire Line
3900 2300 3200 2300
Wire Wire Line
3200 2300 3200 2000
Wire Wire Line
3200 2000 3300 2000
Wire Wire Line
2000 2300 2000 2450
Wire Wire Line
2000 2450 2550 2450
Wire Wire Line
2550 2450 2550 3050
Wire Wire Line
2550 3050 2400 3050
Wire Wire Line
1800 2300 1800 2500
Wire Wire Line
1800 2500 1100 2500
Wire Wire Line
1100 2500 1100 3150
Wire Wire Line
1100 3150 1300 3150
Wire Wire Line
1600 2300 1600 2400
Wire Wire Line
1600 2400 1200 2400
Wire Wire Line
1200 2400 1200 2950
Wire Wire Line
1200 2950 1300 2950
Wire Wire Line
1300 3050 1150 3050
Wire Wire Line
1150 3050 1150 2450
Wire Wire Line
1150 2450 1700 2450
Wire Wire Line
1700 2450 1700 2300
Wire Wire Line
2400 2950 2500 2950
Wire Wire Line
2500 2950 2500 2400
Wire Wire Line
2500 2400 2100 2400
Wire Wire Line
2100 2400 2100 2300
Wire Wire Line
2400 3150 2600 3150
Wire Wire Line
2600 3150 2600 2500
Wire Wire Line
2600 2500 1900 2500
Wire Wire Line
1900 2500 1900 2300
Wire Wire Line
3300 1900 3150 1900
Wire Wire Line
3150 1900 3150 2350
Wire Wire Line
3150 2350 4000 2350
Wire Wire Line
4000 2350 4000 2700
Wire Wire Line
4100 2400 4100 2700
Wire Wire Line
4400 1900 4550 1900
Wire Wire Line
4550 1900 4550 2500
Wire Wire Line
4550 2500 3700 2500
Wire Wire Line
3700 2500 3700 2700
Wire Wire Line
5800 2450 5850 2450
Wire Wire Line
5850 2450 5850 2150
Wire Wire Line
5850 2150 7550 2150
Wire Wire Line
7550 2150 7550 2550
Wire Wire Line
7550 2550 7450 2550
Wire Wire Line
5800 2650 5950 2650
Wire Wire Line
5950 2650 5950 2250
Wire Wire Line
5950 2250 7650 2250
Wire Wire Line
7650 2250 7650 2750
Wire Wire Line
7650 2750 7450 2750
Wire Wire Line
5800 2850 6000 2850
Wire Wire Line
6000 2850 6000 2650
Wire Wire Line
6000 2650 6350 2650
Wire Wire Line
10000 2450 9900 2450
Wire Wire Line
9900 2450 9900 2150
Wire Wire Line
9900 2150 8200 2150
Wire Wire Line
8200 2150 8200 2550
Wire Wire Line
8200 2550 8400 2550
Wire Wire Line
10000 2650 9800 2650
Wire Wire Line
9800 2650 9800 2250
Wire Wire Line
9800 2250 8100 2250
Wire Wire Line
8100 2250 8100 2750
Wire Wire Line
8100 2750 8400 2750
Wire Wire Line
9500 2650 9650 2650
Wire Wire Line
9650 2650 9650 2850
Wire Wire Line
9650 2850 10000 2850
NoConn ~ 7450 2850
NoConn ~ 6350 2850
NoConn ~ 4400 2100
NoConn ~ 3300 2100
$Comp
L ISO7816_CARD SIM1
U 1 1 4E0085A5
P 5900 4000
F 0 "SIM1" H 5900 4250 60 0000 C CNN
F 1 "ISO7816_CARD" H 5900 3750 60 0000 C CNN
1 5900 4000
1 0 0 -1
$EndComp
$Comp
L FFC P3
L FFC P_DOWN2
U 1 1 4E0084E2
P 5900 5250
F 0 "P3" H 5950 5600 60 0000 C CNN
F 1 "FFC" V 6100 5250 60 0000 C CNN
1 5900 5250
P 3850 3050
F 0 "P_DOWN2" H 3900 3400 60 0000 C CNN
F 1 "FFC" V 4050 3050 60 0000 C CNN
1 3850 3050
0 1 1 0
$EndComp
NoConn ~ 1300 3250
NoConn ~ 2400 3250
$Comp
L FFC P2
U 1 1 4E0084DD
P 7550 4000
F 0 "P2" H 7600 4350 60 0000 C CNN
F 1 "FFC" V 7750 4000 60 0000 C CNN
1 7550 4000
L ISO7816_CARD SIM_RIGHT4
U 1 1 4E0ED4DB
P 8950 2700
F 0 "SIM_RIGHT4" H 8950 2950 60 0000 C CNN
F 1 "ISO7816_CARD" H 8950 2450 60 0000 C CNN
1 8950 2700
1 0 0 -1
$EndComp
$Comp
L FFC P1
L ISO7816_CARD SIM_LEFT3
U 1 1 4E0ED4DA
P 6900 2700
F 0 "SIM_LEFT3" H 6900 2950 60 0000 C CNN
F 1 "ISO7816_CARD" H 6900 2450 60 0000 C CNN
1 6900 2700
1 0 0 -1
$EndComp
$Comp
L ISO7816_CARD SIM_DOWN2
U 1 1 4E0ED4A7
P 3850 1950
F 0 "SIM_DOWN2" H 3850 2200 60 0000 C CNN
F 1 "ISO7816_CARD" H 3850 1700 60 0000 C CNN
1 3850 1950
1 0 0 -1
$EndComp
$Comp
L ISO7816_CARD SIM_UP1
U 1 1 4E0085A5
P 1850 3100
F 0 "SIM_UP1" H 1850 3350 60 0000 C CNN
F 1 "ISO7816_CARD" H 1850 2850 60 0000 C CNN
1 1850 3100
1 0 0 -1
$EndComp
$Comp
L FFC P_RIGHT4
U 1 1 4E0084DD
P 10350 2700
F 0 "P_RIGHT4" H 10400 3050 60 0000 C CNN
F 1 "FFC" V 10550 2700 60 0000 C CNN
1 10350 2700
1 0 0 -1
$EndComp
$Comp
L FFC P_UP1
U 1 1 4E0084D9
P 5900 2750
F 0 "P1" H 5950 3100 60 0000 C CNN
F 1 "FFC" V 6100 2750 60 0000 C CNN
1 5900 2750
P 1850 1950
F 0 "P_UP1" H 1900 2300 60 0000 C CNN
F 1 "FFC" V 2050 1950 60 0000 C CNN
1 1850 1950
0 -1 -1 0
$EndComp
$Comp
L FFC P4
L FFC P_LEFT3
U 1 1 4E0084D4
P 4200 4000
F 0 "P4" H 4250 4350 60 0000 C CNN
F 1 "FFC" V 4400 4000 60 0000 C CNN
1 4200 4000
P 5450 2700
F 0 "P_LEFT3" H 5500 3050 60 0000 C CNN
F 1 "FFC" V 5650 2700 60 0000 C CNN
1 5450 2700
-1 0 0 1
$EndComp
NoConn ~ 5350 4150
NoConn ~ 6450 4150
Text Label 5650 3150 3 60 ~ 0
VCC
Text Label 5750 3150 3 60 ~ 0
RST
Text Label 5850 3150 3 60 ~ 0
CLK
Text Label 5950 3150 3 60 ~ 0
I/O
Text Label 6050 3150 3 60 ~ 0
VPP
Text Label 6150 3150 3 60 ~ 0
GND
Text Label 5650 4800 1 60 ~ 0
GND
Text Label 5750 4800 1 60 ~ 0
VPP
Text Label 5850 4800 1 60 ~ 0
I/O
Text Label 5950 4800 1 60 ~ 0
CLK
Text Label 6050 4800 1 60 ~ 0
RST
Text Label 6150 4800 1 60 ~ 0
VCC
Text Label 7000 4250 0 60 ~ 0
GND
Text Label 7000 4150 0 60 ~ 0
VPP
Text Label 7000 4050 0 60 ~ 0
I/O
Text Label 7000 3950 0 60 ~ 0
CLK
Text Label 7000 3850 0 60 ~ 0
RST
Text Label 7000 3750 0 60 ~ 0
VCC
Text Label 6500 4050 0 60 ~ 0
I/O
Text Label 6500 3950 0 60 ~ 0
VPP
Text Label 6500 3850 0 60 ~ 0
GND
Text Label 5150 4050 0 60 ~ 0
CLK
Text Label 5150 3950 0 60 ~ 0
RST
Text Label 5150 3850 0 60 ~ 0
VCC
Wire Wire Line
7200 4250 6950 4250
Wire Wire Line
7200 4050 6950 4050
Wire Wire Line
7200 3850 6950 3850
Wire Wire Line
6050 3100 6050 3350
Wire Wire Line
5850 3100 5850 3350
Wire Wire Line
5650 3100 5650 3350
Wire Wire Line
6700 4050 6450 4050
Wire Wire Line
6450 3950 6700 3950
Wire Wire Line
5100 3950 5350 3950
Wire Wire Line
5650 4900 5650 4600
Wire Wire Line
5850 4900 5850 4600
Wire Wire Line
6050 4900 6050 4600
Wire Wire Line
4550 4250 4800 4250
Wire Wire Line
4550 4050 4800 4050
Wire Wire Line
4550 3850 4800 3850
Wire Wire Line
4550 3750 4800 3750
Wire Wire Line
4550 3950 4800 3950
Wire Wire Line
4550 4150 4800 4150
Wire Wire Line
6150 4900 6150 4600
Wire Wire Line
5950 4900 5950 4600
Wire Wire Line
5750 4900 5750 4600
Wire Wire Line
5100 3850 5350 3850
Wire Wire Line
5100 4050 5350 4050
Wire Wire Line
6450 3850 6700 3850
Wire Wire Line
5750 3100 5750 3350
Wire Wire Line
5950 3100 5950 3350
Wire Wire Line
6150 3100 6150 3350
Wire Wire Line
7200 3950 6950 3950
Wire Wire Line
7200 3750 6950 3750
Wire Wire Line
7200 4150 6950 4150
Text Label 4600 4250 0 60 ~ 0
VCC
Text Label 4600 4150 0 60 ~ 0
RST
Text Label 4600 4050 0 60 ~ 0
CLK
Text Label 4600 3950 0 60 ~ 0
I/O
Text Label 4600 3850 0 60 ~ 0
VPP
Text Label 4600 3750 0 60 ~ 0
GND
$EndSCHEMATC

1722
hardware/kicad/simffc.brd Normal file

File diff suppressed because it is too large Load Diff

76
hardware/kicad/simffc.net Normal file
View File

@@ -0,0 +1,76 @@
# EESchema Netlist Version 1.1 created Do 07 Jul 2011 13:03:35 CEST
(
( /4E158ACC FFC FFC1 FFC
( 1 /VCC1 )
( 2 /RST1 )
( 3 /CLK1 )
( 4 /I-O1 )
( 5 /VPP1 )
( 6 /GND1 )
)
( /4E159114 FFC FFC2 FFC
( 1 /VCC2 )
( 2 /RST2 )
( 3 /CLK2 )
( 4 /I-O2 )
( 5 /VPP2 )
( 6 /GND2 )
)
( /4E15911B FFC FFC3 FFC
( 1 /VCC3 )
( 2 /RST3 )
( 3 /CLK3 )
( 4 /I-O3 )
( 5 /VPP3 )
( 6 /GND3 )
)
( /4E159134 FFC FFC4 FFC
( 1 /VCC4 )
( 2 /RST4 )
( 3 /CLK4 )
( 4 /I-O4 )
( 5 /VPP4 )
( 6 /GND4 )
)
( /4E158AC1 SIM_LIGHT SIM1 ISO7816_CARD
( C1 /VCC1 )
( C2 /RST1 )
( C3 /CLK1 )
( C4 ? )
( C5 /GND1 )
( C6 /VPP1 )
( C7 /I-O1 )
( C8 ? )
)
( /4E159115 SIM_LIGHT SIM2 ISO7816_CARD
( C1 /VCC2 )
( C2 /RST2 )
( C3 /CLK2 )
( C4 ? )
( C5 /GND2 )
( C6 /VPP2 )
( C7 /I-O2 )
( C8 ? )
)
( /4E15911A SIM_LIGHT SIM3 ISO7816_CARD
( C1 /VCC3 )
( C2 /RST3 )
( C3 /CLK3 )
( C4 ? )
( C5 /GND3 )
( C6 /VPP3 )
( C7 /I-O3 )
( C8 ? )
)
( /4E159135 SIM_LIGHT SIM4 ISO7816_CARD
( C1 /VCC4 )
( C2 /RST4 )
( C3 /CLK4 )
( C4 ? )
( C5 /GND4 )
( C6 /VPP4 )
( C7 /I-O4 )
( C8 ? )
)
)
*

100
hardware/kicad/simffc.pro Normal file
View File

@@ -0,0 +1,100 @@
update=Do 07 Jul 2011 12:43:29 CEST
last_client=pcbnew
[eeschema]
version=1
LibDir=/media/data/gsm/sim/simtrace/hardware/kicad/lib
NetFmt=1
HPGLSpd=20
HPGLDm=15
HPGLNum=1
offX_A4=0
offY_A4=0
offX_A3=0
offY_A3=0
offX_A2=0
offY_A2=0
offX_A1=0
offY_A1=0
offX_A0=0
offY_A0=0
offX_A=0
offY_A=0
offX_B=0
offY_B=0
offX_C=0
offY_C=0
offX_D=0
offY_D=0
offX_E=0
offY_E=0
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=smartcard
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew]
version=1
PadDrlX=320
PadDimH=600
PadDimV=600
BoardThickness=630
TxtPcbV=800
TxtPcbH=600
TxtModV=600
TxtModH=600
TxtModW=120
VEgarde=100
DrawLar=150
EdgeLar=150
TxtLar=120
MSegLar=150
LastNetListRead=simffc.net
[pcbnew/libraries]
LibDir=
LibName1=sockets
LibName2=connect
LibName3=discret
LibName4=pin_array
LibName5=divers
LibName6=libcms
LibName7=display
LibName8=valves
LibName9=led
LibName10=dip_sockets
LibName11=lib/smartcard

367
hardware/kicad/simffc.sch Normal file
View File

@@ -0,0 +1,367 @@
EESchema Schematic File Version 2 date Do 07 Jul 2011 13:03:38 CEST
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:smartcard
EELAYER 25 0
EELAYER END
$Descr A4 11700 8267
encoding utf-8
Sheet 1 1
Title "noname.sch"
Date "7 jul 2011"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Label 4450 1850 0 60 ~ 0
I-O2
Text Label 4450 1950 0 60 ~ 0
VPP2
Text Label 4450 2050 0 60 ~ 0
GND2
Text Label 3450 1850 0 60 ~ 0
CLK2
Text Label 3450 1950 0 60 ~ 0
RST2
Text Label 3450 2050 0 60 ~ 0
VCC2
Text Label 2550 1850 0 60 ~ 0
I-O1
Text Label 2550 1950 0 60 ~ 0
VPP1
Text Label 2550 2050 0 60 ~ 0
GND1
$Comp
L ISO7816_CARD SIM4
U 1 1 4E159135
P 7850 1250
F 0 "SIM4" H 7850 1500 60 0000 C CNN
F 1 "ISO7816_CARD" H 7850 1000 60 0000 C CNN
1 7850 1250
1 0 0 -1
$EndComp
$Comp
L FFC FFC4
U 1 1 4E159134
P 7850 2450
F 0 "FFC4" H 7900 2800 60 0000 C CNN
F 1 "FFC" V 8050 2450 60 0000 C CNN
1 7850 2450
0 -1 1 0
$EndComp
Text Label 7250 1850 0 60 ~ 0
CLK4
Text Label 7250 1950 0 60 ~ 0
RST4
Text Label 7250 2050 0 60 ~ 0
VCC4
Wire Wire Line
8650 1200 8650 1950
Wire Wire Line
7900 1850 8600 1850
Wire Wire Line
7900 1850 7900 2100
Wire Wire Line
7700 2100 7700 1950
Wire Wire Line
7700 1950 7050 1950
Wire Wire Line
7100 1300 7100 1850
Wire Wire Line
8400 1300 8600 1300
Wire Wire Line
8100 2100 8100 2050
Wire Wire Line
8100 2050 8700 2050
Wire Wire Line
8700 2050 8700 1100
Wire Wire Line
8700 1100 8400 1100
Wire Wire Line
7300 1200 7050 1200
Wire Wire Line
7300 1100 7000 1100
Wire Wire Line
7000 1100 7000 2050
Wire Wire Line
7000 2050 7600 2050
Wire Wire Line
7600 2050 7600 2100
Wire Wire Line
7100 1300 7300 1300
Wire Wire Line
8650 1200 8400 1200
Wire Wire Line
7100 1850 7800 1850
Wire Wire Line
7800 1850 7800 2100
Wire Wire Line
7050 1200 7050 1950
Wire Wire Line
8600 1300 8600 1850
Wire Wire Line
8000 2100 8000 1950
Wire Wire Line
8000 1950 8650 1950
Text Label 8250 1850 0 60 ~ 0
I-O4
Text Label 8250 1950 0 60 ~ 0
VPP4
Text Label 8250 2050 0 60 ~ 0
GND4
NoConn ~ 8400 1400
NoConn ~ 7300 1400
NoConn ~ 5400 1400
NoConn ~ 6500 1400
Text Label 6350 2050 0 60 ~ 0
GND3
Text Label 6350 1950 0 60 ~ 0
VPP3
Text Label 6350 1850 0 60 ~ 0
I-O3
Wire Wire Line
6100 1950 6750 1950
Wire Wire Line
6100 1950 6100 2100
Wire Wire Line
6700 1300 6700 1850
Wire Wire Line
5150 1200 5150 1950
Wire Wire Line
5900 2100 5900 1850
Wire Wire Line
5900 1850 5200 1850
Wire Wire Line
6500 1200 6750 1200
Wire Wire Line
5400 1300 5200 1300
Wire Wire Line
5700 2100 5700 2050
Wire Wire Line
5700 2050 5100 2050
Wire Wire Line
5100 2050 5100 1100
Wire Wire Line
5100 1100 5400 1100
Wire Wire Line
5150 1200 5400 1200
Wire Wire Line
6500 1100 6800 1100
Wire Wire Line
6800 1100 6800 2050
Wire Wire Line
6800 2050 6200 2050
Wire Wire Line
6200 2050 6200 2100
Wire Wire Line
6700 1300 6500 1300
Wire Wire Line
5200 1300 5200 1850
Wire Wire Line
5150 1950 5800 1950
Wire Wire Line
5800 1950 5800 2100
Wire Wire Line
6000 2100 6000 1850
Wire Wire Line
6000 1850 6700 1850
Wire Wire Line
6750 1200 6750 1950
Text Label 5350 2050 0 60 ~ 0
VCC3
Text Label 5350 1950 0 60 ~ 0
RST3
Text Label 5350 1850 0 60 ~ 0
CLK3
$Comp
L FFC FFC3
U 1 1 4E15911B
P 5950 2450
F 0 "FFC3" H 6000 2800 60 0000 C CNN
F 1 "FFC" V 6150 2450 60 0000 C CNN
1 5950 2450
0 -1 1 0
$EndComp
$Comp
L ISO7816_CARD SIM3
U 1 1 4E15911A
P 5950 1250
F 0 "SIM3" H 5950 1500 60 0000 C CNN
F 1 "ISO7816_CARD" H 5950 1000 60 0000 C CNN
1 5950 1250
1 0 0 -1
$EndComp
$Comp
L ISO7816_CARD SIM2
U 1 1 4E159115
P 4050 1250
F 0 "SIM2" H 4050 1500 60 0000 C CNN
F 1 "ISO7816_CARD" H 4050 1000 60 0000 C CNN
1 4050 1250
1 0 0 -1
$EndComp
$Comp
L FFC FFC2
U 1 1 4E159114
P 4050 2450
F 0 "FFC2" H 4100 2800 60 0000 C CNN
F 1 "FFC" V 4250 2450 60 0000 C CNN
1 4050 2450
0 -1 1 0
$EndComp
Wire Wire Line
4850 1200 4850 1950
Wire Wire Line
4100 1850 4800 1850
Wire Wire Line
4100 1850 4100 2100
Wire Wire Line
3900 2100 3900 1950
Wire Wire Line
3900 1950 3250 1950
Wire Wire Line
3300 1300 3300 1850
Wire Wire Line
4600 1300 4800 1300
Wire Wire Line
4300 2100 4300 2050
Wire Wire Line
4300 2050 4900 2050
Wire Wire Line
4900 2050 4900 1100
Wire Wire Line
4900 1100 4600 1100
Wire Wire Line
3500 1200 3250 1200
Wire Wire Line
3500 1100 3200 1100
Wire Wire Line
3200 1100 3200 2050
Wire Wire Line
3200 2050 3800 2050
Wire Wire Line
3800 2050 3800 2100
Wire Wire Line
3300 1300 3500 1300
Wire Wire Line
4850 1200 4600 1200
Wire Wire Line
3300 1850 4000 1850
Wire Wire Line
4000 1850 4000 2100
Wire Wire Line
3250 1200 3250 1950
Wire Wire Line
4800 1300 4800 1850
Wire Wire Line
4200 2100 4200 1950
Wire Wire Line
4200 1950 4850 1950
NoConn ~ 4600 1400
NoConn ~ 3500 1400
NoConn ~ 1600 1400
NoConn ~ 2700 1400
Wire Wire Line
2300 1950 2950 1950
Wire Wire Line
2300 1950 2300 2100
Wire Wire Line
2900 1300 2900 1850
Wire Wire Line
1350 1200 1350 1950
Wire Wire Line
2100 2100 2100 1850
Wire Wire Line
2100 1850 1400 1850
Wire Wire Line
2700 1200 2950 1200
Wire Wire Line
1600 1300 1400 1300
Wire Wire Line
1900 2100 1900 2050
Wire Wire Line
1900 2050 1300 2050
Wire Wire Line
1300 2050 1300 1100
Wire Wire Line
1300 1100 1600 1100
Wire Wire Line
1350 1200 1600 1200
Wire Wire Line
2700 1100 3000 1100
Wire Wire Line
3000 1100 3000 2050
Wire Wire Line
3000 2050 2400 2050
Wire Wire Line
2400 2050 2400 2100
Wire Wire Line
2900 1300 2700 1300
Wire Wire Line
1400 1300 1400 1850
Wire Wire Line
1350 1950 2000 1950
Wire Wire Line
2000 1950 2000 2100
Wire Wire Line
2200 2100 2200 1850
Wire Wire Line
2200 1850 2900 1850
Wire Wire Line
2950 1200 2950 1950
Text Label 1550 2050 0 60 ~ 0
VCC1
Text Label 1550 1950 0 60 ~ 0
RST1
Text Label 1550 1850 0 60 ~ 0
CLK1
$Comp
L FFC FFC1
U 1 1 4E158ACC
P 2150 2450
F 0 "FFC1" H 2200 2800 60 0000 C CNN
F 1 "FFC" V 2350 2450 60 0000 C CNN
1 2150 2450
0 -1 1 0
$EndComp
$Comp
L ISO7816_CARD SIM1
U 1 1 4E158AC1
P 2150 1250
F 0 "SIM1" H 2150 1500 60 0000 C CNN
F 1 "ISO7816_CARD" H 2150 1000 60 0000 C CNN
1 2150 1250
1 0 0 -1
$EndComp
$EndSCHEMATC

View File

@@ -0,0 +1,24 @@
G04 start of page 3 for group 2 idx 2 *
G04 Title: (unknown), border *
G04 Creator: pcb 20140316 *
G04 CreationDate: Fr 01 Apr 2016 10:35:00 GMT UTC *
G04 For: laforge *
G04 Format: Gerber/RS-274X *
G04 PCB-Dimensions (mil): 7874.02 5000.00 *
G04 PCB-Coordinate-Origin: lower left *
%MOIN*%
%FSLAX25Y25*%
%LNGROUP2*%
%ADD16C,0.0079*%
G54D16*X34075Y462350D02*X636426D01*
X34075Y434792D02*X636426D01*
X34075Y462350D02*Y434792D01*
X689586Y428893D02*X640374Y428886D01*
X699429Y438736D02*X689586Y428893D01*
X699429Y476137D02*Y438736D01*
X640374Y476137D02*X699429D01*
X640374Y466287D02*X640381Y476137D01*
X640374Y428886D02*Y430854D01*
X636426Y462350D02*G75*G03X640363Y466287I0J3937D01*G01*
Y430855D02*G75*G03X636426Y434792I-3937J0D01*G01*
M02*

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@@ -0,0 +1,26 @@
G04 start of page 5 for group -4079 idx -4079 *
G04 Title: (unknown), topsilk *
G04 Creator: pcb 20140316 *
G04 CreationDate: Fr 01 Apr 2016 11:10:24 GMT UTC *
G04 For: laforge *
G04 Format: Gerber/RS-274X *
G04 PCB-Dimensions (mil): 7874.02 5000.00 *
G04 PCB-Coordinate-Origin: lower left *
%MOIN*%
%FSLAX25Y25*%
%LNTOPSILK*%
%ADD19C,0.0079*%
G54D19*X689546Y429155D02*X640334D01*
X699389Y438998D02*X689546Y429155D01*
X699389Y476399D02*Y438998D01*
X640334Y429155D02*Y476392D01*
Y476399D02*X699389D01*
X34078Y434794D02*X65570D01*
X34078D02*X34075Y434792D01*
Y462352D02*Y434792D01*
Y462352D02*X34074Y462353D01*
X49820D01*
X65571Y462350D01*
X49823Y434796D02*X49825Y434794D01*
X65571Y462350D02*Y434796D01*
M02*

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@@ -0,0 +1,246 @@
G04 start of page 2 for group 0 idx 0 *
G04 Title: (unknown), component *
G04 Creator: pcb 20140316 *
G04 CreationDate: Fr 01 Apr 2016 11:10:24 GMT UTC *
G04 For: laforge *
G04 Format: Gerber/RS-274X *
G04 PCB-Dimensions (mil): 7874.02 5000.00 *
G04 PCB-Coordinate-Origin: lower left *
%MOIN*%
%FSLAX25Y25*%
%LNTOP*%
%ADD15R,0.0866X0.0866*%
%ADD14R,0.0354X0.0354*%
%ADD13C,0.0100*%
%ADD12C,0.0295*%
%ADD11C,0.0197*%
G54D11*X41949Y458413D02*X627579D01*
X41947Y450548D02*X627579Y450539D01*
X41949Y454476D02*X627579D01*
X41963Y438720D02*X627579Y438728D01*
X41949Y442666D02*X627579Y442665D01*
X41949Y446603D02*X627579Y446602D01*
G54D12*X626595D03*
X653718Y467746D02*X648723D01*
X639390Y458413D01*
X642343D02*Y461366D01*
X641358D01*
X638406Y458413D01*
X653718Y457904D02*X648723D01*
X653718Y448062D02*X647773D01*
X645295Y450539D01*
X648723Y457904D02*X645295Y454476D01*
X626595Y458413D02*X642343D01*
X640374Y459397D02*X636437D01*
X635453Y458413D01*
X681670Y467746D02*X693049D01*
X695492Y465303D01*
X691555Y454476D02*Y444634D01*
X695492Y465303D02*Y442665D01*
X681670Y448062D02*Y442623D01*
X679744Y440697D01*
X691555Y444634D02*X683681Y436760D01*
X695492Y442665D02*X685650Y432823D01*
X681670Y457904D02*X688128D01*
X691555Y454476D01*
X645295Y436760D02*X683681D01*
X643327Y432823D02*X685650D01*
X647264Y436760D02*X645295D01*
X626595Y454476D03*
Y450539D03*
X645295Y454476D02*X626595D01*
X645295Y450539D02*X626595D01*
X641358Y446602D02*X626595D01*
X679744Y440697D02*X647264D01*
X626595Y438728D02*X637421D01*
X643327Y432823D01*
X638406Y437744D02*X635453D01*
X634469Y438728D01*
X626595Y442665D02*X639390D01*
X645295Y436760D02*X639390Y442665D01*
X647264Y440697D02*X641358Y446602D01*
G54D13*X666762Y473788D02*Y471693D01*
X665238Y472836D01*
Y472264D01*
X665049Y471884D01*
X664858Y471693D01*
X664286Y471502D01*
X663906D02*X664286D01*
X663906D02*X663334Y471693D01*
X662953Y472073D01*
X662762Y472645D01*
Y473216D02*Y472645D01*
Y473216D02*X662953Y473788D01*
X663144Y473978D01*
X663524Y474168D01*
X662762Y470302D02*X666762D01*
Y467827D01*
X664857Y470302D02*Y468779D01*
X662762Y466627D02*X666762D01*
Y464152D01*
X664857Y466627D02*Y465104D01*
X664762Y462952D02*Y460452D01*
X666190Y456586D02*X666571Y456967D01*
X666762Y457538D01*
Y458300D02*Y457538D01*
Y458300D02*X666571Y458872D01*
X666190Y459252D01*
X665810D02*X666190D01*
X665810D02*X665428Y459063D01*
X665238Y458872D01*
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X664476Y456967D01*
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X663905Y456586D01*
X663333D02*X663905D01*
X663333D02*X662953Y456967D01*
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Y458300D02*Y457538D01*
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X662762Y454053D02*X666762D01*
Y455386D02*Y452720D01*
X664762Y451520D02*Y449020D01*
X666762Y446678D02*X666571Y447058D01*
X666190Y447440D01*
X665810Y447630D01*
X665238Y447820D01*
X664286D02*X665238D01*
X664286D02*X663713Y447630D01*
X663714D02*X663333Y447440D01*
X662953Y447058D01*
X662762Y446678D01*
Y445915D01*
X662953Y445535D01*
X663333Y445154D01*
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X664286Y444774D01*
X665238D01*
X665810Y444963D01*
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X666762Y445915D01*
Y446678D02*Y445915D01*
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Y474391D02*Y473820D01*
Y474391D02*X673111Y474963D01*
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X671968Y473629D01*
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X671397Y473058D01*
X671206D02*X671397D01*
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Y474391D02*Y473820D01*
Y474391D02*X670826Y474963D01*
X671206Y475152D01*
X673301Y471668D02*X670635Y470525D01*
X673301Y469382D02*X670635Y470525D01*
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X669492Y471286D01*
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Y471858D02*Y471668D01*
X672731Y466088D02*X673111Y466278D01*
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Y467421D02*Y466850D01*
Y467421D02*X673111Y467993D01*
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X672349Y467993D01*
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X671206D02*X670826Y466278D01*
X670635Y466850D01*
Y467421D02*Y466850D01*
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Y463365D01*
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Y461270D01*
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X672160Y459499D01*
X671778D02*X672160D01*
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Y457976D01*
X670826Y457595D01*
X671207Y457215D01*
X671778Y457024D01*
X672160D01*
X672731Y457215D01*
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X673301Y457976D01*
Y458547D02*Y457976D01*
X672731Y453538D02*X673112Y453920D01*
X673301Y454300D01*
Y454872D02*Y454300D01*
Y454872D02*X673112Y455252D01*
X672731Y455634D01*
X672160Y455824D01*
X671778D02*X672160D01*
X671778D02*X671207Y455634D01*
X670826Y455252D01*
X670635Y454872D01*
Y454300D01*
X670826Y453920D01*
X671207Y453538D01*
X673301Y451386D02*X673112Y451768D01*
X672731Y452149D01*
X672160Y452338D01*
X671778D02*X672160D01*
X671778D02*X671207Y452149D01*
X670826Y451768D01*
X670635Y451386D01*
Y450815D01*
X670826Y450434D01*
X671207Y450054D01*
X671778Y449863D01*
X672160D01*
X672731Y450054D01*
X673112Y450434D01*
X673301Y450815D01*
Y451386D02*Y450815D01*
X670635Y448663D02*X673301D01*
X672540D02*X673112Y448093D01*
X673301Y447711D01*
Y447140D01*
X673112Y446759D01*
X672540Y446569D01*
X670635D02*X672540D01*
X673112Y445997D01*
X673301Y445617D01*
Y445045D01*
X673112Y444665D01*
X672540Y444474D01*
X670635D02*X672540D01*
G54D14*X35847Y438729D02*X48051D01*
G54D15*X680883Y448062D02*X682458D01*
X680883Y457904D02*X682458D01*
X680883Y467746D02*X682458D01*
X652931Y448062D02*X654506D01*
X652931Y457904D02*X654506D01*
X652931Y467746D02*X654506D01*
G54D14*X35847Y442666D02*X48051D01*
X35847Y446603D02*X48051D01*
X35847Y450539D02*X48051D01*
X35847Y454476D02*X48051D01*
X35847Y458413D02*X48051D01*
M02*

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@@ -0,0 +1,26 @@
G04 start of page 4 for group -4063 idx -4063 *
G04 Title: (unknown), componentmask *
G04 Creator: pcb 20140316 *
G04 CreationDate: Fr 01 Apr 2016 11:10:24 GMT UTC *
G04 For: laforge *
G04 Format: Gerber/RS-274X *
G04 PCB-Dimensions (mil): 7874.02 5000.00 *
G04 PCB-Coordinate-Origin: lower left *
%MOIN*%
%FSLAX25Y25*%
%LNTOPMASK*%
%ADD18R,0.1066X0.1066*%
%ADD17R,0.0433X0.0433*%
G54D17*X35847Y438729D02*X48051D01*
G54D18*X680883Y448062D02*X682458D01*
X680883Y457904D02*X682458D01*
X680883Y467746D02*X682458D01*
X652931Y448062D02*X654506D01*
X652931Y457904D02*X654506D01*
X652931Y467746D02*X654506D01*
G54D17*X35847Y442666D02*X48051D01*
X35847Y446603D02*X48051D01*
X35847Y450539D02*X48051D01*
X35847Y454476D02*X48051D01*
X35847Y458413D02*X48051D01*
M02*

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