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qmod: Don't violate PLL minimum output frequency

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Table 42-31 ofd DOC6500 states that the minimum output frequency of the
PLL is 60 MHz.   The existing qmod code violated this by configuring the
PLL multiplier output to 12*4 = 48 MHz.  Let's use 12*8 = 96 and then
divide that by two to get to the desired 48 MHz.

This might help to resolve the non-working USB on the qmod so far.
This commit is contained in:
Harald Welte
2017-01-12 11:07:04 +01:00
parent b871363be7
commit 7861132fad
1 changed files with 3 additions and 3 deletions
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6
firmware/src_board/board_lowlevel.c
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@@ -53,11 +53,11 @@
| CKGR_PLLAR_DIVA(0x5))
#define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
#else /* qmod */
/* QMod has 12 MHz clock, so multply by 4 and divide by 1 */
/* QMod has 12 MHz clock, so multply by 8 (96 MHz) and divide by 2 */
#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
| CKGR_PLLAR_MULA(4-1) \
| CKGR_PLLAR_MULA(8-1) \
| CKGR_PLLAR_PLLACOUNT(0x1) \
| CKGR_PLLAR_DIVA(1))
| CKGR_PLLAR_DIVA(2))
#define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
#endif
/* Clock settings at 64MHz for 18 MHz crystal */