Rearrange the repository and add a library.properties file to make this installable as a .ZIP library in the Arduino IDE.

LICENSE

@@ -1,4 +1,4 @@
-Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham
+Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021,2022,2023 Andrew Gillham
 All rights reserved.
 
 Redistribution and use in source and binary forms, with or without

README.md

@@ -14,6 +14,17 @@ LED pin for an input.
 On the Arduino Mega board 8 channels are supported and 7k of samples.
 Pins 22-29 (Port A) are used by default.
 
+Installation
+============
+
+You can use the GitHub 'Download ZIP' feature to get an installable "library"
+for use with the Arduino IDE.  Select 'Sketch -> Include Library -> Add .ZIP Libary'
+from the Arduino IDE 2.x and select the zip file you downloaded from GitHub, then select open.
+
+Once installed you can use the 'File -> Examples -> LogicAnalyzer' menu to find
+different versions of the sketches.  You might want to start with `logic_analyzer_sigrok`
+and use PulseView.
+
 Client Software
 ===============
 

examples/logic_analyzer/logic_analyzer.ino

@@ -62,7 +62,7 @@
  * until after the trigger fires.
  * Please try it out and report back.
  *
- * Release: v0.16 October 3, 2023.
+ * Release: v0.17 October 5, 2023.
  *
  */
 
@@ -949,7 +949,7 @@ void get_metadata() {
   Serial.write('0');
   Serial.write('.');
   Serial.write('1');
-  Serial.write('6');
+  Serial.write('7');
   Serial.write((uint8_t)0x00);
 
   /* sample memory */

examples/logic_analyzer/logic_analyzer_inline_2mhz.ino

@@ -2,7 +2,7 @@
  *
  * SUMP Protocol Implementation for Arduino boards.
  *
- * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham
+ * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021,2022,2023 Andrew Gillham
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without

examples/logic_analyzer/logic_analyzer_inline_4mhz.ino

@@ -2,7 +2,7 @@
  *
  * SUMP Protocol Implementation for Arduino boards.
  *
- * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham
+ * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021,2022,2023 Andrew Gillham
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without

examples/logic_analyzer_leonardo/logic_analyzer_inline_2mhz.ino

@@ -2,7 +2,7 @@
  *
  * SUMP Protocol Implementation for Arduino boards.
  *
- * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham
+ * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021,2022,2023 Andrew Gillham
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without

examples/logic_analyzer_leonardo/logic_analyzer_inline_4mhz.ino

@@ -2,7 +2,7 @@
  *
  * SUMP Protocol Implementation for Arduino boards.
  *
- * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham
+ * Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021,2022,2023 Andrew Gillham
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without

examples/logic_analyzer_leonardo/logic_analyzer_leonardo.ino

@@ -62,7 +62,7 @@
  * until after the trigger fires.
  * Please try it out and report back.
  *
- * Release: v0.16 October 3, 2023.
+ * Release: v0.17 October 5, 2023.
  *
  */
 
@@ -918,7 +918,7 @@ void get_metadata() {
   Serial.write('0');
   Serial.write('.');
   Serial.write('1');
-  Serial.write('6');
+  Serial.write('7');
   Serial.write((uint8_t)0x00);
 
   /* sample memory */

examples/logic_analyzer_sigrok/logic_analyzer_sigrok.ino

@@ -62,7 +62,7 @@
  * until after the trigger fires.
  * Please try it out and report back.
  *
- * Release: v0.16 October 3, 2023.
+ * Release: v0.17 October 5, 2023.
  *
  */
 
@@ -949,7 +949,7 @@ void get_metadata() {
   Serial.write('0');
   Serial.write('.');
   Serial.write('1');
-  Serial.write('6');
+  Serial.write('7');
   Serial.write((uint8_t)0x00);
 
   /* sample memory */

library.properties

@@ -0,0 +1,9 @@
+name=LogicAnalyzer
+version=0.17.0
+author=Andrew Gillham <gillham@roadsign.com>
+maintainer=Andrew Gillham <gillham@roadsign.com>
+sentence=A SUMP protocol compatible logic analyzer firmware
+paragraph=These firmware sketches provide a 6 channel logic analyzer for use with the SUMP protocol based OLS clients. There is also a Sigrok compatible firmware using the OpenBench Logic Sniffer (ols) driver .
+category=Signal Input/Output
+url=https://github.com/gillham/logic_analyzer
+architectures=avr

logic_analyzer/LICENSE

@@ -1,22 +0,0 @@
-Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY ANDREW GILLHAM ``AS IS'' AND ANY EXPRESS OR
-IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL ANDREW GILLHAM BE LIABLE FOR ANY DIRECT, INDIRECT,
-INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

logic_analyzer_leonardo/LICENSE

@@ -1,22 +0,0 @@
-Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY ANDREW GILLHAM ``AS IS'' AND ANY EXPRESS OR
-IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL ANDREW GILLHAM BE LIABLE FOR ANY DIRECT, INDIRECT,
-INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

logic_analyzer_sigrok/LICENSE

@@ -1,22 +0,0 @@
-Copyright (c) 2011,2012,2013,2014,2015,2016,2017,2018,2019,2020,2021 Andrew Gillham
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY ANDREW GILLHAM ``AS IS'' AND ANY EXPRESS OR
-IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL ANDREW GILLHAM BE LIABLE FOR ANY DIRECT, INDIRECT,
-INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

src/use_examples_for_logic_analyzer.h

@@ -0,0 +1,2 @@
+// This is a placeholder. Use File->Examples->LogicAnalyzer menu
+// for the logic analyzer sketches.